Apple Microarchitecture Research by Dougall Johnson M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions M1/A14 E-core (Icestorm): Overview | Base Instructions | SIMD and FP Instructions
Code:
st2 { v0.2s, v1.2s }, [x6], x8 nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop
mov x0, 0 mov x8, 0
(no loop instructions)
Retires (minus 60 nops): 2.000
Issues: 3.000
Integer unit issues: 1.000
Load/store unit issues: 1.000
SIMD/FP unit issues: 1.000
retire uop (01) | cycle (02) | 03 | l1i tlb fill (04) | mmu table walk instruction (07) | l2 tlb miss instruction (0a) | 18 | 19 | 1e | 1f | 22 | 24 | 3a | 3f | 46 | 51 | schedule uop (52) | schedule int uop (53) | schedule simd uop (54) | schedule ldst uop (55) | dispatch int uop (56) | dispatch simd uop (57) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | ldst uops in schedulers (5b) | 5f | 60 | 61 | 69 | 6d | 6e | map rewind (75) | map stall (76) | dispatch uop (78) | map ldst uop (7d) | map simd uop (7e) | map ldst uop inputs (80) | map simd uop inputs (81) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst simd store (99) | inst ldst (9b) | l1d tlb access (a0) | l1d tlb miss (a1) | l1d cache miss st (a2) | ld unit uop (a6) | st unit uop (a7) | l1d cache writeback (a8) | ac | af | l1d cache miss st nonspec (c0) | c2 | cf | d0 | d2 | l1i cache miss demand (d3) | l1i tlb miss demand (d4) | d5 | map dispatch bubble (d6) | d9 | da | db | dd | fetch restart (de) | e0 | ? int output thing (e9) | ea | eb | ec | ? ldst retires (ed) | ? simd retires (ee) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
62006 | 29415 | 236 | 5 | 1 | 3 | 13 | 12 | 1593 | 968 | 0 | 0 | 4380 | 29164 | 0 | 18448 | 3009 | 1002 | 1005 | 1005 | 1007 | 1001 | 1004 | 5000 | 10906 | 8000 | 10 | 1 | 0 | 21714 | 28821 | 28852 | 3 | 10 | 3000 | 1000 | 1000 | 3000 | 2000 | 28678 | 28811 | 1 | 1 | 61001 | 1000 | 1000 | 1000 | 0 | 2 | 0 | 1000 | 0 | 0 | 1000 | 2 | 0 | 13351 | 9677 | 6993 | 3197 | 0 | 62 | 20077 | 3188 | 3820 | 23 | 58 | 62 | 28338 | 1000 | 15420 | 12603 | 13765 | 1000 | 1000 | 1000 | 28589 | 28687 | 28686 | 28590 | 28773 |
62004 | 28675 | 223 | 0 | 2 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 4713 | 28710 | 0 | 17658 | 3000 | 1000 | 1000 | 1000 | 1000 | 1002 | 1000 | 5000 | 10914 | 8000 | 2 | 0 | 0 | 21731 | 28544 | 28884 | 3 | 10 | 3000 | 1000 | 1000 | 3000 | 2000 | 28657 | 28719 | 1 | 1 | 61001 | 1000 | 1000 | 1000 | 0 | 2 | 0 | 1000 | 0 | 0 | 1000 | 2 | 0 | 13162 | 9361 | 6938 | 3105 | 0 | 59 | 20327 | 3214 | 3815 | 9 | 62 | 68 | 28441 | 1000 | 15624 | 13022 | 14142 | 1000 | 1000 | 1000 | 28891 | 28971 | 28933 | 28973 | 28953 |
62004 | 28915 | 231 | 0 | 0 | 2 | 0 | 0 | 0 | 1 | 0 | 0 | 4639 | 28888 | 0 | 17844 | 3000 | 1000 | 1000 | 1000 | 1000 | 1000 | 1000 | 5000 | 10906 | 8000 | 5 | 0 | 0 | 21687 | 28653 | 28976 | 3 | 10 | 3000 | 1001 | 1000 | 3000 | 2000 | 28964 | 29012 | 1 | 1 | 61001 | 1000 | 1000 | 1000 | 0 | 0 | 0 | 1000 | 0 | 0 | 1000 | 2 | 2 | 13168 | 9069 | 6888 | 3148 | 0 | 63 | 20295 | 3231 | 3821 | 18 | 61 | 61 | 28536 | 1000 | 15776 | 13052 | 13865 | 1000 | 1000 | 1000 | 28927 | 28980 | 29081 | 28956 | 28852 |
62004 | 29208 | 232 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 4748 | 29055 | 0 | 18055 | 3000 | 1000 | 1000 | 1001 | 1000 | 1000 | 1000 | 5000 | 10907 | 8000 | 6 | 0 | 0 | 21746 | 28516 | 28917 | 3 | 10 | 3000 | 1000 | 1000 | 3000 | 2000 | 28846 | 28790 | 1 | 1 | 61001 | 1000 | 1000 | 1000 | 0 | 2 | 0 | 1000 | 0 | 0 | 1000 | 0 | 0 | 13282 | 9302 | 6901 | 3160 | 1 | 61 | 20142 | 3219 | 3823 | 19 | 59 | 63 | 28219 | 1000 | 15613 | 12893 | 13712 | 1000 | 1000 | 1000 | 28700 | 28852 | 28856 | 28860 | 28776 |
62004 | 28779 | 223 | 0 | 1 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 4664 | 28688 | 0 | 17767 | 3000 | 1000 | 1000 | 1000 | 1001 | 1000 | 1000 | 5000 | 10892 | 8000 | 2 | 0 | 0 | 21705 | 28572 | 28862 | 3 | 10 | 3000 | 1000 | 1000 | 3000 | 2000 | 28844 | 28787 | 1 | 1 | 61001 | 1000 | 1000 | 1000 | 9 | 2 | 0 | 1000 | 0 | 0 | 1000 | 2 | 0 | 13358 | 9478 | 6962 | 3118 | 1 | 61 | 20184 | 3127 | 3816 | 18 | 58 | 63 | 28288 | 1000 | 15843 | 12818 | 13755 | 1000 | 1000 | 1000 | 28809 | 28836 | 28832 | 28842 | 28951 |
62004 | 28694 | 223 | 0 | 2 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 4730 | 28640 | 0 | 17817 | 3000 | 1000 | 1000 | 1000 | 1000 | 1000 | 1000 | 5000 | 10906 | 8000 | 2 | 0 | 0 | 21780 | 28503 | 28723 | 3 | 10 | 3003 | 1000 | 1000 | 3003 | 2000 | 28728 | 28743 | 1 | 1 | 61001 | 1000 | 1000 | 1000 | 0 | 2 | 2 | 1000 | 0 | 0 | 1001 | 2 | 0 | 13139 | 9272 | 6901 | 3145 | 0 | 62 | 20072 | 3181 | 3822 | 23 | 59 | 60 | 28333 | 1000 | 15598 | 12717 | 14064 | 1000 | 1000 | 1000 | 28841 | 28845 | 28736 | 28825 | 28749 |
62004 | 28829 | 223 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 4650 | 28703 | 1 | 17760 | 3000 | 1000 | 1000 | 1000 | 1000 | 1000 | 1000 | 5000 | 10902 | 8000 | 3 | 0 | 0 | 21711 | 28567 | 28860 | 3 | 10 | 3000 | 1000 | 1000 | 3000 | 2000 | 28770 | 28852 | 1 | 1 | 61001 | 1000 | 1000 | 1000 | 2 | 2 | 0 | 1000 | 0 | 0 | 1000 | 0 | 0 | 13256 | 9684 | 6961 | 3159 | 1 | 59 | 20219 | 3160 | 3828 | 18 | 63 | 62 | 28340 | 1000 | 15771 | 12462 | 13890 | 1000 | 1000 | 1000 | 28661 | 28730 | 28799 | 28760 | 28773 |
62004 | 28837 | 222 | 0 | 3 | 2 | 0 | 0 | 0 | 1 | 0 | 0 | 4613 | 28675 | 0 | 17777 | 3000 | 1000 | 1000 | 1000 | 1000 | 1000 | 1000 | 5000 | 10904 | 8000 | 4 | 0 | 0 | 21729 | 28607 | 28759 | 3 | 10 | 3000 | 1000 | 1000 | 3000 | 2000 | 28720 | 28728 | 1 | 1 | 61001 | 1000 | 1000 | 1000 | 0 | 2 | 0 | 1000 | 0 | 0 | 1000 | 2 | 0 | 13142 | 9229 | 6979 | 3179 | 0 | 60 | 20153 | 3311 | 3818 | 20 | 60 | 57 | 28204 | 1000 | 15710 | 12777 | 13979 | 1000 | 1000 | 1000 | 28694 | 28819 | 28846 | 28855 | 28726 |
62004 | 28817 | 223 | 0 | 2 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 4629 | 28647 | 0 | 17789 | 3000 | 1000 | 1000 | 1000 | 1000 | 1000 | 1000 | 5000 | 10907 | 8000 | 2 | 0 | 8 | 21713 | 28523 | 28810 | 3 | 10 | 3000 | 1000 | 1000 | 3000 | 2000 | 28727 | 28821 | 1 | 1 | 61001 | 1000 | 1000 | 1000 | 0 | 2 | 0 | 1000 | 0 | 0 | 1000 | 2 | 0 | 13294 | 9267 | 6916 | 3247 | 1 | 63 | 20171 | 3130 | 3820 | 21 | 55 | 71 | 28341 | 1000 | 15926 | 12819 | 13813 | 1000 | 1000 | 1000 | 28705 | 28720 | 28872 | 28775 | 28808 |
62004 | 28795 | 223 | 0 | 2 | 3 | 0 | 0 | 0 | 1 | 0 | 0 | 4786 | 28849 | 0 | 17841 | 3000 | 1000 | 1000 | 1000 | 1000 | 1000 | 1000 | 5000 | 10899 | 8000 | 1 | 0 | 8 | 21755 | 28314 | 28717 | 3 | 10 | 3000 | 1000 | 1000 | 3000 | 2000 | 28699 | 28568 | 1 | 1 | 61001 | 1000 | 1000 | 1000 | 0 | 2 | 0 | 1000 | 0 | 0 | 1000 | 2 | 0 | 13268 | 9500 | 6971 | 3125 | 1 | 57 | 20246 | 3253 | 3819 | 11 | 58 | 58 | 28113 | 1000 | 15734 | 12730 | 13577 | 1000 | 1000 | 1000 | 28701 | 28651 | 28621 | 28682 | 28836 |
Count: 8
Code:
st2 { v0.2s, v1.2s }, [x6], x8 st2 { v0.2s, v1.2s }, [x6], x8 st2 { v0.2s, v1.2s }, [x6], x8 st2 { v0.2s, v1.2s }, [x6], x8 st2 { v0.2s, v1.2s }, [x6], x8 st2 { v0.2s, v1.2s }, [x6], x8 st2 { v0.2s, v1.2s }, [x6], x8 st2 { v0.2s, v1.2s }, [x6], x8
mov x7, x6 mov x8, x6 mov x9, x6 mov x10, x6 mov x11, x6 mov x12, x6 mov x13, x6 mov x8, 0
(fused SUBS/B.cc loop)
Result (median cycles for code divided by count): 1.0005
retire uop (01) | cycle (02) | 03 | l1d tlb fill (05) | mmu table walk data (08) | 09 | l2 tlb miss data (0b) | 18 | 19 | 1e | 1f | 23 | 24 | 37 | 3a | 3f | 46 | 49 | 4f | 51 | schedule uop (52) | schedule int uop (53) | schedule simd uop (54) | schedule ldst uop (55) | dispatch int uop (56) | dispatch simd uop (57) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | ldst uops in schedulers (5b) | 60 | 69 | 6b | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map simd uop (7e) | map int uop inputs (7f) | map ldst uop inputs (80) | map simd uop inputs (81) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int alu (97) | inst simd store (99) | inst ldst (9b) | 9f | l1d tlb access (a0) | l1d tlb miss (a1) | l1d cache miss st (a2) | a4 | ld unit uop (a6) | st unit uop (a7) | l1d cache writeback (a8) | a9 | ac | af | bc | l1d cache miss st nonspec (c0) | l1d tlb miss nonspec (c1) | c2 | branch cond mispred nonspec (c5) | branch mispred nonspec (cb) | cd | cf | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ? int output thing (e9) | ? ldst retires (ed) | ? simd retires (ee) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
160206 | 80040 | 642 | 1 | 0 | 1 | 0 | 0 | 0 | 12 | 9 | 0 | 0 | 2442 | 1 | 80025 | 9 | 9 | 2 | 25 | 241854 | 80100 | 82532 | 80180 | 83120 | 82433 | 80000 | 4358990 | 3758848 | 642064 | 0 | 80015 | 0 | 80040 | 80040 | 59924 | 3 | 59998 | 240100 | 200 | 80000 | 80000 | 200 | 240000 | 160000 | 80040 | 80040 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 80000 | 0 | 21 | 0 | 0 | 80001 | 0 | 0 | 3 | 80001 | 8 | 29 | 7 | 0 | 0 | 0 | 0 | 5110 | 1 | 16 | 1 | 1 | 80037 | 80091 | 80000 | 80000 | 80100 | 80041 | 80041 | 80041 | 80041 | 80041 |
160204 | 80040 | 621 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1035 | 0 | 80025 | 8 | 8 | 3 | 25 | 245273 | 80100 | 81756 | 80000 | 80100 | 80000 | 80000 | 4358994 | 3758848 | 640483 | 1 | 80015 | 0 | 80040 | 80040 | 59924 | 3 | 59998 | 240100 | 202 | 80000 | 80000 | 200 | 240000 | 160000 | 80040 | 80040 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 80007 | 7 | 0 | 0 | 1 | 80007 | 0 | 0 | 10 | 80001 | 1 | 21 | 0 | 0 | 0 | 0 | 0 | 5110 | 1 | 16 | 1 | 2 | 80037 | 80000 | 80000 | 80000 | 80100 | 80041 | 80164 | 80041 | 80041 | 80041 |
160204 | 80040 | 620 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 7 | 0 | 1 | 135 | 1 | 80025 | 0 | 9 | 2 | 25 | 242150 | 80100 | 85149 | 80000 | 80100 | 80000 | 80108 | 4358990 | 3758848 | 644320 | 0 | 80015 | 0 | 80040 | 80040 | 59988 | 3 | 59998 | 240100 | 200 | 80000 | 80000 | 200 | 240000 | 160000 | 80040 | 80040 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 80067 | 0 | 21 | 0 | 0 | 80001 | 0 | 0 | 1 | 80001 | 8 | 29 | 7 | 0 | 0 | 0 | 0 | 5110 | 1 | 16 | 1 | 1 | 80037 | 80000 | 80000 | 80000 | 80100 | 80041 | 80041 | 80041 | 80041 | 80041 |
160204 | 80040 | 621 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 848 | 0 | 80025 | 8 | 8 | 1 | 25 | 244403 | 80100 | 80100 | 80000 | 80100 | 80000 | 80000 | 4358994 | 3758848 | 655648 | 0 | 80015 | 0 | 80040 | 80040 | 59924 | 3 | 59998 | 240100 | 200 | 80000 | 80000 | 200 | 240000 | 160000 | 80040 | 80040 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 80007 | 7 | 29 | 0 | 1 | 80008 | 0 | 0 | 11 | 80001 | 1 | 21 | 0 | 0 | 0 | 0 | 0 | 5110 | 1 | 16 | 1 | 1 | 80037 | 80000 | 80000 | 80000 | 80100 | 80041 | 80041 | 80041 | 80041 | 80041 |
160204 | 80040 | 620 | 1 | 0 | 1 | 1 | 0 | 0 | 12 | 9 | 0 | 0 | 2057 | 1 | 80025 | 9 | 9 | 5 | 25 | 240261 | 80100 | 80186 | 80000 | 80216 | 80000 | 80000 | 4359002 | 3758848 | 641635 | 0 | 80015 | 0 | 80161 | 80040 | 59924 | 3 | 59998 | 240100 | 200 | 80000 | 80000 | 200 | 240000 | 160000 | 80040 | 80040 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 80000 | 0 | 21 | 0 | 0 | 80001 | 0 | 0 | 3 | 80001 | 8 | 29 | 7 | 0 | 0 | 0 | 0 | 5110 | 1 | 16 | 1 | 1 | 80037 | 80000 | 80000 | 80000 | 80100 | 80041 | 80041 | 80041 | 80041 | 80164 |
160204 | 80040 | 620 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 849 | 0 | 80025 | 8 | 8 | 0 | 25 | 244402 | 80100 | 81160 | 80000 | 80100 | 80000 | 80000 | 4358990 | 3758848 | 646632 | 0 | 80015 | 0 | 80040 | 80040 | 59924 | 3 | 59998 | 240100 | 200 | 80000 | 80000 | 200 | 240000 | 160000 | 80040 | 80040 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 80008 | 8 | 30 | 0 | 3 | 81507 | 0 | 0 | 8 | 80001 | 2 | 21 | 0 | 0 | 0 | 0 | 0 | 5110 | 1 | 16 | 1 | 1 | 80037 | 80000 | 80000 | 80000 | 80100 | 80041 | 80041 | 80041 | 80041 | 80041 |
160204 | 80040 | 620 | 1 | 1 | 1 | 2 | 0 | 0 | 0 | 12 | 0 | 0 | 1264 | 1 | 80025 | 9 | 9 | 6 | 25 | 240219 | 80100 | 82322 | 80000 | 80100 | 80000 | 80000 | 4358994 | 3758848 | 655556 | 0 | 80015 | 0 | 80040 | 80040 | 59924 | 3 | 59998 | 240100 | 200 | 80000 | 80000 | 200 | 240000 | 160000 | 80040 | 80040 | 2 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 80000 | 0 | 21 | 0 | 0 | 80001 | 0 | 0 | 0 | 80001 | 1 | 21 | 0 | 0 | 0 | 0 | 0 | 5110 | 1 | 16 | 1 | 1 | 80037 | 80000 | 80000 | 80000 | 80100 | 80041 | 80041 | 80041 | 80041 | 80041 |
160204 | 80040 | 620 | 1 | 0 | 0 | 1 | 0 | 0 | 39 | 9 | 0 | 0 | 2041 | 1 | 80025 | 0 | 9 | 2 | 25 | 245226 | 80100 | 84289 | 80000 | 80100 | 80000 | 80000 | 4358994 | 3758848 | 642624 | 0 | 80015 | 0 | 80040 | 80040 | 59924 | 13 | 59998 | 240100 | 200 | 80000 | 80000 | 200 | 240000 | 160000 | 80040 | 80040 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 80000 | 0 | 21 | 27 | 0 | 80001 | 1 | 0 | 0 | 80001 | 8 | 29 | 7 | 1 | 0 | 0 | 0 | 5110 | 1 | 16 | 1 | 1 | 80037 | 80000 | 80000 | 80000 | 80100 | 80041 | 80041 | 80041 | 80041 | 80041 |
160204 | 80040 | 620 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0 | 1 | 1033 | 0 | 80025 | 8 | 8 | 3 | 25 | 241135 | 80100 | 80896 | 80000 | 80100 | 80000 | 80000 | 4358990 | 3758848 | 644895 | 1 | 80015 | 0 | 80040 | 80040 | 59924 | 3 | 59998 | 240100 | 200 | 80000 | 80000 | 200 | 240000 | 160000 | 80040 | 80040 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 80008 | 8 | 29 | 0 | 1 | 80008 | 0 | 1 | 8 | 80001 | 1 | 21 | 0 | 0 | 0 | 0 | 0 | 5110 | 1 | 16 | 1 | 1 | 80037 | 80000 | 80000 | 80000 | 80100 | 80041 | 80041 | 80041 | 80041 | 80041 |
160204 | 80040 | 621 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 9 | 0 | 0 | 183 | 1 | 80025 | 8 | 0 | 6 | 25 | 244654 | 80100 | 82049 | 80000 | 80100 | 80000 | 80000 | 4358990 | 3758848 | 642624 | 1 | 80015 | 0 | 80040 | 80040 | 59924 | 3 | 59998 | 240100 | 200 | 80000 | 80000 | 200 | 240000 | 160000 | 80269 | 80040 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 80000 | 0 | 21 | 0 | 0 | 80001 | 2 | 0 | 6 | 80002 | 7 | 0 | 7 | 1 | 0 | 0 | 0 | 5110 | 1 | 16 | 1 | 1 | 80037 | 80000 | 80000 | 80000 | 80100 | 80041 | 80041 | 80041 | 80041 | 80041 |
Result (median cycles for code divided by count): 1.0005
retire uop (01) | cycle (02) | 03 | l1d tlb fill (05) | mmu table walk instruction (07) | mmu table walk data (08) | l2 tlb miss instruction (0a) | l2 tlb miss data (0b) | 0f | 18 | 19 | 1e | 1f | 22 | 23 | 24 | 37 | 3a | 3f | 46 | 49 | 4f | 51 | schedule uop (52) | schedule int uop (53) | schedule simd uop (54) | schedule ldst uop (55) | dispatch int uop (56) | dispatch simd uop (57) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | ldst uops in schedulers (5b) | 60 | 69 | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map simd uop (7e) | map int uop inputs (7f) | map ldst uop inputs (80) | map simd uop inputs (81) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int alu (97) | inst simd store (99) | inst ldst (9b) | 9f | l1d tlb access (a0) | l1d tlb miss (a1) | l1d cache miss st (a2) | a4 | ld unit uop (a6) | st unit uop (a7) | l1d cache writeback (a8) | a9 | ac | af | bc | l1d cache miss st nonspec (c0) | l1d tlb miss nonspec (c1) | c2 | cf | d5 | map dispatch bubble (d6) | db | dd | fetch restart (de) | e0 | ? int output thing (e9) | ? ldst retires (ed) | ? simd retires (ee) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
160026 | 80040 | 620 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 9 | 0 | 0 | 0 | 3756 | 0 | 80025 | 8 | 0 | 1 | 25 | 241731 | 80010 | 80009 | 80000 | 80010 | 80000 | 80000 | 4358429 | 3758848 | 651271 | 0 | 80015 | 80040 | 80040 | 59946 | 3 | 60020 | 240010 | 20 | 80000 | 80000 | 20 | 240000 | 160000 | 80040 | 80040 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 80000 | 0 | 25 | 0 | 1 | 80008 | 0 | 0 | 3 | 80001 | 1 | 25 | 7 | 0 | 5020 | 3 | 16 | 0 | 3 | 2 | 80037 | 80000 | 80000 | 80000 | 80010 | 80041 | 80041 | 80041 | 80041 | 80041 |
160024 | 80040 | 621 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 12 | 9 | 1 | 0 | 0 | 1148 | 0 | 80025 | 0 | 0 | 2 | 25 | 240928 | 80010 | 84744 | 80000 | 80010 | 80000 | 80000 | 4358409 | 3758848 | 644414 | 0 | 80015 | 80040 | 80040 | 59946 | 3 | 60020 | 240010 | 20 | 80000 | 80000 | 20 | 240000 | 160000 | 80040 | 80040 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 80008 | 7 | 25 | 0 | 0 | 80001 | 0 | 0 | 2 | 80001 | 8 | 25 | 0 | 0 | 5020 | 3 | 266 | 0 | 4 | 4 | 80037 | 80000 | 80000 | 80000 | 80010 | 80041 | 80041 | 80041 | 80041 | 80041 |
160024 | 80040 | 620 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 12 | 0 | 0 | 0 | 3755 | 1 | 80025 | 11 | 11 | 1 | 25 | 240932 | 80010 | 84694 | 80000 | 80010 | 80000 | 80000 | 4358409 | 3758848 | 656895 | 0 | 80015 | 80040 | 80040 | 59946 | 3 | 60020 | 240010 | 20 | 80000 | 80000 | 20 | 240000 | 160000 | 80165 | 80148 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 80008 | 0 | 17 | 0 | 0 | 80001 | 1 | 0 | 2 | 80001 | 8 | 0 | 0 | 0 | 5020 | 3 | 16 | 0 | 2 | 3 | 80037 | 80000 | 80000 | 80000 | 80010 | 80041 | 80041 | 80041 | 80041 | 80041 |
160024 | 80040 | 620 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 7 | 1 | 0 | 0 | 1622 | 0 | 80025 | 11 | 11 | 0 | 25 | 244703 | 80010 | 80922 | 80000 | 80010 | 80000 | 80000 | 4358429 | 3758848 | 654080 | 0 | 80015 | 80040 | 80040 | 59946 | 3 | 60103 | 240010 | 20 | 80000 | 80000 | 20 | 240000 | 160000 | 80040 | 80040 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 80000 | 0 | 17 | 0 | 0 | 80001 | 0 | 0 | 2 | 80000 | 0 | 0 | 0 | 0 | 5020 | 3 | 16 | 0 | 3 | 3 | 80037 | 80000 | 80000 | 80000 | 80010 | 80041 | 80041 | 80041 | 80041 | 80041 |
160024 | 80040 | 620 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 126 | 2 | 0 | 0 | 0 | 5636 | 0 | 80025 | 8 | 8 | 0 | 25 | 240589 | 80010 | 80020 | 80000 | 80010 | 80000 | 80000 | 4358429 | 3758848 | 641729 | 0 | 80117 | 80040 | 80040 | 59946 | 3 | 60020 | 240010 | 20 | 80000 | 80000 | 20 | 240000 | 160000 | 83585 | 82849 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 80000 | 0 | 0 | 0 | 0 | 80001 | 2 | 0 | 0 | 80001 | 1 | 17 | 0 | 0 | 5020 | 3 | 16 | 0 | 3 | 3 | 80037 | 80000 | 80000 | 80000 | 80010 | 80041 | 80041 | 80041 | 80041 | 80041 |
160024 | 80040 | 620 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 12 | 0 | 0 | 0 | 1151 | 0 | 80025 | 8 | 8 | 2 | 25 | 241158 | 80010 | 84694 | 80000 | 80010 | 80000 | 80000 | 4358429 | 3758848 | 654092 | 0 | 80015 | 80040 | 80040 | 59946 | 3 | 60020 | 240010 | 20 | 80000 | 80000 | 20 | 240000 | 160000 | 80040 | 80040 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 80000 | 9 | 25 | 0 | 0 | 80001 | 1 | 0 | 2 | 80000 | 1 | 25 | 7 | 0 | 5020 | 5 | 16 | 0 | 3 | 2 | 80037 | 80000 | 80000 | 80000 | 80010 | 80041 | 80041 | 80041 | 80041 | 80041 |
160024 | 80040 | 621 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 9 | 0 | 0 | 0 | 4739 | 0 | 80025 | 8 | 0 | 1 | 25 | 244705 | 80010 | 80014 | 80000 | 80010 | 80000 | 80000 | 4358405 | 3758848 | 645164 | 0 | 80015 | 80040 | 80040 | 59946 | 3 | 60020 | 240010 | 20 | 80000 | 80120 | 20 | 240000 | 160000 | 80040 | 80040 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 80000 | 7 | 0 | 0 | 0 | 80001 | 1 | 0 | 13 | 80002 | 0 | 17 | 0 | 0 | 5020 | 2 | 16 | 0 | 3 | 3 | 80037 | 80000 | 80000 | 80000 | 80010 | 80041 | 80041 | 80041 | 80041 | 80041 |
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