Apple Microarchitecture Research by Dougall Johnson M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions M1/A14 E-core (Icestorm): Overview | Base Instructions | SIMD and FP Instructions
Code:
st2 { v0.4h, v1.4h }, [x6], x8 nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop
mov x0, 0 mov x8, 0
(no loop instructions)
Retires (minus 60 nops): 2.000
Issues: 3.000
Integer unit issues: 1.000
Load/store unit issues: 1.000
SIMD/FP unit issues: 1.000
retire uop (01) | cycle (02) | 03 | l1i tlb fill (04) | l1d tlb fill (05) | mmu table walk instruction (07) | mmu table walk data (08) | 09 | l2 tlb miss instruction (0a) | l2 tlb miss data (0b) | 18 | 19 | 1e | 1f | 22 | 23 | 24 | 3a | 3f | 46 | 49 | 51 | schedule uop (52) | schedule int uop (53) | schedule simd uop (54) | schedule ldst uop (55) | dispatch int uop (56) | dispatch simd uop (57) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | ldst uops in schedulers (5b) | 5f | 69 | 6d | 6e | map rewind (75) | map stall (76) | dispatch uop (78) | map ldst uop (7d) | map simd uop (7e) | map ldst uop inputs (80) | map simd uop inputs (81) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst simd store (99) | inst ldst (9b) | l1d tlb access (a0) | l1d tlb miss (a1) | l1d cache miss st (a2) | ld unit uop (a6) | st unit uop (a7) | l1d cache writeback (a8) | a9 | ac | af | bc | l1d cache miss st nonspec (c0) | l1d tlb miss nonspec (c1) | c2 | c9 | cf | d0 | d2 | l1i cache miss demand (d3) | l1i tlb miss demand (d4) | d5 | map dispatch bubble (d6) | d9 | da | db | dd | fetch restart (de) | e0 | ? int output thing (e9) | ea | eb | ec | ? ldst retires (ed) | ? simd retires (ee) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
62006 | 28993 | 232 | 2 | 1 | 3 | 1 | 0 | 2 | 0 | 0 | 0 | 0 | 3 | 1 | 0 | 0 | 4638 | 28635 | 1 | 0 | 17817 | 3000 | 1000 | 1000 | 1001 | 1000 | 1000 | 1000 | 5000 | 10911 | 8000 | 8 | 21647 | 28578 | 28720 | 3 | 10 | 3000 | 1000 | 1000 | 3003 | 2000 | 28664 | 28663 | 1 | 1 | 61001 | 1000 | 1000 | 1000 | 0 | 3 | 0 | 1001 | 1 | 0 | 1 | 1000 | 2 | 3 | 0 | 0 | 0 | 13314 | 9413 | 6920 | 3102 | 1 | 50 | 20525 | 3291 | 3803 | 20 | 54 | 59 | 28323 | 1000 | 15792 | 12709 | 13684 | 1000 | 1000 | 1000 | 28816 | 28880 | 28862 | 28811 | 28789 |
62004 | 28836 | 231 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 153 | 1 | 0 | 0 | 0 | 4662 | 28539 | 1 | 1 | 17747 | 3000 | 1000 | 1000 | 1000 | 1000 | 1000 | 1000 | 5000 | 10899 | 8000 | 8 | 21741 | 28544 | 28805 | 3 | 10 | 3000 | 1000 | 1000 | 3000 | 2000 | 28785 | 28783 | 1 | 1 | 61001 | 1000 | 1000 | 1000 | 0 | 0 | 2 | 1002 | 0 | 0 | 465 | 1001 | 0 | 3 | 1 | 1 | 0 | 13146 | 9393 | 7002 | 3154 | 0 | 52 | 20158 | 3220 | 3814 | 15 | 57 | 59 | 28247 | 1000 | 15302 | 12964 | 14008 | 1000 | 1000 | 1000 | 29010 | 28840 | 28800 | 28806 | 28851 |
62004 | 28828 | 232 | 0 | 0 | 1 | 0 | 1 | 1 | 2 | 0 | 0 | 132 | 2 | 0 | 0 | 0 | 4734 | 28695 | 1 | 0 | 17833 | 3003 | 1002 | 1000 | 1001 | 1000 | 1000 | 1000 | 5000 | 10907 | 8000 | 6 | 21748 | 28712 | 28684 | 3 | 10 | 3000 | 1000 | 1000 | 3000 | 2000 | 28841 | 28777 | 1 | 1 | 61001 | 1000 | 1000 | 1001 | 2 | 3 | 0 | 1000 | 0 | 1 | 1 | 1000 | 1 | 4 | 0 | 0 | 0 | 13204 | 9255 | 6877 | 3161 | 2 | 57 | 20133 | 3215 | 3813 | 21 | 47 | 50 | 28286 | 1000 | 15653 | 12943 | 13921 | 1000 | 1000 | 1000 | 28864 | 28931 | 28932 | 28823 | 28814 |
62004 | 28842 | 231 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 4676 | 28634 | 0 | 0 | 17778 | 3000 | 1000 | 1000 | 1000 | 1000 | 1000 | 1000 | 5005 | 10899 | 8000 | 7 | 21704 | 28634 | 28881 | 9 | 10 | 3000 | 1000 | 1000 | 3003 | 2000 | 28870 | 28778 | 1 | 1 | 61001 | 1000 | 1000 | 1000 | 0 | 3 | 0 | 1001 | 0 | 0 | 430 | 1001 | 0 | 2 | 1 | 1 | 0 | 13182 | 9292 | 6921 | 3100 | 2 | 55 | 20103 | 3192 | 3818 | 20 | 56 | 57 | 28234 | 1000 | 15679 | 12718 | 13823 | 1000 | 1000 | 1000 | 28905 | 28992 | 28751 | 28855 | 28787 |
62004 | 28854 | 232 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | 4777 | 28629 | 0 | 1 | 17891 | 3000 | 1000 | 1000 | 1000 | 1000 | 1000 | 1000 | 5000 | 10896 | 8000 | 9 | 21667 | 28578 | 28939 | 3 | 10 | 3000 | 1000 | 1000 | 3000 | 2000 | 28807 | 28834 | 1 | 1 | 61001 | 1000 | 1000 | 1000 | 0 | 4 | 1 | 1001 | 1 | 0 | 5 | 1000 | 1 | 3 | 0 | 0 | 0 | 13015 | 9392 | 6939 | 3146 | 0 | 44 | 20322 | 3268 | 3815 | 18 | 50 | 53 | 28333 | 1000 | 16034 | 13141 | 13898 | 1000 | 1000 | 1000 | 28945 | 28872 | 28833 | 28828 | 28919 |
62004 | 28897 | 236 | 0 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 144 | 2 | 1 | 0 | 0 | 4718 | 28812 | 1 | 1 | 17987 | 3000 | 1000 | 1000 | 1000 | 1000 | 1000 | 1000 | 5000 | 10905 | 8000 | 8 | 21708 | 28624 | 28827 | 3 | 10 | 3000 | 1000 | 1000 | 3000 | 2000 | 28823 | 28846 | 1 | 1 | 61001 | 1000 | 1000 | 1000 | 0 | 0 | 2 | 1002 | 2 | 0 | 0 | 1000 | 0 | 3 | 1 | 0 | 147 | 13270 | 9147 | 6949 | 3131 | 1 | 56 | 20535 | 3211 | 3811 | 12 | 48 | 53 | 28507 | 1000 | 15992 | 12876 | 14188 | 1000 | 1000 | 1000 | 29015 | 29208 | 29264 | 29184 | 28861 |
62004 | 29106 | 232 | 1 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 2 | 0 | 0 | 1 | 4756 | 28817 | 1 | 0 | 17761 | 3000 | 1000 | 1000 | 1000 | 1000 | 1000 | 1000 | 5000 | 10908 | 8000 | 6 | 21713 | 28550 | 28872 | 3 | 10 | 3000 | 1000 | 1000 | 3000 | 2000 | 28766 | 28753 | 1 | 1 | 61001 | 1000 | 1000 | 1003 | 3 | 4 | 0 | 1001 | 0 | 0 | 481 | 1000 | 1 | 4 | 0 | 2 | 0 | 13010 | 9382 | 6924 | 3158 | 1 | 48 | 20343 | 3272 | 3810 | 23 | 54 | 59 | 28267 | 1002 | 15808 | 12859 | 13949 | 1000 | 1000 | 1000 | 28981 | 29058 | 28852 | 28858 | 28927 |
62004 | 29010 | 233 | 0 | 0 | 0 | 0 | 2 | 1 | 2 | 2 | 1 | 132 | 179 | 0 | 0 | 1 | 4636 | 28764 | 1 | 0 | 17833 | 3003 | 1001 | 1001 | 1002 | 1000 | 1000 | 1005 | 5025 | 10906 | 8000 | 4 | 21689 | 28849 | 29023 | 3 | 10 | 3000 | 1000 | 1000 | 3000 | 2000 | 29052 | 29093 | 2 | 1 | 61001 | 1000 | 1000 | 1003 | 0 | 0 | 3 | 1004 | 0 | 2 | 0 | 1001 | 0 | 3 | 1 | 3 | 0 | 13078 | 9314 | 6863 | 3129 | 1 | 50 | 20241 | 3166 | 3812 | 25 | 54 | 49 | 28126 | 1001 | 15811 | 13012 | 13818 | 1000 | 1000 | 1000 | 28938 | 30178 | 29125 | 29019 | 29221 |
62004 | 29154 | 235 | 0 | 0 | 1 | 2 | 2 | 0 | 2 | 0 | 1 | 132 | 266 | 0 | 0 | 1 | 4746 | 28943 | 1 | 1 | 18430 | 3000 | 1000 | 1000 | 1000 | 1000 | 1000 | 1000 | 5000 | 10907 | 8000 | 9 | 21747 | 28894 | 29312 | 3 | 10 | 3000 | 1000 | 1000 | 3000 | 2000 | 29049 | 29168 | 1 | 1 | 61001 | 1000 | 1000 | 1000 | 0 | 4 | 1 | 1001 | 0 | 0 | 8 | 1000 | 1 | 0 | 1 | 1 | 416 | 13129 | 9352 | 6978 | 3137 | 0 | 57 | 20426 | 3353 | 3810 | 13 | 51 | 57 | 28218 | 1000 | 15590 | 12959 | 13986 | 1000 | 1000 | 1000 | 29055 | 28774 | 28791 | 28486 | 28670 |
62004 | 28599 | 222 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 4690 | 28500 | 0 | 0 | 17718 | 3000 | 1000 | 1000 | 1000 | 1000 | 1000 | 1000 | 5000 | 10903 | 8000 | 4 | 21685 | 28429 | 28565 | 3 | 10 | 3000 | 1000 | 1000 | 3000 | 2000 | 28719 | 28617 | 1 | 1 | 61001 | 1000 | 1000 | 1000 | 0 | 3 | 1 | 1001 | 0 | 0 | 0 | 1000 | 0 | 3 | 1 | 1 | 0 | 13390 | 9329 | 6974 | 3311 | 1 | 47 | 21351 | 3285 | 3814 | 33 | 51 | 46 | 29070 | 1000 | 17318 | 14446 | 18263 | 1000 | 1000 | 1000 | 28961 | 28914 | 28826 | 28702 | 28772 |
Count: 8
Code:
st2 { v0.4h, v1.4h }, [x6], x8 st2 { v0.4h, v1.4h }, [x6], x8 st2 { v0.4h, v1.4h }, [x6], x8 st2 { v0.4h, v1.4h }, [x6], x8 st2 { v0.4h, v1.4h }, [x6], x8 st2 { v0.4h, v1.4h }, [x6], x8 st2 { v0.4h, v1.4h }, [x6], x8 st2 { v0.4h, v1.4h }, [x6], x8
mov x7, x6 mov x8, x6 mov x9, x6 mov x10, x6 mov x11, x6 mov x12, x6 mov x13, x6 mov x8, 0
(fused SUBS/B.cc loop)
Result (median cycles for code divided by count): 1.0005
retire uop (01) | cycle (02) | 03 | l1d tlb fill (05) | mmu table walk data (08) | l2 tlb miss data (0b) | 18 | 19 | 1e | 1f | 22 | 24 | 37 | 3a | 3f | 46 | 49 | 4f | 51 | schedule uop (52) | schedule int uop (53) | schedule simd uop (54) | schedule ldst uop (55) | dispatch int uop (56) | dispatch simd uop (57) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | ldst uops in schedulers (5b) | 60 | 69 | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map simd uop (7e) | map int uop inputs (7f) | map ldst uop inputs (80) | map simd uop inputs (81) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int alu (97) | inst simd store (99) | inst ldst (9b) | 9f | l1d tlb access (a0) | l1d tlb miss (a1) | l1d cache miss st (a2) | a4 | ld unit uop (a6) | st unit uop (a7) | l1d cache writeback (a8) | a9 | ac | af | bc | l1d cache miss st nonspec (c0) | c2 | cd | cf | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ? int output thing (e9) | ea | ? ldst retires (ed) | ? simd retires (ee) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
160206 | 80040 | 620 | 1 | 0 | 0 | 0 | 0 | 18 | 0 | 1 | 0 | 1480 | 0 | 80025 | 8 | 8 | 3 | 25 | 240222 | 80100 | 86044 | 80000 | 80333 | 80000 | 80000 | 4359014 | 3758848 | 643107 | 0 | 80015 | 80040 | 80040 | 59924 | 3 | 59998 | 240100 | 200 | 80000 | 80000 | 200 | 240000 | 160000 | 80040 | 80040 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 80000 | 0 | 0 | 0 | 0 | 80001 | 1 | 0 | 5 | 80000 | 0 | 0 | 0 | 0 | 5110 | 0 | 16 | 1 | 1 | 80037 | 80000 | 0 | 80000 | 80000 | 80100 | 80041 | 80041 | 80041 | 80041 | 80041 |
160204 | 80040 | 621 | 0 | 0 | 0 | 0 | 0 | 12 | 3 | 0 | 0 | 1080 | 0 | 80025 | 8 | 8 | 1 | 25 | 240996 | 80100 | 82678 | 80000 | 80100 | 80000 | 80000 | 4359014 | 3758848 | 655522 | 0 | 80015 | 80040 | 80040 | 59924 | 3 | 59998 | 240100 | 200 | 80000 | 80000 | 200 | 240000 | 160000 | 80040 | 80040 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 80000 | 0 | 17 | 0 | 0 | 80001 | 3 | 0 | 1 | 80001 | 1 | 17 | 0 | 0 | 5110 | 1 | 16 | 1 | 1 | 80037 | 80000 | 0 | 80000 | 80000 | 80100 | 80041 | 80041 | 80041 | 80041 | 80041 |
160204 | 80040 | 620 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 1159 | 0 | 80025 | 0 | 8 | 0 | 25 | 240222 | 80100 | 81035 | 80000 | 80100 | 80000 | 80000 | 4359014 | 3758848 | 648062 | 1 | 80015 | 80040 | 80040 | 59924 | 3 | 59998 | 240100 | 200 | 80000 | 80000 | 200 | 240000 | 160000 | 80040 | 80040 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 80000 | 0 | 0 | 0 | 0 | 80001 | 0 | 0 | 0 | 80001 | 0 | 17 | 0 | 0 | 5110 | 1 | 16 | 1 | 1 | 80037 | 80000 | 0 | 80000 | 80000 | 80100 | 80041 | 80041 | 80041 | 80041 | 80041 |
160204 | 80040 | 620 | 0 | 0 | 0 | 0 | 0 | 24 | 3 | 1 | 0 | 1480 | 0 | 80025 | 8 | 8 | 1 | 25 | 244403 | 80100 | 81450 | 80000 | 80100 | 80000 | 80000 | 4359014 | 3758848 | 648046 | 0 | 80015 | 80040 | 80040 | 59924 | 3 | 59998 | 240100 | 200 | 80000 | 80000 | 200 | 240000 | 160000 | 80040 | 80040 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 80000 | 0 | 17 | 0 | 0 | 80000 | 0 | 0 | 3 | 80001 | 0 | 0 | 0 | 0 | 5110 | 1 | 16 | 1 | 1 | 80037 | 80000 | 0 | 80000 | 80000 | 80100 | 80041 | 80041 | 80041 | 80041 | 80041 |
160204 | 80040 | 620 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 122 | 0 | 80025 | 8 | 0 | 3 | 25 | 244403 | 80100 | 81160 | 80000 | 80100 | 80000 | 80000 | 4359014 | 3758848 | 645375 | 0 | 80015 | 80040 | 80040 | 59924 | 3 | 59998 | 240100 | 200 | 80000 | 80000 | 200 | 240000 | 160000 | 80040 | 80040 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 80000 | 0 | 17 | 0 | 0 | 80001 | 1 | 0 | 0 | 80001 | 1 | 17 | 0 | 0 | 5110 | 1 | 16 | 1 | 1 | 80037 | 80000 | 0 | 80000 | 80000 | 80100 | 80041 | 80041 | 80041 | 80041 | 80041 |
160204 | 80040 | 620 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 113 | 0 | 80025 | 8 | 8 | 1 | 25 | 241260 | 80100 | 81480 | 80000 | 80100 | 80000 | 80000 | 4359014 | 3758848 | 640207 | 0 | 80015 | 80040 | 80040 | 59924 | 3 | 59998 | 240100 | 200 | 80000 | 80000 | 200 | 240000 | 160000 | 80040 | 80040 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 80000 | 0 | 17 | 0 | 0 | 80001 | 0 | 0 | 2 | 80001 | 1 | 17 | 0 | 0 | 5110 | 1 | 16 | 1 | 1 | 80037 | 80000 | 0 | 80000 | 80000 | 80100 | 80041 | 80041 | 80041 | 80041 | 80041 |
160204 | 80040 | 620 | 0 | 0 | 0 | 0 | 0 | 15 | 3 | 1 | 0 | 896 | 0 | 80025 | 0 | 8 | 0 | 25 | 241260 | 80100 | 80159 | 80000 | 80100 | 80000 | 80000 | 4358990 | 3758848 | 644450 | 1 | 80015 | 80040 | 80040 | 59924 | 3 | 59998 | 240100 | 200 | 80000 | 80000 | 200 | 240000 | 160000 | 80040 | 80040 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 80000 | 0 | 17 | 0 | 0 | 80000 | 0 | 0 | 5 | 80002 | 0 | 0 | 0 | 0 | 5110 | 1 | 16 | 1 | 1 | 80037 | 80000 | 0 | 80000 | 80000 | 80100 | 80041 | 80041 | 80041 | 80041 | 80041 |
160204 | 80040 | 620 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 1160 | 0 | 80025 | 0 | 8 | 2 | 25 | 241260 | 80100 | 81035 | 80000 | 80100 | 80000 | 80000 | 4359014 | 3758848 | 644458 | 0 | 80015 | 80040 | 80040 | 59924 | 3 | 59998 | 240100 | 200 | 80000 | 80000 | 200 | 240000 | 160000 | 80040 | 80040 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 80000 | 0 | 17 | 0 | 0 | 80001 | 0 | 0 | 0 | 80001 | 1 | 17 | 0 | 0 | 5110 | 1 | 16 | 1 | 1 | 80037 | 80000 | 0 | 80000 | 80000 | 80100 | 80041 | 80041 | 80041 | 80041 | 80041 |
160204 | 80040 | 620 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 99 | 0 | 80025 | 8 | 8 | 1 | 25 | 241255 | 80100 | 80179 | 80000 | 80100 | 80000 | 80000 | 4359014 | 3758848 | 642410 | 0 | 80015 | 80040 | 80040 | 59924 | 3 | 59998 | 240100 | 200 | 80000 | 80000 | 200 | 240000 | 160000 | 80040 | 80040 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 80000 | 0 | 17 | 0 | 0 | 80001 | 0 | 0 | 1 | 80001 | 1 | 17 | 0 | 0 | 5110 | 1 | 16 | 1 | 1 | 80037 | 80000 | 0 | 80000 | 80000 | 80100 | 80041 | 80041 | 80041 | 80041 | 80041 |
160204 | 80040 | 621 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 664 | 0 | 80025 | 0 | 0 | 0 | 25 | 245277 | 80100 | 81035 | 80000 | 80100 | 80000 | 80000 | 4359014 | 3758848 | 643100 | 0 | 80015 | 80040 | 80040 | 59924 | 3 | 59998 | 240100 | 200 | 80000 | 80000 | 200 | 240000 | 160000 | 80040 | 80040 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 80000 | 0 | 17 | 0 | 0 | 80000 | 0 | 0 | 0 | 80000 | 1 | 17 | 0 | 0 | 5110 | 1 | 16 | 1 | 1 | 80037 | 80000 | 0 | 80000 | 80000 | 80100 | 80041 | 80041 | 80041 | 80041 | 80041 |
Result (median cycles for code divided by count): 1.0005
retire uop (01) | cycle (02) | 03 | l1d tlb fill (05) | mmu table walk data (08) | 09 | l2 tlb miss data (0b) | 18 | 19 | 1e | 1f | 22 | 23 | 24 | 37 | 3a | 3f | 46 | 49 | 4f | 51 | schedule uop (52) | schedule int uop (53) | schedule simd uop (54) | schedule ldst uop (55) | dispatch int uop (56) | dispatch simd uop (57) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | ldst uops in schedulers (5b) | 69 | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map simd uop (7e) | map int uop inputs (7f) | map ldst uop inputs (80) | map simd uop inputs (81) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int alu (97) | inst simd store (99) | inst ldst (9b) | 9f | l1d tlb access (a0) | l1d tlb miss (a1) | l1d cache miss st (a2) | a4 | ld unit uop (a6) | st unit uop (a7) | l1d cache writeback (a8) | a9 | ac | af | bc | l1d cache miss st nonspec (c0) | l1d tlb miss nonspec (c1) | c2 | cf | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ? int output thing (e9) | ? ldst retires (ed) | ? simd retires (ee) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
160026 | 80040 | 620 | 1 | 0 | 0 | 1 | 0 | 0 | 15 | 7 | 1 | 0 | 0 | 3756 | 1 | 80025 | 11 | 11 | 2 | 25 | 243766 | 80010 | 83756 | 80000 | 80010 | 80000 | 80000 | 4358405 | 3758848 | 645164 | 80015 | 80040 | 80040 | 59946 | 3 | 60020 | 240010 | 20 | 80000 | 80000 | 20 | 240000 | 160000 | 80040 | 80040 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 80008 | 8 | 25 | 0 | 0 | 80008 | 0 | 1 | 14 | 80001 | 8 | 25 | 7 | 1 | 5020 | 38 | 16 | 46 | 20 | 80037 | 80000 | 80000 | 80000 | 80010 | 80041 | 80041 | 80041 | 80041 | 80041 |
160024 | 80040 | 620 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 9 | 0 | 0 | 0 | 4742 | 1 | 80025 | 11 | 11 | 2 | 25 | 245640 | 80010 | 82070 | 80000 | 80010 | 80000 | 80000 | 4358405 | 3758848 | 651367 | 80015 | 80040 | 80040 | 59946 | 3 | 60020 | 240010 | 20 | 80000 | 80000 | 20 | 240000 | 160000 | 80040 | 80040 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 80007 | 8 | 25 | 0 | 1 | 80008 | 1 | 1 | 8 | 80001 | 8 | 25 | 7 | 1 | 5020 | 42 | 16 | 37 | 37 | 80037 | 80000 | 80000 | 80000 | 80010 | 80041 | 80041 | 80041 | 80041 | 80041 |
160024 | 80040 | 621 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 7 | 0 | 0 | 0 | 1147 | 1 | 80025 | 9 | 10 | 1 | 25 | 241484 | 80010 | 84691 | 80000 | 80010 | 80000 | 80000 | 4358409 | 3758848 | 654229 | 80015 | 80040 | 80040 | 59946 | 3 | 60020 | 240010 | 20 | 80000 | 80000 | 20 | 240000 | 160000 | 80040 | 80040 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 80008 | 7 | 25 | 0 | 0 | 80008 | 0 | 0 | 8 | 80001 | 8 | 25 | 7 | 0 | 5020 | 40 | 16 | 39 | 40 | 80037 | 80000 | 80000 | 80000 | 80010 | 80041 | 80041 | 80041 | 80041 | 80041 |
160024 | 80148 | 621 | 1 | 1 | 0 | 1 | 0 | 0 | 507 | 7 | 1 | 0 | 0 | 24 | 1 | 80025 | 11 | 11 | 1 | 38 | 241473 | 80010 | 81721 | 80000 | 80010 | 80000 | 80108 | 4358417 | 3758848 | 651265 | 80015 | 80040 | 80040 | 60009 | 3 | 60020 | 240010 | 20 | 80000 | 80000 | 20 | 240000 | 160000 | 80040 | 80040 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 80007 | 7 | 25 | 0 | 0 | 80008 | 2 | 0 | 11 | 80001 | 8 | 25 | 7 | 0 | 5020 | 41 | 16 | 39 | 40 | 80037 | 80000 | 80000 | 80000 | 80010 | 80041 | 80041 | 80041 | 80041 | 80041 |
160024 | 80040 | 621 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 7 | 0 | 0 | 0 | 1724 | 1 | 80025 | 11 | 11 | 2 | 25 | 245701 | 80010 | 81296 | 80000 | 80010 | 80000 | 80000 | 4358405 | 3758848 | 647677 | 80015 | 80040 | 80179 | 60095 | 3 | 60020 | 240010 | 20 | 80000 | 80000 | 20 | 240000 | 160000 | 80040 | 80040 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 80008 | 7 | 25 | 0 | 0 | 80008 | 1 | 0 | 11 | 80001 | 8 | 25 | 7 | 0 | 5020 | 41 | 16 | 40 | 15 | 80037 | 80000 | 80000 | 80000 | 80010 | 80041 | 80041 | 80041 | 80041 | 80041 |
160024 | 80040 | 620 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 9 | 0 | 0 | 0 | 3754 | 1 | 80025 | 11 | 11 | 2 | 25 | 241790 | 80010 | 81148 | 80000 | 80010 | 80000 | 80000 | 4358409 | 3758848 | 643444 | 80015 | 80040 | 80040 | 59946 | 3 | 60020 | 240010 | 20 | 80000 | 80000 | 20 | 240000 | 160000 | 80040 | 80040 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 80007 | 7 | 25 | 0 | 0 | 80008 | 0 | 1 | 7 | 80000 | 8 | 25 | 7 | 1 | 5020 | 15 | 16 | 37 | 41 | 80037 | 80000 | 80000 | 80000 | 80010 | 80041 | 80041 | 80041 | 80041 | 80041 |
160024 | 80040 | 620 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 9 | 0 | 0 | 0 | 4738 | 1 | 80025 | 9 | 11 | 1 | 25 | 241158 | 80010 | 85635 | 80000 | 80010 | 80000 | 80000 | 4358409 | 3758848 | 651271 | 80015 | 80040 | 80040 | 59946 | 3 | 60020 | 240010 | 20 | 80000 | 80000 | 20 | 240000 | 160000 | 80040 | 80040 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 80009 | 9 | 25 | 0 | 1 | 80008 | 0 | 0 | 8 | 80001 | 8 | 25 | 7 | 1 | 5020 | 38 | 16 | 43 | 17 | 80037 | 80000 | 80000 | 80000 | 80010 | 80041 | 80041 | 80041 | 80041 | 80041 |
160024 | 80040 | 620 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 9 | 0 | 0 | 0 | 2070 | 1 | 80025 | 11 | 11 | 2 | 25 | 241896 | 80010 | 84695 | 80000 | 80010 | 80000 | 80000 | 4358409 | 3758848 | 642760 | 80015 | 80040 | 80040 | 59946 | 3 | 60020 | 240010 | 20 | 80000 | 80000 | 20 | 240000 | 160000 | 80040 | 80040 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 80007 | 8 | 25 | 0 | 0 | 80008 | 1 | 1 | 8 | 80001 | 8 | 25 | 7 | 2 | 5020 | 37 | 16 | 43 | 42 | 80037 | 80000 | 80000 | 80000 | 80010 | 80041 | 80041 | 80041 | 80041 | 80041 |
160024 | 80040 | 620 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 12 | 0 | 0 | 0 | 4742 | 1 | 80025 | 11 | 10 | 1 | 25 | 242079 | 80010 | 81380 | 80000 | 80010 | 80000 | 80000 | 4358417 | 3758848 | 656896 | 80015 | 80040 | 80040 | 59946 | 3 | 60020 | 240010 | 20 | 80000 | 80000 | 20 | 240000 | 160000 | 80040 | 80040 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 80008 | 7 | 25 | 0 | 0 | 80008 | 0 | 0 | 11 | 80061 | 7 | 25 | 7 | 1 | 5020 | 38 | 16 | 39 | 15 | 80037 | 80000 | 80000 | 80000 | 80010 | 80041 | 80041 | 80041 | 80041 | 80041 |
160024 | 80040 | 620 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 185 | 0 | 0 | 0 | 3024 | 1 | 82222 | 11 | 11 | 148 | 81 | 242547 | 80103 | 81503 | 80120 | 80126 | 80116 | 80216 | 4360693 | 3762988 | 644962 | 80117 | 80040 | 80282 | 59946 | 192 | 61356 | 245790 | 20 | 80120 | 80240 | 20 | 240360 | 160480 | 80162 | 80163 | 3 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 80130 | 7 | 25 | 57 | 0 | 80068 | 0 | 3 | 1091 | 80061 | 8 | 25 | 7 | 3 | 5056 | 39 | 34 | 24 | 39 | 80248 | 81554 | 80000 | 80000 | 80010 | 80287 | 80161 | 80162 | 80163 | 80163 |