Apple Microarchitecture Research by Dougall Johnson M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions M1/A14 E-core (Icestorm): Overview | Base Instructions | SIMD and FP Instructions
Code:
st2 { v0.4s, v1.4s }, [x6], x8 nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop
mov x0, 0 mov x8, 0
(no loop instructions)
Retires (minus 60 nops): 4.000
Issues: 5.000
Integer unit issues: 1.000
Load/store unit issues: 2.000
SIMD/FP unit issues: 2.000
retire uop (01) | cycle (02) | 03 | l1i tlb fill (04) | mmu table walk instruction (07) | mmu table walk data (08) | l2 tlb miss instruction (0a) | 18 | 1e | 1f | 22 | 23 | 3a | 3f | 46 | 49 | 51 | schedule uop (52) | schedule int uop (53) | schedule simd uop (54) | schedule ldst uop (55) | dispatch int uop (56) | dispatch simd uop (57) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | ldst uops in schedulers (5b) | 5f | 69 | 6d | 6e | map rewind (75) | map stall (76) | dispatch uop (78) | map ldst uop (7d) | map simd uop (7e) | map ldst uop inputs (80) | map simd uop inputs (81) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst simd store (99) | inst ldst (9b) | l1d tlb access (a0) | l1d cache miss st (a2) | ld unit uop (a6) | st unit uop (a7) | l1d cache writeback (a8) | a9 | ac | af | bc | l1d cache miss st nonspec (c0) | c2 | c9 | cf | d0 | d2 | l1i cache miss demand (d3) | l1i tlb miss demand (d4) | d5 | map dispatch bubble (d6) | d9 | da | db | dd | fetch restart (de) | e0 | ? int output thing (e9) | ea | eb | ec | ? ldst retires (ed) | ? simd retires (ee) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
64007 | 29613 | 238 | 1 | 4 | 0 | 31 | 0 | 0 | 0 | 0 | 0 | 4698 | 29151 | 2 | 2 | 18386 | 5000 | 1000 | 2000 | 2000 | 1000 | 2000 | 2000 | 5000 | 21608 | 16000 | 2 | 21828 | 29261 | 29437 | 3 | 10 | 5000 | 2000 | 2000 | 5000 | 4000 | 29464 | 29484 | 1 | 1 | 61001 | 1000 | 1000 | 2000 | 6 | 0 | 2000 | 0 | 0 | 0 | 2000 | 0 | 6 | 0 | 2373 | 13011 | 9312 | 6909 | 3174 | 2 | 69 | 20440 | 3349 | 3813 | 21 | 69 | 68 | 28838 | 1000 | 16024 | 13213 | 14617 | 2000 | 2000 | 1000 | 29543 | 29613 | 29548 | 29498 | 29484 |
64004 | 29460 | 236 | 2 | 3 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 4639 | 29358 | 0 | 2 | 18412 | 5000 | 1001 | 2000 | 2000 | 1000 | 2000 | 2000 | 5000 | 21620 | 16000 | 2 | 21813 | 29452 | 29690 | 3 | 10 | 5000 | 2000 | 2004 | 5000 | 4000 | 29618 | 29395 | 1 | 1 | 61001 | 1000 | 1000 | 2000 | 0 | 0 | 2000 | 1 | 0 | 30 | 2000 | 0 | 6 | 0 | 0 | 13354 | 9377 | 6998 | 3159 | 2 | 67 | 20563 | 3354 | 3818 | 25 | 68 | 70 | 28713 | 1000 | 16617 | 13312 | 14603 | 2000 | 2000 | 1000 | 29550 | 29593 | 29480 | 29514 | 28918 |
64004 | 34277 | 238 | 2 | 2 | 0 | 5 | 0 | 0 | 3 | 0 | 0 | 4582 | 28554 | 0 | 0 | 17916 | 5000 | 1001 | 2000 | 2002 | 1001 | 2000 | 2000 | 5000 | 21625 | 16000 | 11 | 21808 | 28424 | 28745 | 3 | 10 | 5000 | 2000 | 2000 | 5000 | 4000 | 28929 | 28843 | 1 | 1 | 61001 | 1000 | 1000 | 2000 | 6 | 0 | 2000 | 0 | 0 | 2 | 2002 | 0 | 4 | 0 | 0 | 13206 | 9614 | 7021 | 3169 | 2 | 68 | 19739 | 3202 | 3818 | 21 | 69 | 74 | 28249 | 1000 | 15257 | 12791 | 13857 | 2000 | 2000 | 1000 | 28782 | 28617 | 28657 | 28684 | 28925 |
64004 | 28744 | 223 | 2 | 1 | 0 | 1 | 0 | 9 | 1 | 0 | 0 | 4682 | 28868 | 0 | 0 | 17817 | 5000 | 1000 | 2000 | 2000 | 1000 | 2000 | 2000 | 5000 | 21605 | 16000 | 1 | 21846 | 28742 | 28927 | 3 | 10 | 5000 | 2002 | 2000 | 5000 | 4000 | 28944 | 29058 | 1 | 1 | 61001 | 1000 | 1000 | 2000 | 0 | 0 | 2000 | 0 | 0 | 0 | 2002 | 0 | 4 | 2 | 0 | 13161 | 9175 | 6986 | 3161 | 2 | 72 | 19988 | 3265 | 3816 | 21 | 67 | 71 | 28417 | 1000 | 15774 | 13065 | 14202 | 2000 | 2000 | 1000 | 28908 | 29072 | 28968 | 28941 | 28910 |
64004 | 28985 | 233 | 2 | 1 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 4686 | 28872 | 2 | 0 | 17828 | 5000 | 1000 | 2000 | 2000 | 1000 | 2000 | 2000 | 5000 | 21630 | 16000 | 1 | 21848 | 28908 | 29061 | 3 | 10 | 5000 | 2000 | 2000 | 5000 | 4000 | 28729 | 28694 | 1 | 1 | 61001 | 1000 | 1000 | 2000 | 6 | 0 | 2000 | 0 | 0 | 0 | 2002 | 0 | 6 | 0 | 0 | 13359 | 9289 | 6999 | 3171 | 1 | 67 | 19790 | 3168 | 3812 | 26 | 67 | 71 | 28187 | 1000 | 15319 | 12716 | 13874 | 2000 | 2000 | 1000 | 28641 | 28756 | 28800 | 28890 | 28791 |
64004 | 28715 | 223 | 2 | 3 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 4819 | 28657 | 0 | 0 | 17601 | 5000 | 1000 | 2000 | 2000 | 1000 | 2000 | 2000 | 5000 | 21628 | 16000 | 4 | 21809 | 28582 | 28783 | 8 | 10 | 5000 | 2000 | 2002 | 5000 | 4000 | 28733 | 28721 | 1 | 1 | 61001 | 1000 | 1000 | 2000 | 6 | 0 | 2000 | 0 | 0 | 0 | 2002 | 0 | 4 | 0 | 0 | 13350 | 9462 | 6918 | 3167 | 2 | 74 | 19686 | 3193 | 3809 | 18 | 67 | 70 | 28142 | 1000 | 15417 | 12926 | 13418 | 2000 | 2000 | 1000 | 28748 | 28844 | 28756 | 28631 | 28750 |
64004 | 28821 | 223 | 2 | 3 | 0 | 2 | 0 | 0 | 1 | 0 | 0 | 4713 | 28469 | 0 | 2 | 17517 | 5000 | 1000 | 2000 | 2000 | 1000 | 2000 | 2000 | 5000 | 21619 | 16000 | 14 | 21777 | 28467 | 28754 | 3 | 10 | 5005 | 2000 | 2000 | 5000 | 4000 | 28579 | 28841 | 1 | 1 | 61001 | 1000 | 1000 | 2000 | 0 | 2 | 2002 | 0 | 0 | 0 | 2002 | 2 | 6 | 0 | 0 | 13363 | 9250 | 6963 | 3085 | 3 | 63 | 19708 | 3235 | 3807 | 20 | 63 | 68 | 28272 | 1000 | 15290 | 12603 | 13800 | 2000 | 2000 | 1000 | 28845 | 28620 | 28741 | 28805 | 28793 |
64004 | 28765 | 223 | 2 | 3 | 0 | 3 | 0 | 0 | 91 | 0 | 0 | 4664 | 28608 | 2 | 2 | 17625 | 5000 | 1000 | 2000 | 2000 | 1001 | 2000 | 2000 | 5000 | 21619 | 16000 | 16 | 21822 | 28460 | 28850 | 3 | 10 | 5000 | 2000 | 2000 | 5000 | 4000 | 28663 | 28672 | 2 | 1 | 61001 | 1000 | 1000 | 2000 | 6 | 0 | 2000 | 0 | 2 | 0 | 2002 | 4 | 6 | 0 | 0 | 13034 | 9544 | 6872 | 3108 | 1 | 66 | 19748 | 3144 | 3804 | 27 | 70 | 70 | 28189 | 1000 | 15379 | 12680 | 13842 | 2000 | 2000 | 1000 | 28755 | 28649 | 28774 | 28668 | 28729 |
64004 | 28636 | 223 | 1 | 2 | 0 | 2 | 0 | 0 | 3 | 0 | 0 | 4833 | 28563 | 2 | 2 | 17638 | 5000 | 1000 | 2000 | 2000 | 1000 | 2000 | 2000 | 5000 | 21635 | 16000 | 19 | 21771 | 28340 | 28780 | 3 | 10 | 5000 | 2000 | 2000 | 5000 | 4000 | 28634 | 28598 | 1 | 1 | 61001 | 1000 | 1000 | 2000 | 0 | 0 | 2002 | 1 | 0 | 0 | 2002 | 2 | 0 | 0 | 0 | 13245 | 9273 | 6954 | 3181 | 2 | 65 | 19763 | 3190 | 3801 | 18 | 69 | 70 | 28289 | 1000 | 15629 | 12681 | 14027 | 2000 | 2000 | 1000 | 28713 | 28755 | 28677 | 28671 | 28734 |
64004 | 28693 | 223 | 2 | 1 | 0 | 2 | 0 | 0 | 3 | 0 | 0 | 4612 | 28586 | 0 | 2 | 17662 | 5000 | 1000 | 2000 | 2000 | 1000 | 2000 | 2000 | 5000 | 21609 | 16000 | 20 | 21855 | 28512 | 28766 | 3 | 10 | 5000 | 2000 | 2000 | 5005 | 4000 | 28704 | 28703 | 1 | 1 | 61001 | 1000 | 1000 | 2000 | 6 | 0 | 2002 | 0 | 0 | 5 | 2000 | 0 | 4 | 0 | 0 | 13230 | 9345 | 6993 | 3174 | 3 | 67 | 19694 | 3135 | 3804 | 21 | 56 | 60 | 28210 | 1000 | 15445 | 12722 | 13635 | 2000 | 2000 | 1000 | 28841 | 28750 | 28743 | 28695 | 28703 |
Count: 8
Code:
st2 { v0.4s, v1.4s }, [x6], x8 st2 { v0.4s, v1.4s }, [x6], x8 st2 { v0.4s, v1.4s }, [x6], x8 st2 { v0.4s, v1.4s }, [x6], x8 st2 { v0.4s, v1.4s }, [x6], x8 st2 { v0.4s, v1.4s }, [x6], x8 st2 { v0.4s, v1.4s }, [x6], x8 st2 { v0.4s, v1.4s }, [x6], x8
mov x7, x6 mov x8, x6 mov x9, x6 mov x10, x6 mov x11, x6 mov x12, x6 mov x13, x6 mov x8, 0
(fused SUBS/B.cc loop)
Result (median cycles for code divided by count): 1.0006
retire uop (01) | cycle (02) | 03 | mmu table walk data (08) | 09 | l2 tlb miss data (0b) | 18 | 19 | 1e | 1f | 24 | 37 | 3f | 46 | 49 | 4f | 51 | schedule uop (52) | schedule int uop (53) | schedule simd uop (54) | schedule ldst uop (55) | dispatch int uop (56) | dispatch simd uop (57) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | ldst uops in schedulers (5b) | 60 | 69 | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map simd uop (7e) | map int uop inputs (7f) | map ldst uop inputs (80) | map simd uop inputs (81) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int alu (97) | inst simd store (99) | inst ldst (9b) | 9f | l1d tlb access (a0) | l1d tlb miss (a1) | l1d cache miss st (a2) | a4 | ld unit uop (a6) | st unit uop (a7) | l1d cache writeback (a8) | a9 | ac | af | bc | l1d cache miss st nonspec (c0) | branch mispred nonspec (cb) | cf | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ? int output thing (e9) | ? ldst retires (ed) | ? simd retires (ee) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
320207 | 80071 | 620 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 6202 | 80030 | 16 | 16 | 103 | 25 | 404222 | 80100 | 165153 | 160000 | 80100 | 160000 | 160000 | 480499 | 2079350 | 1297162 | 0 | 80023 | 80044 | 80044 | 0 | 3 | 30 | 400100 | 200 | 160000 | 160480 | 200 | 400000 | 320000 | 80045 | 80044 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 160000 | 0 | 0 | 0 | 0 | 160002 | 0 | 0 | 2 | 160002 | 2 | 40 | 0 | 5163 | 4 | 62 | 1 | 2 | 80042 | 80000 | 160000 | 160000 | 80100 | 80770 | 80774 | 80647 | 80594 | 80780 |
320204 | 80772 | 626 | 0 | 0 | 1 | 4 | 4 | 558 | 395 | 0 | 4137 | 80030 | 16 | 16 | 0 | 25 | 405476 | 80100 | 164018 | 160000 | 80100 | 160000 | 160000 | 480499 | 2158256 | 1295625 | 0 | 80023 | 80045 | 80045 | 0 | 3 | 27 | 400100 | 200 | 160000 | 160000 | 200 | 400000 | 320000 | 80045 | 80046 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 160000 | 0 | 40 | 0 | 0 | 160000 | 0 | 0 | 11 | 160002 | 0 | 40 | 0 | 5109 | 1 | 17 | 1 | 1 | 80042 | 80000 | 160000 | 160000 | 80100 | 80046 | 80046 | 80045 | 80045 | 80046 |
320204 | 80045 | 620 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0 | 4841 | 80030 | 0 | 16 | 0 | 25 | 404946 | 80100 | 163986 | 160000 | 80100 | 160000 | 160000 | 480499 | 2079721 | 1301628 | 1 | 80023 | 80044 | 80045 | 0 | 3 | 27 | 400100 | 200 | 160000 | 160000 | 200 | 400000 | 320000 | 80045 | 80044 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 160000 | 0 | 40 | 0 | 0 | 160002 | 0 | 0 | 2 | 160002 | 2 | 40 | 0 | 5109 | 1 | 17 | 1 | 1 | 80042 | 80000 | 160000 | 160000 | 80100 | 80046 | 80046 | 80046 | 80045 | 80046 |
320204 | 80045 | 620 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0 | 2051 | 80030 | 16 | 16 | 0 | 25 | 405824 | 80100 | 163834 | 160000 | 80100 | 160000 | 160000 | 480499 | 2079051 | 1301424 | 0 | 80023 | 80044 | 80045 | 0 | 3 | 27 | 400100 | 200 | 160000 | 160000 | 200 | 400000 | 320000 | 80045 | 80044 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 160000 | 0 | 40 | 0 | 0 | 160002 | 0 | 0 | 2 | 160002 | 2 | 40 | 0 | 5109 | 1 | 17 | 1 | 1 | 80042 | 80000 | 160000 | 160000 | 80100 | 80046 | 80046 | 80046 | 80044 | 80046 |
320204 | 80044 | 620 | 0 | 0 | 0 | 0 | 0 | 12 | 3 | 0 | 3323 | 80030 | 16 | 16 | 0 | 25 | 405962 | 80100 | 163901 | 160000 | 80100 | 160000 | 160000 | 480499 | 2235902 | 1300773 | 0 | 80023 | 80045 | 80045 | 0 | 3 | 27 | 400100 | 200 | 160000 | 160000 | 200 | 400000 | 320000 | 80046 | 80045 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 160000 | 0 | 42 | 0 | 0 | 160002 | 1 | 0 | 2 | 160002 | 2 | 40 | 0 | 5109 | 1 | 17 | 1 | 1 | 80042 | 80000 | 160000 | 160000 | 80100 | 80046 | 80046 | 80046 | 80045 | 80046 |
320204 | 80044 | 621 | 0 | 0 | 0 | 0 | 0 | 12 | 3 | 0 | 3670 | 80030 | 16 | 16 | 0 | 25 | 406017 | 80100 | 165121 | 160000 | 80100 | 160000 | 160000 | 480499 | 2237757 | 1295614 | 0 | 80023 | 80045 | 80044 | 0 | 3 | 26 | 400100 | 200 | 160000 | 160480 | 200 | 400000 | 320000 | 80045 | 80045 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 160000 | 0 | 0 | 0 | 0 | 160000 | 2 | 0 | 2 | 160002 | 2 | 0 | 0 | 5109 | 1 | 17 | 1 | 1 | 80042 | 80000 | 160000 | 160000 | 80100 | 80046 | 80046 | 80045 | 80046 | 80046 |
320204 | 80046 | 621 | 0 | 0 | 0 | 0 | 2 | 0 | 3 | 0 | 2873 | 80030 | 16 | 16 | 0 | 25 | 407211 | 80100 | 164444 | 160000 | 80100 | 160000 | 160000 | 480499 | 2238846 | 1294673 | 0 | 80023 | 80046 | 80044 | 0 | 3 | 27 | 400100 | 200 | 160000 | 160000 | 200 | 400000 | 320000 | 80043 | 80045 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 160000 | 0 | 40 | 0 | 0 | 160002 | 0 | 0 | 2 | 160002 | 2 | 40 | 0 | 5109 | 1 | 17 | 1 | 1 | 80042 | 80000 | 160000 | 160000 | 80100 | 80046 | 80045 | 80045 | 80045 | 80046 |
320204 | 80044 | 620 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | 3848 | 80030 | 16 | 16 | 0 | 25 | 404144 | 80100 | 164018 | 160000 | 80100 | 160000 | 160000 | 480499 | 2238893 | 1305482 | 0 | 80024 | 80045 | 80044 | 0 | 3 | 27 | 400100 | 200 | 160000 | 160000 | 200 | 400000 | 320000 | 80045 | 80046 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 160000 | 0 | 40 | 0 | 0 | 160002 | 1 | 0 | 2 | 160002 | 2 | 0 | 0 | 5109 | 1 | 17 | 1 | 1 | 80042 | 80000 | 160000 | 160000 | 80100 | 80046 | 80046 | 80046 | 80045 | 80045 |
320204 | 80044 | 620 | 0 | 0 | 0 | 0 | 0 | 12 | 3 | 0 | 5428 | 80030 | 16 | 16 | 0 | 25 | 404118 | 80100 | 163335 | 160000 | 80100 | 160000 | 160000 | 480499 | 2158256 | 1297925 | 0 | 80023 | 80044 | 80046 | 0 | 3 | 27 | 400100 | 200 | 160000 | 160000 | 200 | 400000 | 320000 | 80044 | 80045 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 160000 | 0 | 40 | 0 | 0 | 160002 | 0 | 0 | 20 | 160002 | 2 | 0 | 0 | 5109 | 1 | 17 | 1 | 1 | 80043 | 80000 | 160000 | 160000 | 80100 | 80046 | 80046 | 80045 | 80046 | 80046 |
320204 | 80044 | 621 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5149 | 80039 | 0 | 16 | 0 | 25 | 403770 | 80100 | 164898 | 160000 | 80100 | 160000 | 160000 | 480499 | 2156998 | 1295327 | 0 | 80022 | 80054 | 80045 | 0 | 3 | 26 | 400100 | 200 | 160000 | 160000 | 200 | 400000 | 320000 | 80045 | 80045 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 160000 | 0 | 40 | 0 | 0 | 160002 | 0 | 0 | 2 | 160002 | 2 | 40 | 0 | 5109 | 1 | 17 | 1 | 1 | 80042 | 80000 | 160000 | 160000 | 80100 | 80045 | 80045 | 80045 | 80045 | 80046 |
Result (median cycles for code divided by count): 1.0006
retire uop (01) | cycle (02) | 03 | l1d tlb fill (05) | mmu table walk data (08) | 09 | l2 tlb miss data (0b) | 0f | 1e | 1f | 22 | 23 | 37 | 3a | 3f | 46 | 49 | 4f | 51 | schedule uop (52) | schedule int uop (53) | schedule simd uop (54) | schedule ldst uop (55) | dispatch int uop (56) | dispatch simd uop (57) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | ldst uops in schedulers (5b) | 60 | 69 | 6b | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map simd uop (7e) | map int uop inputs (7f) | map ldst uop inputs (80) | map simd uop inputs (81) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int alu (97) | inst simd store (99) | inst ldst (9b) | 9f | l1d tlb access (a0) | l1d tlb miss (a1) | l1d cache miss st (a2) | a4 | ld unit uop (a6) | st unit uop (a7) | l1d cache writeback (a8) | a9 | ac | af | bc | l1d cache miss st nonspec (c0) | l1d tlb miss nonspec (c1) | c2 | cf | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ? int output thing (e9) | ? ldst retires (ed) | ? simd retires (ee) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
320027 | 80058 | 620 | 0 | 0 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 30 | 1 | 80034 | 24 | 0 | 0 | 35 | 403451 | 80010 | 165906 | 160000 | 80010 | 160000 | 160000 | 480049 | 2319388 | 1302773 | 0 | 80036 | 0 | 80050 | 80049 | 0 | 3 | 39 | 400010 | 20 | 160000 | 160000 | 20 | 400000 | 320000 | 80056 | 80056 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 160012 | 12 | 38 | 0 | 0 | 160014 | 0 | 0 | 12 | 160000 | 14 | 60 | 12 | 0 | 5021 | 5 | 17 | 5 | 5 | 80054 | 80000 | 160000 | 160000 | 80010 | 80050 | 80046 | 80051 | 80046 | 80045 |
320024 | 80045 | 599 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 3255 | 1 | 80035 | 16 | 16 | 0 | 25 | 404027 | 80010 | 165076 | 160000 | 80010 | 160000 | 160000 | 480049 | 2079520 | 1288109 | 0 | 80025 | 0 | 80045 | 80048 | 0 | 3 | 26 | 400010 | 20 | 160000 | 160000 | 20 | 400000 | 320000 | 80050 | 80050 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 160000 | 0 | 32 | 0 | 0 | 160000 | 0 | 0 | 11 | 160002 | 2 | 54 | 0 | 0 | 5021 | 5 | 18 | 5 | 5 | 80045 | 80000 | 160000 | 160000 | 80010 | 80049 | 80049 | 80045 | 80046 | 80049 |
320024 | 80050 | 600 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 6996 | 1 | 80030 | 16 | 16 | 0 | 25 | 403568 | 80010 | 163353 | 160000 | 80010 | 160000 | 160000 | 480049 | 2077275 | 1294211 | 0 | 80024 | 0 | 80045 | 80044 | 0 | 3 | 26 | 400010 | 20 | 160000 | 160000 | 20 | 400000 | 320240 | 80045 | 80045 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 160000 | 0 | 32 | 2 | 0 | 160000 | 0 | 0 | 2 | 160000 | 4 | 54 | 0 | 0 | 5021 | 4 | 17 | 5 | 3 | 80041 | 80000 | 160000 | 160000 | 80010 | 80048 | 80046 | 80050 | 80045 | 80046 |
320024 | 80045 | 599 | 0 | 0 | 0 | 0 | 0 | 0 | 9 | 0 | 0 | 5321 | 1 | 80035 | 24 | 0 | 0 | 25 | 406276 | 80010 | 161026 | 160000 | 80010 | 160000 | 160000 | 480049 | 2078874 | 1301787 | 0 | 80027 | 0 | 80048 | 80044 | 0 | 3 | 30 | 400010 | 20 | 160000 | 160000 | 20 | 400000 | 320000 | 80044 | 80044 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 160000 | 0 | 32 | 0 | 0 | 160002 | 2 | 0 | 8 | 160002 | 2 | 54 | 0 | 0 | 5021 | 6 | 17 | 5 | 3 | 80041 | 80000 | 160000 | 160000 | 80010 | 80046 | 80045 | 80046 | 80045 | 80050 |
320024 | 80050 | 599 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3782 | 1 | 80030 | 24 | 0 | 0 | 25 | 402223 | 80010 | 162663 | 160000 | 80010 | 160000 | 160000 | 480049 | 2399440 | 1303109 | 0 | 80028 | 0 | 80048 | 80048 | 0 | 3 | 30 | 400010 | 20 | 160000 | 160000 | 20 | 400000 | 320000 | 80049 | 80049 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 160000 | 0 | 32 | 2 | 0 | 160002 | 0 | 0 | 2 | 160002 | 2 | 32 | 0 | 0 | 5021 | 5 | 17 | 4 | 5 | 80041 | 80000 | 160000 | 160000 | 80010 | 80050 | 80045 | 80045 | 80050 | 80051 |
320024 | 80045 | 599 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 3520 | 1 | 80029 | 24 | 16 | 0 | 25 | 404197 | 80010 | 166470 | 160000 | 80010 | 160000 | 160000 | 480049 | 2398951 | 1303481 | 0 | 80024 | 0 | 80049 | 80044 | 0 | 3 | 30 | 400010 | 20 | 160000 | 160000 | 20 | 400000 | 320000 | 80048 | 80045 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 160000 | 0 | 32 | 0 | 0 | 160000 | 0 | 0 | 2 | 160002 | 2 | 32 | 0 | 0 | 5021 | 5 | 17 | 5 | 4 | 80046 | 80000 | 160000 | 160000 | 80010 | 80045 | 80049 | 80050 | 80050 | 80046 |
320024 | 80049 | 600 | 0 | 0 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 60 | 1 | 80033 | 16 | 16 | 0 | 25 | 404829 | 80010 | 166044 | 160000 | 80010 | 160000 | 160000 | 480049 | 1919780 | 1301521 | 0 | 80024 | 0 | 80045 | 80048 | 0 | 3 | 26 | 400010 | 20 | 160000 | 160000 | 20 | 400000 | 320000 | 80049 | 80049 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 160000 | 0 | 32 | 0 | 0 | 160002 | 0 | 0 | 0 | 160002 | 2 | 32 | 0 | 0 | 5021 | 5 | 17 | 5 | 5 | 80042 | 80000 | 160000 | 160000 | 80010 | 80047 | 80045 | 80050 | 80045 | 80045 |
320024 | 80049 | 599 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 6421 | 1 | 80032 | 0 | 16 | 0 | 25 | 404830 | 80010 | 164332 | 160000 | 80010 | 160000 | 160000 | 480049 | 2239375 | 1280066 | 0 | 80482 | 0 | 80048 | 80045 | 0 | 3 | 27 | 400010 | 20 | 160000 | 160000 | 20 | 400340 | 320000 | 80049 | 80049 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 160000 | 0 | 56 | 2 | 0 | 160002 | 0 | 0 | 2 | 160002 | 2 | 54 | 0 | 0 | 5021 | 4 | 17 | 5 | 3 | 80042 | 80000 | 160000 | 160000 | 80010 | 80045 | 80047 | 80046 | 80050 | 80051 |
320024 | 80045 | 600 | 0 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | 33 | 1 | 80034 | 24 | 0 | 0 | 25 | 404404 | 80010 | 167727 | 160000 | 80010 | 160000 | 160000 | 480049 | 2388632 | 1299401 | 0 | 80024 | 0 | 80050 | 80049 | 0 | 3 | 32 | 400010 | 20 | 160000 | 160000 | 20 | 400000 | 320000 | 80045 | 80048 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 160000 | 0 | 32 | 0 | 0 | 160002 | 0 | 0 | 2 | 160002 | 2 | 54 | 0 | 0 | 5021 | 5 | 17 | 5 | 3 | 80046 | 80000 | 160000 | 160000 | 80010 | 80046 | 80050 | 80046 | 80050 | 80051 |
320024 | 80044 | 600 | 0 | 0 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 7321 | 1 | 80030 | 16 | 16 | 0 | 25 | 405585 | 80010 | 164556 | 160000 | 80010 | 160000 | 160000 | 480049 | 2284596 | 1290405 | 0 | 80025 | 0 | 80045 | 80049 | 0 | 3 | 30 | 400010 | 20 | 160000 | 160000 | 20 | 400000 | 320000 | 80044 | 80044 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 160000 | 0 | 54 | 2 | 0 | 160000 | 0 | 0 | 2 | 160002 | 2 | 54 | 0 | 0 | 5021 | 5 | 17 | 5 | 5 | 80041 | 80000 | 160000 | 160000 | 80010 | 80045 | 80048 | 80045 | 80047 | 80049 |