Apple Microarchitecture Research by Dougall Johnson M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions M1/A14 E-core (Icestorm): Overview | Base Instructions | SIMD and FP Instructions
Code:
st2 { v0.8b, v1.8b }, [x6], x8 nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop
mov x0, 0 mov x8, 0
(no loop instructions)
Retires (minus 60 nops): 2.000
Issues: 3.000
Integer unit issues: 1.000
Load/store unit issues: 1.000
SIMD/FP unit issues: 1.000
retire uop (01) | cycle (02) | 03 | mmu table walk instruction (07) | l2 tlb miss instruction (0a) | l2 tlb miss data (0b) | 18 | 19 | 1e | 1f | 22 | 23 | 24 | 3a | 3f | 46 | 49 | 51 | schedule uop (52) | schedule int uop (53) | schedule simd uop (54) | schedule ldst uop (55) | dispatch int uop (56) | dispatch simd uop (57) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | ldst uops in schedulers (5b) | 5f | 69 | 6d | 6e | map rewind (75) | map stall (76) | dispatch uop (78) | map ldst uop (7d) | map simd uop (7e) | map ldst uop inputs (80) | map simd uop inputs (81) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst simd store (99) | inst ldst (9b) | l1d tlb access (a0) | l1d cache miss st (a2) | st unit uop (a7) | l1d cache writeback (a8) | ac | af | bc | l1d cache miss st nonspec (c0) | c9 | cf | d0 | d2 | l1i cache miss demand (d3) | l1i tlb miss demand (d4) | d5 | map dispatch bubble (d6) | d9 | da | db | dd | fetch restart (de) | df | e0 | ? int output thing (e9) | ea | eb | ec | ? ldst retires (ed) | ? simd retires (ee) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
62006 | 28644 | 223 | 17 | 17 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 4849 | 28519 | 0 | 1 | 17680 | 3000 | 1000 | 1000 | 1000 | 1000 | 1000 | 1000 | 5000 | 10899 | 8000 | 16 | 21633 | 28381 | 28685 | 3 | 10 | 3000 | 1000 | 1000 | 3000 | 2000 | 28544 | 28568 | 1 | 1 | 61001 | 1000 | 1000 | 1000 | 0 | 1000 | 0 | 0 | 1000 | 0 | 3 | 0 | 13277 | 9629 | 7003 | 3120 | 8 | 48 | 19961 | 3173 | 3807 | 19 | 40 | 50 | 2 | 28100 | 1000 | 15558 | 12646 | 13683 | 1000 | 1000 | 1000 | 28647 | 28793 | 28643 | 28673 | 28648 |
62004 | 28605 | 223 | 15 | 16 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 4584 | 28390 | 1 | 1 | 17745 | 3000 | 1000 | 1000 | 1000 | 1000 | 1000 | 1000 | 5000 | 10907 | 8000 | 12 | 21649 | 28409 | 28693 | 3 | 10 | 3000 | 1000 | 1000 | 3000 | 2000 | 28619 | 28576 | 1 | 1 | 61001 | 1000 | 1000 | 1000 | 0 | 1000 | 0 | 0 | 1000 | 0 | 3 | 0 | 13034 | 9358 | 6943 | 3193 | 10 | 42 | 20029 | 3230 | 3811 | 21 | 41 | 39 | 2 | 28180 | 1000 | 15750 | 12545 | 13605 | 1000 | 1000 | 1000 | 28753 | 28693 | 28598 | 28547 | 28588 |
62004 | 28701 | 222 | 17 | 13 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 4846 | 28569 | 1 | 1 | 17647 | 3000 | 1000 | 1000 | 1000 | 1000 | 1000 | 1000 | 5000 | 10908 | 8000 | 17 | 21720 | 28412 | 28590 | 3 | 10 | 3000 | 1000 | 1000 | 3000 | 2000 | 28556 | 28633 | 1 | 1 | 61001 | 1000 | 1000 | 1000 | 0 | 1000 | 0 | 0 | 1000 | 0 | 3 | 0 | 13156 | 9504 | 6925 | 3157 | 5 | 42 | 20069 | 3216 | 3807 | 21 | 35 | 38 | 2 | 28184 | 1000 | 15659 | 12785 | 13678 | 1000 | 1000 | 1000 | 28750 | 28633 | 28699 | 28644 | 28643 |
62004 | 28757 | 223 | 16 | 22 | 0 | 0 | 0 | 9 | 0 | 0 | 0 | 0 | 4710 | 28569 | 1 | 1 | 17612 | 3000 | 1000 | 1000 | 1000 | 1000 | 1000 | 1000 | 5000 | 10903 | 8000 | 7 | 21673 | 28466 | 28674 | 3 | 10 | 3000 | 1000 | 1000 | 3000 | 2000 | 28656 | 28653 | 1 | 1 | 61001 | 1000 | 1000 | 1000 | 3 | 1000 | 0 | 0 | 1000 | 0 | 3 | 0 | 13193 | 9483 | 6921 | 3237 | 8 | 41 | 20104 | 3132 | 3815 | 23 | 41 | 42 | 2 | 28136 | 1000 | 15639 | 12604 | 13653 | 1000 | 1000 | 1000 | 28620 | 28673 | 28622 | 28758 | 28658 |
62004 | 28679 | 223 | 14 | 22 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 4616 | 28601 | 1 | 1 | 17530 | 3000 | 1000 | 1000 | 1000 | 1000 | 1000 | 1000 | 5000 | 10910 | 8000 | 18 | 21712 | 28468 | 28495 | 3 | 10 | 3000 | 1000 | 1000 | 3000 | 2000 | 28633 | 28715 | 1 | 1 | 61001 | 1000 | 1000 | 1000 | 3 | 1000 | 0 | 0 | 1000 | 0 | 3 | 0 | 13258 | 9502 | 6975 | 3169 | 9 | 43 | 19952 | 3162 | 3807 | 15 | 36 | 38 | 2 | 28153 | 1000 | 15315 | 12752 | 13595 | 1000 | 1000 | 1000 | 28633 | 28571 | 28560 | 28529 | 28793 |
62004 | 28630 | 222 | 17 | 15 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 4733 | 28515 | 1 | 1 | 17665 | 3000 | 1000 | 1000 | 1000 | 1000 | 1000 | 1000 | 5000 | 10904 | 8000 | 18 | 21648 | 28420 | 28632 | 3 | 10 | 3000 | 1000 | 1000 | 3000 | 2000 | 28176 | 28518 | 1 | 1 | 61001 | 1000 | 1000 | 1000 | 3 | 1000 | 0 | 0 | 1000 | 0 | 0 | 0 | 13308 | 9512 | 6974 | 3138 | 10 | 52 | 20100 | 3202 | 3814 | 16 | 40 | 40 | 2 | 28160 | 1000 | 15401 | 12604 | 13404 | 1000 | 1000 | 1000 | 28625 | 28706 | 28704 | 28549 | 28552 |
62004 | 28633 | 222 | 19 | 16 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 4767 | 28571 | 1 | 0 | 17674 | 3000 | 1000 | 1000 | 1000 | 1000 | 1000 | 1000 | 5000 | 10901 | 8000 | 16 | 21660 | 28421 | 28656 | 3 | 10 | 3000 | 1000 | 1000 | 3000 | 2000 | 28636 | 28602 | 1 | 1 | 61001 | 1000 | 1000 | 1000 | 0 | 1000 | 0 | 0 | 1000 | 0 | 3 | 0 | 13112 | 9434 | 6882 | 3219 | 9 | 44 | 20044 | 3202 | 3809 | 19 | 44 | 42 | 2 | 28271 | 1000 | 15538 | 12704 | 13716 | 1000 | 1000 | 1000 | 28687 | 28619 | 28636 | 28564 | 28601 |
62004 | 28746 | 223 | 17 | 18 | 0 | 0 | 4 | 0 | 1 | 1 | 0 | 0 | 4939 | 28571 | 0 | 1 | 17727 | 3000 | 1000 | 1000 | 1000 | 1000 | 1000 | 1000 | 5000 | 10904 | 8000 | 17 | 21676 | 28518 | 28745 | 3 | 10 | 3000 | 1000 | 1000 | 3000 | 2000 | 28560 | 28617 | 1 | 1 | 61001 | 1000 | 1000 | 1000 | 0 | 1000 | 0 | 0 | 1000 | 0 | 3 | 0 | 13050 | 9402 | 6877 | 3131 | 9 | 46 | 20055 | 3192 | 3801 | 18 | 43 | 48 | 2 | 28199 | 1000 | 15416 | 12458 | 13430 | 1000 | 1000 | 1000 | 28631 | 28721 | 28697 | 28711 | 28727 |
62004 | 28609 | 222 | 20 | 16 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 4778 | 28542 | 1 | 1 | 17721 | 3000 | 1000 | 1000 | 1000 | 1000 | 1000 | 1000 | 5000 | 10898 | 8000 | 18 | 21706 | 28388 | 28729 | 3 | 10 | 3000 | 1000 | 1000 | 3000 | 2000 | 28574 | 28594 | 1 | 1 | 61001 | 1000 | 1000 | 1000 | 0 | 1000 | 0 | 0 | 1000 | 0 | 3 | 0 | 13099 | 9441 | 6907 | 3168 | 7 | 45 | 19908 | 3228 | 3804 | 16 | 42 | 41 | 2 | 28154 | 1000 | 15419 | 12803 | 13784 | 1000 | 1000 | 1000 | 28641 | 28600 | 28600 | 28686 | 28598 |
62004 | 28586 | 222 | 11 | 14 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 4713 | 28469 | 0 | 1 | 17647 | 3000 | 1000 | 1000 | 1000 | 1000 | 1000 | 1000 | 5000 | 10910 | 8000 | 9 | 21709 | 28412 | 28667 | 3 | 10 | 3000 | 1000 | 1000 | 3000 | 2000 | 28679 | 28472 | 1 | 1 | 61001 | 1000 | 1000 | 1000 | 3 | 1000 | 0 | 0 | 1000 | 0 | 3 | 114 | 13129 | 9459 | 6890 | 3223 | 5 | 45 | 19988 | 3054 | 3812 | 13 | 48 | 43 | 2 | 28188 | 1000 | 15430 | 12703 | 13449 | 1000 | 1000 | 1000 | 28650 | 28675 | 28530 | 28690 | 28642 |
Count: 8
Code:
st2 { v0.8b, v1.8b }, [x6], x8 st2 { v0.8b, v1.8b }, [x6], x8 st2 { v0.8b, v1.8b }, [x6], x8 st2 { v0.8b, v1.8b }, [x6], x8 st2 { v0.8b, v1.8b }, [x6], x8 st2 { v0.8b, v1.8b }, [x6], x8 st2 { v0.8b, v1.8b }, [x6], x8 st2 { v0.8b, v1.8b }, [x6], x8
mov x7, x6 mov x8, x6 mov x9, x6 mov x10, x6 mov x11, x6 mov x12, x6 mov x13, x6 mov x8, 0
(fused SUBS/B.cc loop)
Result (median cycles for code divided by count): 1.0005
retire uop (01) | cycle (02) | 03 | 09 | l2 tlb miss data (0b) | 18 | 19 | 1e | 1f | 22 | 23 | 24 | 37 | 3f | 46 | 49 | 4f | 51 | schedule uop (52) | schedule int uop (53) | schedule simd uop (54) | schedule ldst uop (55) | dispatch int uop (56) | dispatch simd uop (57) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | ldst uops in schedulers (5b) | 60 | 69 | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map simd uop (7e) | map int uop inputs (7f) | map ldst uop inputs (80) | map simd uop inputs (81) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int alu (97) | inst simd store (99) | inst ldst (9b) | 9f | l1d tlb access (a0) | l1d tlb miss (a1) | l1d cache miss st (a2) | a4 | ld unit uop (a6) | st unit uop (a7) | l1d cache writeback (a8) | a9 | ac | af | bc | l1d cache miss st nonspec (c0) | c2 | cf | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ? int output thing (e9) | ? ldst retires (ed) | ? simd retires (ee) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
160206 | 80535 | 647 | 1 | 0 | 4 | 5 | 528 | 440 | 0 | 0 | 0 | 1596 | 80391 | 8 | 8 | 290 | 109 | 246008 | 80560 | 82403 | 80240 | 80565 | 80464 | 80324 | 4363723 | 3771412 | 647517 | 0 | 80427 | 80523 | 80537 | 60109 | 34 | 60332 | 241460 | 200 | 80478 | 80727 | 202 | 241797 | 160960 | 80407 | 80530 | 5 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 80240 | 0 | 17 | 85 | 2 | 80241 | 1 | 0 | 4297 | 80301 | 1 | 19 | 4 | 5179 | 1 | 43 | 1 | 1 | 80458 | 80000 | 80000 | 80000 | 80100 | 80041 | 80164 | 80041 | 80041 | 80041 |
160204 | 80040 | 643 | 0 | 0 | 0 | 0 | 132 | 3 | 1 | 0 | 0 | 1765 | 80025 | 0 | 8 | 0 | 25 | 240824 | 80100 | 81184 | 80000 | 80216 | 80000 | 80000 | 4359014 | 3758848 | 642209 | 0 | 80015 | 80040 | 80040 | 59924 | 3 | 59998 | 240100 | 200 | 80000 | 80000 | 200 | 240000 | 160000 | 80040 | 80040 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 80000 | 0 | 17 | 0 | 0 | 80001 | 0 | 0 | 2 | 80001 | 1 | 17 | 0 | 5110 | 1 | 16 | 1 | 1 | 80037 | 80093 | 80000 | 80000 | 80100 | 80041 | 80041 | 80041 | 80041 | 80041 |
160204 | 80040 | 643 | 0 | 0 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | 229 | 80025 | 8 | 8 | 3 | 25 | 244337 | 80100 | 84222 | 80000 | 80216 | 80000 | 80000 | 4359014 | 3758848 | 642624 | 0 | 80015 | 80161 | 80163 | 59924 | 13 | 59998 | 240100 | 200 | 80120 | 80000 | 200 | 240000 | 160000 | 80040 | 80040 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 80000 | 0 | 17 | 0 | 0 | 80001 | 0 | 0 | 0 | 80001 | 0 | 0 | 0 | 5110 | 1 | 16 | 1 | 1 | 80037 | 80000 | 80000 | 80000 | 80100 | 80164 | 80041 | 80041 | 80041 | 80164 |
160204 | 80040 | 643 | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | 1759 | 80025 | 8 | 8 | 3 | 25 | 240232 | 80100 | 86043 | 80000 | 80217 | 80000 | 80000 | 4359014 | 3758848 | 642410 | 0 | 80015 | 80040 | 80040 | 59924 | 3 | 59998 | 240100 | 200 | 80000 | 80000 | 200 | 240000 | 160000 | 80040 | 80040 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 80000 | 0 | 17 | 0 | 0 | 80061 | 0 | 0 | 0 | 80001 | 0 | 17 | 0 | 5110 | 1 | 16 | 1 | 1 | 80140 | 80000 | 80000 | 80000 | 80100 | 80041 | 80041 | 80041 | 80041 | 80041 |
160204 | 80165 | 642 | 0 | 0 | 0 | 0 | 12 | 3 | 0 | 0 | 0 | 135 | 80025 | 8 | 8 | 1 | 25 | 241638 | 80100 | 81482 | 80000 | 80100 | 80000 | 80000 | 4359014 | 3758848 | 640397 | 0 | 80015 | 80040 | 80040 | 59924 | 3 | 59998 | 240100 | 200 | 80000 | 80120 | 200 | 240000 | 160000 | 80146 | 80040 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 80060 | 0 | 17 | 0 | 0 | 80001 | 0 | 0 | 3 | 80001 | 1 | 17 | 0 | 5110 | 1 | 16 | 1 | 1 | 80037 | 80000 | 80000 | 80000 | 80100 | 80041 | 80041 | 80041 | 80041 | 80041 |
160204 | 80040 | 643 | 0 | 0 | 0 | 0 | 0 | 91 | 0 | 0 | 0 | 181 | 80025 | 8 | 8 | 3 | 25 | 242329 | 80192 | 83434 | 80000 | 80100 | 80000 | 80000 | 4359014 | 3758848 | 642885 | 0 | 80015 | 80040 | 80040 | 59924 | 15 | 59998 | 240100 | 200 | 80000 | 80120 | 200 | 240000 | 160000 | 80040 | 80040 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 80000 | 0 | 17 | 0 | 0 | 80001 | 0 | 0 | 0 | 80001 | 1 | 17 | 0 | 5110 | 1 | 16 | 1 | 1 | 80037 | 80090 | 80000 | 80000 | 80100 | 80041 | 80041 | 80161 | 80041 | 80041 |
160204 | 80040 | 643 | 0 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | 851 | 80025 | 0 | 0 | 3 | 25 | 245277 | 80100 | 80289 | 80000 | 80100 | 80000 | 80000 | 4359014 | 3758848 | 656528 | 0 | 80120 | 80040 | 80040 | 59988 | 3 | 59998 | 240100 | 200 | 80000 | 80120 | 200 | 240000 | 160000 | 80040 | 80040 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 80000 | 2 | 17 | 0 | 0 | 80001 | 1 | 2 | 3 | 80001 | 0 | 0 | 0 | 5110 | 1 | 16 | 1 | 1 | 80037 | 80000 | 80000 | 80000 | 80100 | 80041 | 80041 | 80041 | 80163 | 80041 |
160204 | 80040 | 643 | 0 | 1 | 0 | 0 | 12 | 0 | 0 | 0 | 0 | 99 | 80025 | 8 | 8 | 1 | 25 | 242779 | 80100 | 80137 | 80000 | 80100 | 80116 | 80000 | 4359014 | 3758848 | 655226 | 0 | 80015 | 80161 | 80040 | 59924 | 3 | 59998 | 240100 | 200 | 80000 | 80000 | 200 | 240000 | 160000 | 80040 | 80162 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 80062 | 0 | 17 | 0 | 0 | 80001 | 0 | 0 | 2 | 80061 | 1 | 17 | 0 | 5110 | 1 | 16 | 1 | 1 | 80037 | 80000 | 80000 | 80000 | 80100 | 80041 | 80041 | 80164 | 80041 | 80041 |
160204 | 80040 | 643 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4295 | 80025 | 8 | 8 | 71 | 25 | 245265 | 80100 | 81763 | 80000 | 80100 | 80000 | 80000 | 4359014 | 3758848 | 640258 | 0 | 80015 | 80040 | 80040 | 59924 | 3 | 59998 | 240100 | 200 | 80000 | 80000 | 200 | 240000 | 160240 | 80040 | 80040 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 80000 | 0 | 17 | 0 | 0 | 80001 | 0 | 0 | 2 | 80001 | 0 | 17 | 0 | 5110 | 1 | 16 | 1 | 1 | 80037 | 80093 | 80000 | 80000 | 80100 | 80041 | 80041 | 80041 | 80163 | 80041 |
160204 | 80040 | 643 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1160 | 80025 | 0 | 8 | 2 | 54 | 241645 | 80100 | 83403 | 80000 | 80100 | 80000 | 80000 | 4361527 | 3758848 | 652738 | 0 | 80015 | 80040 | 80040 | 59924 | 3 | 60083 | 240100 | 200 | 80120 | 80000 | 200 | 240000 | 160000 | 80040 | 80040 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 80000 | 0 | 17 | 0 | 0 | 80001 | 1 | 0 | 6 | 80001 | 1 | 17 | 0 | 5127 | 1 | 25 | 1 | 0 | 80037 | 80000 | 80000 | 80000 | 80100 | 80041 | 80041 | 80041 | 80041 | 80041 |
Result (median cycles for code divided by count): 1.0005
retire uop (01) | cycle (02) | 03 | l1d tlb fill (05) | mmu table walk data (08) | l2 tlb miss instruction (0a) | l2 tlb miss data (0b) | 18 | 19 | 1e | 1f | 22 | 23 | 37 | 3a | 3f | 46 | 49 | 4f | 51 | schedule uop (52) | schedule int uop (53) | schedule simd uop (54) | schedule ldst uop (55) | dispatch int uop (56) | dispatch simd uop (57) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | ldst uops in schedulers (5b) | 60 | 69 | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map simd uop (7e) | map int uop inputs (7f) | map ldst uop inputs (80) | map simd uop inputs (81) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int alu (97) | inst simd store (99) | inst ldst (9b) | 9f | l1d tlb access (a0) | l1d tlb miss (a1) | l1d cache miss st (a2) | a4 | ld unit uop (a6) | st unit uop (a7) | l1d cache writeback (a8) | a9 | ac | af | bc | l1d cache miss st nonspec (c0) | l1d tlb miss nonspec (c1) | c2 | cf | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ? int output thing (e9) | ? ldst retires (ed) | ? simd retires (ee) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
160026 | 80040 | 620 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 9 | 0 | 0 | 3756 | 1 | 80025 | 11 | 0 | 2 | 25 | 240927 | 80010 | 80005 | 80000 | 80010 | 80000 | 80000 | 4358417 | 3758848 | 647709 | 0 | 80015 | 80040 | 80040 | 60007 | 3 | 60020 | 240010 | 20 | 80000 | 80000 | 20 | 240000 | 160000 | 80040 | 80040 | 1 | 1 | 80022 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 80007 | 8 | 25 | 0 | 0 | 80008 | 0 | 0 | 14 | 80001 | 8 | 25 | 7 | 1 | 5020 | 10 | 16 | 12 | 6 | 80037 | 80000 | 80000 | 80000 | 80010 | 80041 | 80041 | 80041 | 80041 | 80041 |
160024 | 80040 | 621 | 1 | 2 | 0 | 0 | 0 | 0 | 12 | 9 | 0 | 0 | 1154 | 1 | 80025 | 11 | 0 | 6 | 25 | 243802 | 80010 | 84856 | 80000 | 80010 | 80000 | 80000 | 4358405 | 3758848 | 651268 | 0 | 80015 | 80162 | 80040 | 59946 | 3 | 60020 | 240010 | 20 | 80000 | 80000 | 20 | 240000 | 160000 | 80040 | 80040 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 80007 | 7 | 25 | 0 | 1 | 80008 | 0 | 1 | 14 | 80001 | 8 | 25 | 7 | 1 | 5020 | 11 | 16 | 9 | 9 | 80037 | 80000 | 80000 | 80000 | 80010 | 80041 | 80041 | 80041 | 80041 | 80041 |
160024 | 80040 | 620 | 1 | 0 | 0 | 0 | 0 | 0 | 138 | 14 | 0 | 0 | 840 | 1 | 80025 | 11 | 0 | 76 | 25 | 242579 | 80010 | 80006 | 80000 | 80010 | 80000 | 80000 | 4358417 | 3758848 | 643441 | 0 | 80015 | 80040 | 80040 | 59946 | 3 | 60020 | 240010 | 20 | 80000 | 80000 | 20 | 240000 | 160240 | 80040 | 80040 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 80007 | 7 | 25 | 0 | 0 | 80008 | 1 | 1 | 7 | 80001 | 8 | 26 | 7 | 0 | 5020 | 10 | 16 | 13 | 8 | 80037 | 80000 | 80000 | 80000 | 80010 | 80041 | 80041 | 80041 | 80041 | 80041 |
160024 | 80040 | 620 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 9 | 0 | 0 | 5635 | 1 | 80025 | 11 | 11 | 2 | 25 | 241158 | 80010 | 84137 | 80000 | 80010 | 80000 | 80000 | 4358413 | 3758848 | 643444 | 0 | 80015 | 80040 | 80040 | 59946 | 3 | 60020 | 240010 | 20 | 80000 | 80000 | 20 | 240000 | 160000 | 80040 | 80040 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 80008 | 7 | 25 | 0 | 0 | 80008 | 1 | 1 | 8 | 80001 | 8 | 25 | 7 | 0 | 5020 | 10 | 16 | 10 | 9 | 80037 | 80000 | 80000 | 80000 | 80010 | 80041 | 80041 | 80041 | 80041 | 80041 |
160024 | 80040 | 620 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 12 | 0 | 0 | 920 | 1 | 80753 | 0 | 11 | 2 | 25 | 240032 | 80010 | 81378 | 80000 | 80010 | 80000 | 80000 | 4358417 | 3758848 | 646211 | 0 | 80015 | 80040 | 80040 | 59946 | 3 | 60020 | 240350 | 20 | 80000 | 80000 | 20 | 240000 | 160000 | 80040 | 80040 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 80007 | 7 | 0 | 0 | 1 | 80008 | 0 | 0 | 14 | 80061 | 8 | 25 | 7 | 1 | 5020 | 10 | 16 | 9 | 9 | 80037 | 80000 | 80000 | 80000 | 80010 | 80041 | 80041 | 80041 | 80163 | 80041 |
160024 | 80040 | 620 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 9 | 0 | 0 | 1724 | 1 | 80025 | 11 | 11 | 2 | 25 | 242147 | 80010 | 80009 | 80000 | 80010 | 80000 | 80000 | 4358405 | 3758848 | 642769 | 0 | 80015 | 80040 | 80040 | 59946 | 3 | 60020 | 240010 | 20 | 80000 | 80000 | 20 | 240000 | 160000 | 80040 | 80040 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 80008 | 7 | 0 | 0 | 0 | 80008 | 0 | 1 | 14 | 80001 | 8 | 0 | 7 | 0 | 5020 | 10 | 16 | 9 | 10 | 80037 | 80000 | 80000 | 80000 | 80010 | 80041 | 80041 | 80041 | 80041 | 80041 |
160024 | 80040 | 620 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 100 | 0 | 0 | 5692 | 1 | 80025 | 10 | 11 | 78 | 25 | 245641 | 80010 | 81721 | 80000 | 80010 | 80000 | 80000 | 4358405 | 3758848 | 647674 | 0 | 80118 | 80040 | 80040 | 59946 | 3 | 60020 | 240010 | 20 | 80000 | 80000 | 20 | 240000 | 160000 | 80162 | 80040 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 80007 | 9 | 25 | 0 | 1 | 80008 | 0 | 0 | 11 | 80001 | 7 | 25 | 7 | 1 | 5020 | 10 | 16 | 9 | 10 | 80037 | 80000 | 80000 | 80000 | 80010 | 80041 | 80041 | 80041 | 80041 | 80041 |
160024 | 80040 | 620 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 9 | 0 | 0 | 922 | 1 | 80025 | 11 | 11 | 2 | 25 | 240032 | 80010 | 83755 | 80000 | 80010 | 80000 | 80000 | 4358409 | 3758848 | 644404 | 0 | 80015 | 80040 | 80040 | 59946 | 13 | 60020 | 240010 | 20 | 80000 | 80000 | 20 | 240000 | 160000 | 80040 | 80040 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 80007 | 7 | 25 | 28 | 1 | 80008 | 0 | 0 | 11 | 80001 | 8 | 25 | 7 | 0 | 5020 | 9 | 16 | 10 | 9 | 80037 | 80000 | 80000 | 80000 | 80010 | 80041 | 80041 | 80164 | 80041 | 80041 |
160024 | 80040 | 620 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 9 | 0 | 0 | 1147 | 1 | 80025 | 11 | 11 | 2 | 25 | 243766 | 80010 | 81148 | 80000 | 80010 | 80000 | 80000 | 4358405 | 3758848 | 644167 | 0 | 80015 | 80040 | 80040 | 59946 | 3 | 60104 | 240010 | 20 | 80000 | 80000 | 20 | 240000 | 160000 | 80040 | 80040 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 80007 | 7 | 29 | 0 | 0 | 80008 | 0 | 1 | 11 | 80001 | 8 | 25 | 7 | 0 | 5020 | 10 | 16 | 10 | 9 | 80037 | 80000 | 80000 | 80000 | 80010 | 80041 | 80041 | 80041 | 80041 | 80041 |
160024 | 80040 | 621 | 1 | 0 | 0 | 1 | 1 | 0 | 0 | 7 | 0 | 0 | 1769 | 1 | 80025 | 11 | 11 | 2 | 25 | 241475 | 80010 | 81392 | 80000 | 80010 | 80000 | 80000 | 4358405 | 3758848 | 642748 | 0 | 80118 | 80040 | 80040 | 59946 | 3 | 60020 | 240010 | 20 | 80000 | 80000 | 20 | 240000 | 160240 | 80040 | 80040 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 80008 | 8 | 25 | 0 | 0 | 80008 | 0 | 0 | 11 | 80001 | 8 | 25 | 7 | 0 | 5020 | 10 | 16 | 12 | 8 | 80037 | 80000 | 80000 | 80000 | 80010 | 80041 | 80041 | 80041 | 80041 | 83464 |