Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

ST2 (multiple, post-index, 8H)

Test 1: uops

Code:

  st2 { v0.8h, v1.8h }, [x6], x8
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop
  mov x0, 0
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 4.000

Issues: 5.000

Integer unit issues: 1.000

Load/store unit issues: 2.000

SIMD/FP unit issues: 2.000

retire uop (01)cycle (02)03l1d tlb fill (05)mmu table walk instruction (07)mmu table walk data (08)09l2 tlb miss instruction (0a)l2 tlb miss data (0b)0e18191e1f22243a3f40464951schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)5e5f6061696d6emap rewind (75)map stall (76)dispatch uop (78)map ldst uop (7d)map simd uop (7e)map ldst uop inputs (80)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd store (99)inst ldst (9b)l1d tlb access (a0)l1d tlb miss (a1)l1d cache miss st (a2)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acafbcl1d cache miss st nonspec (c0)c2c9cfd0d2l1i cache miss demand (d3)l1i tlb miss demand (d4)d5map dispatch bubble (d6)d9dadbddfetch restart (de)e0? int output thing (e9)eaebec? ldst retires (ed)? simd retires (ee)? int retires (ef)f5f6f7f8fd
64007287842220170021000024300481828557020176435000100020002000100020002000500021620160000410217942837928622310500020002000500040002873728629116100110001000200000020001002000060013031947068903156106119711313738162162632827210001530312547138212000200010002869428762286052863528790
6400428546222021001600000010476028676000177135000100020002000100020002000500021625160000800218832855328787310500020002000500540002863428644116100110001000200006020020002002060013402947169523252106019615317938122560612809610001505512485137732000200010002872128682287612871828692
64004286002220120021000001005044286270221764550001000200020001000200020005000216261600001100218142851728750310500020002000500040002871228643116100110001000200006020000002002060013303938569013114145819521323238041449562813510001520212388136072000200010002866328749287482858628807
64004287202220180017000000004806285910021758850001000200020001000200020005000216811600001400218122846928622310500020002000500040002858428591116100110001000200006020020002002260013209969669103198125719573315238101559562822810001537712554136792000200010002872128740286842847228472
6400428557222018001600000300479228604020175535000100020002000100020002000500021626160000200217352844228536310500020002002500540002867428602116100110001000200000020020022000260013555946670323137116119687316638061863602815910001550412450137382000200010002868228699286562864128600
6400428635223017001300000110483128445020176135000100020002000100020002000500021612160000120021757283442873131050002000200050004000286442858711610011000100020000002000002200206001312094066980321896619605316638081562642825510001524312683136882000200010002869028833287322878329033
6400428909233020002000000010468728670022177985000100020002000100020002000500021619160000300217512857628714310500020002000500040002879928819116100110001000200000020000002000060013359940068903143116019836320238072155542824410001560512752137802000200010002909229754294752978629646
640042890523211711211000783300462028669022177495000100020002000100020002000500021612160000131021751286082886831050002000200050004000287982888311610011000100020000602002042200206001314991806898312395919878324537992565602838310001564312608138692000200010002885028772288272896928840
640042880523102000190000624300452728731020177975000100020002000100020002000500021627160000110021833285742879731050002000200050004000288532875511610011000100020000002000000200206001323493926922319486019853320838052154592825410001556312852139962000200010002879728813288982881928872
6400428713232018001800005703004624287360221779850001000200020001000200020005000216171600001400217992864928796310500020002000500040002880428760116100110001000200000020020032000260013303939968733140105619882314838112858582834810001575512621140902000200010002888528837288242882328867

Test 2: throughput

Count: 8

Code:

  st2 { v0.8h, v1.8h }, [x6], x8
  st2 { v0.8h, v1.8h }, [x6], x8
  st2 { v0.8h, v1.8h }, [x6], x8
  st2 { v0.8h, v1.8h }, [x6], x8
  st2 { v0.8h, v1.8h }, [x6], x8
  st2 { v0.8h, v1.8h }, [x6], x8
  st2 { v0.8h, v1.8h }, [x6], x8
  st2 { v0.8h, v1.8h }, [x6], x8
  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0007

retire uop (01)cycle (02)03l1d tlb fill (05)mmu table walk instruction (07)mmu table walk data (08)l2 tlb miss data (0b)18191e1f2224373a3f46494f51schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd store (99)inst ldst (9b)9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache miss st (a2)a4ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acafbcl1d cache miss st nonspec (c0)l1d tlb miss nonspec (c1)c2cdcfd0d5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)ea? ldst retires (ed)? simd retires (ee)? int retires (ef)f5f6f7f8fd
320207800536211010000120054982800381616025405198801001624261600008010016000016000048049925598451290596800278005280053033440010020016000016000020040000032000080052800491180201100991001008000080000100160012134600160014501516000214461210510903173380050800000160000160000801008005480050800518005180053
32020480051620101000012104964280038016025405640801001644431600008010016000016000048049923999351300978800288005280052033540010020016000016000020040000032000080053800521180201100991001008000080000100160013120001600143301416000214461200510903173380049800000160000160000801008005180052800538005380224
32020480052621100100012104821280036160025404604801001655261600008010016000016000048049925598221307039800278005280052032940010020016000016000020040000032000080050800531180201100991001008000080000100160012124601160014201516000214451200510903173380050800000160000160000801008005380053800548005380055
32020480052620101000015005757280037161602540558380100166155160000801001600001600004804992719805129945080026800498005103294001002001600001600002004000003200008004980051118020210099100100800008000010016001313001160014410151600021401200510903173280048800000160000160000801008005180048800548005280056
320204800536201010000171046752800361600254046788010016462416000080100160000160000480499271977812997408002780052800520334400100200160000160000200400000320000800518005111802011009910010080000800001001600121344001600143701416000214501200510903173280049800000160000160000801008005480050800498005180057
3202048004962010000001510507728003616160254060568010016482616000080100160000160000480499247975912993108002780052800520333400100200160000160000200400000320000800538005211802011009910010080000800001001600131346001600124301316000214461210510903172380049800000160000160000801008005280054800538004880057
320204800516201010009120056672800381600254027678010016451116000080100160000160000480499232002712972928002480051800520333400100200160000160000200400000320000800518005011802011009910010080000800001001600121346001600142201416000412461210510903173380049800000160000160000801008005180055800538005380722
3202048005262110000001600147428003616160254048778010016587216000080100160000160000480499255984713025128002780050800520334400100200160000160000200400000320000800478004811802011009910010080000800001001600121246011600122201516000214461210510903173380049800000160000160000801008005180053800538005380051
32020480052620101100121500828003716160254055798010016587716000080100160000160000480499255973612952948002780050800500335400100200160000160000200400000320000800538005311802011009910010080000800001001600121246011600142601716000212461200510903173380050800000160000160000801008005380053800528005380054
3202048005362110100001210654628003816160254056858010016478916000080100160000160000480499271976212951298002880053800520333400100200160000160000200400000320000800528004811802011009910010080000800001001600131346001600145101216000012461220510902173380049800000160000160000801008005280053800548005180056

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0006

retire uop (01)cycle (02)03l1i tlb fill (04)l1d tlb fill (05)mmu table walk data (08)l2 tlb miss data (0b)0f18191e1f2224373a3f46494f51schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd store (99)inst ldst (9b)9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache miss st (a2)a4ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acafbcl1d cache miss st nonspec (c0)l1d tlb miss nonspec (c1)c2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)f5f6f7f8fd
3200278005862101013000170044802800371600254038308001016227516000080010160000160000480049271911212959880800268005380052033440001020160000160000204000003200008005180049118002110910108000080000101600751200016001210141600021401205019317238005080059160000160000800108005280048800518005180052
3200248022162001100001212002995280037161602540587480010166582160000800101600001600004800492319939129386708002880050800530334400010201600001600002040000032000080141800511180021109101080000800001016001213001160014019391600001421205019317338004980000160000160000800108004980051800518005280054
32002480047620010000012121057802800361616025404720800101671091600608001016000016000048004920984021303644080387800508021703314000102016000016000020400000320000800498004911800211091010800008000010160012134600160014101416000214461215019317338004580000160000160000800108005180051800548005280053
32002480049620010000093120043742800331616025404454800101681131600008001016000016000048004927197111303613080027800508005203334000102016000016000020400000320000800478004811800211091010800008000010160012134601160074101216000214461215019217328004880000160000160000800108005480050800528005480051
32002480053621010000001600584528003816161022540496880010165457160060800101600001600004800492161779130001508002680052800500332400010201600001601202040000032000080219800511180021109101080000800001016001213460016001400151600621401205019317338004680000160000160000800108005380223800538005280054
320024800486200101000121210478828003816160254038248001016537816000080010160000160000480049216279113030380800268005380052033340001020160000160000204003003200008005280052118002110910108000080000101600131246631160014001516000212461205019317328004880000160000160000800108005480054800538005480050
32002480049620110100012120070572800371616025404347800101642401600008001016000016000048004927197581300748080028800528005303314000102016000016000020400000320000800498005211800211091010800008000010160012130631160012001516000212461205019317338004880000160000160000800108005480054800518005480050
32002480051620010000001500422228003216160254058858006916533016000080010160000160000480049223979313045730800238005180053883324000102016000016000020400000320000800528005021800211091010800008000010160013134600160014001416000214441205019317328004980000160000160000800108004880050802228005480053
320024800536200101000121500461728003701602540588580010165878160000800101600001600004800492319939130158408002780049800500332400010201600001600002040000032000080050800531180021109101080000800001016001215001160014001516000212461205019217238004680059160000160000800108005180051800508005380052
3200248021662101100001212004791280038160025404422800101667361600008001016000016000048004927996971300674080028800528005303136400010201600001600002040000032000080051800531180021109101080000800001016001212000160012031416000012461205033417338004880000160000160000800108005180051800538005480053