Apple Microarchitecture Research by Dougall Johnson M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions M1/A14 E-core (Icestorm): Overview | Base Instructions | SIMD and FP Instructions
Code:
st2 { v0.b, v1.b }[1], [x6] nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop
mov x0, 0
(no loop instructions)
Retires (minus 60 nops): 2.000
Issues: 2.000
Integer unit issues: 0.000
Load/store unit issues: 1.000
SIMD/FP unit issues: 1.000
retire uop (01) | cycle (02) | 03 | l1d tlb fill (05) | mmu table walk instruction (07) | mmu table walk data (08) | 09 | l2 tlb miss instruction (0a) | l2 tlb miss data (0b) | 18 | 19 | 1e | 1f | 23 | 3a | 3f | 51 | schedule uop (52) | schedule simd uop (54) | schedule ldst uop (55) | dispatch simd uop (57) | dispatch ldst uop (58) | simd uops in schedulers (5a) | ldst uops in schedulers (5b) | 5e | 5f | 69 | 6b | 6d | 6e | map rewind (75) | map stall (76) | dispatch uop (78) | map ldst uop (7d) | map simd uop (7e) | map ldst uop inputs (80) | map simd uop inputs (81) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst simd store (99) | inst ldst (9b) | l1d tlb access (a0) | l1d tlb miss (a1) | l1d cache miss st (a2) | ld unit uop (a6) | st unit uop (a7) | l1d cache writeback (a8) | a9 | ac | af | bc | l1d cache miss st nonspec (c0) | l1d tlb miss nonspec (c1) | c2 | cf | d0 | d2 | l1i cache miss demand (d3) | l1i tlb miss demand (d4) | d5 | map dispatch bubble (d6) | d9 | da | db | dd | fetch restart (de) | e0 | ea | eb | ec | ? ldst retires (ed) | ? simd retires (ee) | f5 | f6 | f7 | f8 | fd |
62006 | 28702 | 224 | 1 | 28 | 0 | 0 | 28 | 1 | 0 | 0 | 12 | 1 | 0 | 4862 | 28611 | 17630 | 2000 | 1000 | 1000 | 1000 | 1000 | 10907 | 8000 | 0 | 3 | 21721 | 0 | 28195 | 28759 | 3 | 10 | 2000 | 1000 | 1000 | 2000 | 2000 | 28599 | 28550 | 1 | 1 | 61001 | 1000 | 1000 | 1002 | 1 | 2 | 1 | 1001 | 0 | 0 | 1 | 1000 | 0 | 2 | 1 | 1 | 13205 | 9557 | 6973 | 3289 | 11 | 43 | 20011 | 3158 | 3814 | 15 | 53 | 48 | 28160 | 15125 | 12664 | 13674 | 1000 | 1000 | 28650 | 28589 | 28610 | 28752 | 28668 |
62004 | 28555 | 222 | 1 | 19 | 0 | 1 | 26 | 0 | 0 | 0 | 0 | 1 | 0 | 4671 | 28578 | 17688 | 2000 | 1000 | 1000 | 1000 | 1000 | 10905 | 8000 | 0 | 9 | 21776 | 0 | 28482 | 28775 | 3 | 10 | 2000 | 1000 | 1000 | 2000 | 2000 | 28552 | 28525 | 1 | 1 | 61001 | 1000 | 1000 | 1000 | 0 | 3 | 0 | 1001 | 0 | 0 | 1 | 1000 | 1 | 3 | 0 | 0 | 13288 | 9514 | 6955 | 3171 | 10 | 55 | 20068 | 3169 | 3807 | 16 | 53 | 54 | 28202 | 15490 | 12794 | 14215 | 1000 | 1000 | 28806 | 28682 | 28774 | 28742 | 28774 |
62005 | 28532 | 224 | 1 | 25 | 0 | 0 | 21 | 1 | 0 | 0 | 0 | 2 | 0 | 4825 | 28598 | 17494 | 2000 | 1000 | 1000 | 1000 | 1000 | 10905 | 8000 | 0 | 17 | 21702 | 0 | 28020 | 28628 | 3 | 10 | 2000 | 1000 | 1000 | 2000 | 2000 | 28697 | 28510 | 1 | 1 | 61001 | 1000 | 1000 | 1002 | 2 | 2 | 2 | 1001 | 0 | 0 | 1 | 1000 | 0 | 2 | 1 | 1 | 13321 | 9573 | 6975 | 3238 | 7 | 48 | 20005 | 3143 | 3804 | 16 | 52 | 54 | 28184 | 15233 | 12700 | 14217 | 1000 | 1000 | 28623 | 28682 | 28646 | 28630 | 28857 |
62004 | 28683 | 220 | 0 | 23 | 1 | 0 | 20 | 0 | 0 | 0 | 0 | 2 | 0 | 4763 | 28582 | 17477 | 2000 | 1000 | 1000 | 1000 | 1000 | 10909 | 8000 | 0 | 17 | 21718 | 0 | 28344 | 28687 | 3 | 10 | 2000 | 1000 | 1000 | 2000 | 2000 | 28555 | 28736 | 2 | 1 | 61001 | 1000 | 1000 | 1000 | 288 | 2 | 1 | 1001 | 0 | 0 | 1 | 1000 | 1 | 2 | 1 | 1 | 13248 | 9599 | 6959 | 3119 | 16 | 58 | 20113 | 3192 | 3811 | 21 | 48 | 50 | 28282 | 15117 | 12757 | 14348 | 1000 | 1000 | 28573 | 28598 | 28704 | 28877 | 28571 |
62004 | 28749 | 222 | 1 | 19 | 0 | 0 | 23 | 1 | 0 | 0 | 0 | 2 | 0 | 4877 | 28547 | 17869 | 2000 | 1000 | 1000 | 1000 | 1000 | 10903 | 8000 | 0 | 8 | 21689 | 0 | 28438 | 28588 | 60 | 160 | 2000 | 1000 | 1000 | 2000 | 2000 | 28695 | 28649 | 1 | 1 | 61001 | 1000 | 1000 | 1000 | 3 | 2 | 0 | 1001 | 0 | 1 | 0 | 1000 | 1 | 2 | 0 | 1 | 13159 | 9578 | 6931 | 3250 | 10 | 51 | 20013 | 3100 | 3808 | 16 | 52 | 53 | 28206 | 15546 | 12895 | 14066 | 1000 | 1000 | 28711 | 28543 | 28608 | 28773 | 28824 |
62004 | 28683 | 223 | 1 | 20 | 0 | 1 | 23 | 0 | 0 | 0 | 0 | 2 | 0 | 4810 | 28563 | 17700 | 2000 | 1000 | 1000 | 1000 | 1000 | 10907 | 8000 | 0 | 9 | 21747 | 0 | 28474 | 28781 | 3 | 10 | 2000 | 1000 | 1000 | 2000 | 2000 | 28702 | 28628 | 1 | 1 | 61001 | 1000 | 1000 | 1001 | 2 | 2 | 0 | 1001 | 0 | 1 | 1 | 1000 | 1 | 2 | 1 | 1 | 13107 | 9444 | 6970 | 3260 | 11 | 51 | 20065 | 3209 | 3803 | 22 | 50 | 49 | 28225 | 15352 | 12592 | 13975 | 1000 | 1000 | 28606 | 28771 | 28713 | 28770 | 28624 |
62004 | 28754 | 223 | 1 | 22 | 0 | 0 | 24 | 1 | 0 | 0 | 0 | 2 | 0 | 4836 | 28571 | 17687 | 2000 | 1000 | 1000 | 1000 | 1000 | 10907 | 8000 | 0 | 7 | 21689 | 0 | 28531 | 28581 | 3 | 10 | 2000 | 1000 | 1000 | 2000 | 2000 | 28608 | 28644 | 1 | 1 | 61001 | 1000 | 1000 | 1000 | 2 | 2 | 0 | 1001 | 0 | 2 | 0 | 1000 | 1 | 2 | 0 | 0 | 13408 | 9587 | 6908 | 3189 | 10 | 50 | 20123 | 3195 | 3808 | 13 | 47 | 47 | 28159 | 15369 | 12680 | 14313 | 1000 | 1000 | 28752 | 28728 | 28729 | 28618 | 28556 |
62004 | 28557 | 223 | 0 | 19 | 1 | 0 | 23 | 0 | 0 | 0 | 0 | 1 | 0 | 4910 | 28610 | 17575 | 2000 | 1000 | 1000 | 1000 | 1000 | 10900 | 8000 | 0 | 7 | 21701 | 0 | 28260 | 28627 | 3 | 10 | 2000 | 1000 | 1000 | 2000 | 2000 | 28562 | 28604 | 1 | 1 | 61001 | 1000 | 1000 | 1000 | 0 | 2 | 1 | 1000 | 0 | 0 | 4 | 1000 | 0 | 2 | 0 | 0 | 13466 | 9570 | 6996 | 3166 | 13 | 59 | 20114 | 3178 | 3810 | 18 | 56 | 48 | 28120 | 15247 | 12992 | 14265 | 1000 | 1000 | 28847 | 28668 | 28672 | 28720 | 28729 |
62004 | 28749 | 222 | 1 | 22 | 0 | 0 | 17 | 0 | 0 | 0 | 0 | 2 | 0 | 4785 | 28619 | 17689 | 2000 | 1000 | 1000 | 1000 | 1000 | 10913 | 8000 | 0 | 12 | 21726 | 0 | 28418 | 28775 | 3 | 10 | 2000 | 1000 | 1000 | 2000 | 2000 | 28587 | 28661 | 1 | 1 | 61001 | 1000 | 1000 | 1002 | 2 | 2 | 2 | 1001 | 1 | 0 | 1 | 1000 | 0 | 2 | 1 | 0 | 13552 | 9420 | 6964 | 3197 | 11 | 45 | 20073 | 3242 | 3807 | 13 | 51 | 52 | 28088 | 15302 | 12651 | 14086 | 1000 | 1000 | 28635 | 28729 | 28669 | 28629 | 28662 |
62004 | 28584 | 223 | 1 | 20 | 0 | 0 | 17 | 0 | 0 | 0 | 0 | 2 | 0 | 4822 | 28566 | 17830 | 2000 | 1000 | 1000 | 1000 | 1000 | 10906 | 8000 | 0 | 10 | 21644 | 0 | 28394 | 28739 | 3 | 10 | 2000 | 1000 | 1000 | 2000 | 2000 | 28672 | 28606 | 1 | 1 | 61001 | 1000 | 1000 | 1000 | 0 | 2 | 1 | 1000 | 0 | 2 | 1 | 1000 | 0 | 2 | 0 | 0 | 13235 | 9542 | 7009 | 3172 | 6 | 49 | 20067 | 3204 | 3805 | 15 | 51 | 52 | 27953 | 15292 | 12847 | 14325 | 1000 | 1000 | 28634 | 28727 | 28901 | 28627 | 28760 |
Count: 8
Code:
st2 { v0.b, v1.b }[1], [x6] st2 { v0.b, v1.b }[1], [x6] st2 { v0.b, v1.b }[1], [x6] st2 { v0.b, v1.b }[1], [x6] st2 { v0.b, v1.b }[1], [x6] st2 { v0.b, v1.b }[1], [x6] st2 { v0.b, v1.b }[1], [x6] st2 { v0.b, v1.b }[1], [x6]
mov x7, x6 mov x8, x6 mov x9, x6 mov x10, x6 mov x11, x6 mov x12, x6 mov x13, x6
(fused SUBS/B.cc loop)
Result (median cycles for code divided by count): 0.5005
retire uop (01) | cycle (02) | 03 | mmu table walk data (08) | 18 | 19 | 1e | 1f | 22 | 23 | 24 | 37 | 3f | 46 | 49 | 4f | 50 | 51 | schedule uop (52) | schedule int uop (53) | schedule simd uop (54) | schedule ldst uop (55) | dispatch int uop (56) | dispatch simd uop (57) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | ldst uops in schedulers (5b) | 60 | 69 | 6d | 6e | map stall dispatch (70) | rob full (74) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map simd uop (7e) | map int uop inputs (7f) | map ldst uop inputs (80) | map simd uop inputs (81) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int alu (97) | inst simd store (99) | inst ldst (9b) | 9f | l1d tlb access (a0) | l1d tlb miss (a1) | l1d cache miss st (a2) | a4 | st unit uop (a7) | l1d cache writeback (a8) | a9 | ac | af | bc | l1d cache miss st nonspec (c0) | c2 | branch cond mispred nonspec (c5) | branch mispred nonspec (cb) | cd | cf | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ? int output thing (e9) | ? ldst retires (ed) | ? simd retires (ee) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
160206 | 40058 | 311 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3165 | 40034 | 16 | 16 | 0 | 0 | 25 | 163033 | 100 | 80857 | 80000 | 100 | 80000 | 80000 | 500 | 1839712 | 644347 | 1 | 40021 | 40043 | 40049 | 19961 | 0 | 3 | 20009 | 160100 | 200 | 80000 | 80000 | 200 | 160000 | 160000 | 40048 | 40042 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 80000 | 0 | 34 | 0 | 80000 | 1 | 0 | 0 | 80002 | 2 | 0 | 0 | 0 | 0 | 0 | 5110 | 1 | 16 | 1 | 1 | 40040 | 0 | 80000 | 80000 | 100 | 40043 | 40044 | 40043 | 40043 | 40043 |
160204 | 40043 | 310 | 0 | 0 | 0 | 12 | 9 | 0 | 0 | 0 | 1383 | 40028 | 0 | 16 | 0 | 0 | 25 | 163264 | 100 | 82320 | 80000 | 100 | 80000 | 80000 | 500 | 1839712 | 650174 | 0 | 40021 | 40042 | 40043 | 19961 | 0 | 3 | 20006 | 160100 | 200 | 80000 | 80000 | 200 | 160000 | 160000 | 40043 | 40042 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 80000 | 0 | 34 | 0 | 80002 | 0 | 0 | 2 | 80002 | 2 | 34 | 0 | 0 | 0 | 0 | 5110 | 1 | 16 | 1 | 1 | 40046 | 0 | 80000 | 80000 | 100 | 40043 | 40044 | 40043 | 40044 | 40044 |
160204 | 40043 | 310 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | 1039 | 40027 | 0 | 0 | 0 | 0 | 25 | 163642 | 100 | 81386 | 80000 | 100 | 80000 | 80000 | 500 | 1846326 | 649221 | 0 | 40024 | 40048 | 40043 | 19959 | 0 | 3 | 20001 | 160100 | 200 | 80000 | 80000 | 200 | 160000 | 160240 | 40356 | 40049 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 80000 | 0 | 34 | 0 | 80002 | 0 | 0 | 0 | 80002 | 2 | 34 | 0 | 0 | 0 | 0 | 5110 | 1 | 16 | 1 | 1 | 40040 | 0 | 80000 | 80000 | 100 | 40043 | 40044 | 40043 | 40044 | 40050 |
160204 | 40043 | 311 | 0 | 0 | 0 | 12 | 0 | 0 | 0 | 0 | 1838 | 40027 | 0 | 16 | 1 | 0 | 25 | 161244 | 100 | 83903 | 80000 | 100 | 80000 | 80000 | 500 | 1839712 | 644347 | 0 | 40021 | 40042 | 40043 | 19961 | 0 | 3 | 20006 | 160100 | 200 | 80000 | 80000 | 200 | 160000 | 160000 | 40042 | 40042 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 80000 | 0 | 0 | 0 | 80000 | 0 | 0 | 8 | 80002 | 2 | 34 | 0 | 0 | 0 | 0 | 5110 | 1 | 16 | 1 | 1 | 40039 | 0 | 80000 | 80000 | 100 | 40044 | 40043 | 40043 | 40043 | 40050 |
160204 | 40042 | 311 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | 3275 | 40028 | 16 | 16 | 0 | 0 | 25 | 162304 | 100 | 81345 | 80000 | 100 | 80000 | 80000 | 500 | 1839712 | 644084 | 0 | 40021 | 40043 | 40042 | 19959 | 0 | 3 | 20000 | 160100 | 200 | 80000 | 80000 | 200 | 160000 | 160000 | 40042 | 40043 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 80000 | 0 | 34 | 0 | 80002 | 0 | 0 | 2 | 80002 | 2 | 34 | 0 | 0 | 0 | 0 | 5110 | 1 | 16 | 1 | 1 | 40040 | 0 | 80000 | 80000 | 100 | 40043 | 40043 | 40044 | 40043 | 40044 |
160204 | 40042 | 310 | 0 | 0 | 0 | 0 | 3 | 1 | 0 | 0 | 1445 | 40027 | 16 | 0 | 2 | 0 | 25 | 162647 | 100 | 83350 | 80000 | 100 | 80000 | 80000 | 500 | 1839712 | 648813 | 0 | 40021 | 40042 | 40042 | 19962 | 0 | 3 | 20006 | 160100 | 200 | 80000 | 80000 | 200 | 160000 | 160000 | 40043 | 40042 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 80000 | 0 | 0 | 0 | 80002 | 1 | 0 | 2 | 80000 | 2 | 34 | 0 | 0 | 0 | 0 | 5110 | 1 | 16 | 1 | 1 | 40039 | 0 | 80000 | 80000 | 100 | 40044 | 40049 | 40044 | 40049 | 40044 |
160204 | 40042 | 311 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | 1132 | 40027 | 16 | 0 | 0 | 0 | 25 | 161988 | 100 | 83278 | 80000 | 100 | 80000 | 80000 | 500 | 1839832 | 647685 | 0 | 40021 | 40043 | 40042 | 19959 | 0 | 3 | 20007 | 160100 | 200 | 80000 | 80000 | 200 | 160000 | 160000 | 40048 | 40043 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 80000 | 0 | 34 | 0 | 80002 | 0 | 0 | 2 | 80002 | 2 | 34 | 0 | 0 | 0 | 0 | 5110 | 1 | 16 | 1 | 1 | 40040 | 0 | 80000 | 80000 | 100 | 40050 | 40049 | 40064 | 40050 | 40043 |
160204 | 40049 | 310 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2012 | 40027 | 16 | 16 | 0 | 0 | 25 | 164072 | 100 | 82891 | 80000 | 100 | 80000 | 80000 | 500 | 1839712 | 647649 | 0 | 40021 | 40042 | 40043 | 19959 | 0 | 3 | 20001 | 160100 | 200 | 80000 | 80000 | 200 | 160240 | 160000 | 40048 | 40043 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 80000 | 0 | 34 | 0 | 80002 | 0 | 0 | 3 | 80002 | 2 | 34 | 0 | 0 | 0 | 0 | 5110 | 1 | 16 | 1 | 1 | 40045 | 0 | 80000 | 80000 | 100 | 40049 | 40044 | 40043 | 40044 | 40044 |
160204 | 40043 | 310 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2939 | 40034 | 16 | 16 | 0 | 0 | 25 | 163465 | 100 | 83154 | 80000 | 100 | 80000 | 80000 | 500 | 1839712 | 648680 | 0 | 40021 | 40043 | 40042 | 19962 | 0 | 3 | 20007 | 160100 | 200 | 80000 | 80000 | 200 | 160000 | 160000 | 40042 | 40043 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 80000 | 0 | 34 | 0 | 80002 | 0 | 0 | 0 | 80002 | 2 | 34 | 0 | 0 | 0 | 0 | 5110 | 1 | 16 | 1 | 1 | 40046 | 0 | 80000 | 80000 | 100 | 40043 | 40044 | 40043 | 40044 | 40050 |
160204 | 40043 | 310 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | 2124 | 40027 | 16 | 16 | 0 | 0 | 25 | 162343 | 100 | 83058 | 80000 | 100 | 80000 | 80000 | 500 | 1839712 | 650174 | 0 | 40021 | 40042 | 40043 | 19959 | 0 | 3 | 20001 | 160100 | 200 | 80000 | 80000 | 200 | 160000 | 160000 | 40048 | 40042 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 80000 | 0 | 34 | 0 | 80002 | 1 | 0 | 0 | 80002 | 2 | 34 | 0 | 0 | 0 | 0 | 5110 | 1 | 16 | 1 | 1 | 40039 | 0 | 80000 | 80000 | 100 | 40049 | 40043 | 40043 | 40050 | 40043 |
Result (median cycles for code divided by count): 0.5007
retire uop (01) | cycle (02) | 03 | l1d tlb fill (05) | mmu table walk data (08) | 09 | l2 tlb miss data (0b) | 18 | 19 | 1e | 1f | 23 | 24 | 37 | 3a | 3f | 46 | 49 | 4f | 51 | schedule uop (52) | schedule int uop (53) | schedule simd uop (54) | schedule ldst uop (55) | dispatch int uop (56) | dispatch simd uop (57) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | ldst uops in schedulers (5b) | 60 | 69 | 6b | 6d | 6e | map stall dispatch (70) | rob full (74) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map simd uop (7e) | map int uop inputs (7f) | map ldst uop inputs (80) | map simd uop inputs (81) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int alu (97) | inst simd store (99) | inst ldst (9b) | 9f | l1d tlb access (a0) | l1d tlb miss (a1) | l1d cache miss st (a2) | a4 | ld unit uop (a6) | st unit uop (a7) | l1d cache writeback (a8) | a9 | ac | af | bc | l1d cache miss st nonspec (c0) | l1d tlb miss nonspec (c1) | c2 | branch mispred nonspec (cb) | cf | d2 | l1i cache miss demand (d3) | d5 | map dispatch bubble (d6) | da | dd | fetch restart (de) | e0 | ? ldst retires (ed) | ? simd retires (ee) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
160026 | 40051 | 310 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 17 | 0 | 0 | 4798 | 1 | 40047 | 16 | 16 | 0 | 25 | 160800 | 10 | 81978 | 80000 | 10 | 80000 | 80000 | 50 | 1840456 | 648962 | 0 | 40026 | 0 | 40054 | 40053 | 19988 | 0 | 3 | 20042 | 160010 | 20 | 80000 | 80000 | 20 | 160000 | 160000 | 40052 | 40055 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 80014 | 14 | 44 | 0 | 1 | 80016 | 0 | 0 | 16 | 80002 | 16 | 44 | 14 | 0 | 0 | 5020 | 0 | 2 | 1 | 16 | 0 | 1 | 1 | 40050 | 80000 | 80000 | 10 | 40063 | 40063 | 40053 | 40064 | 40055 |
160024 | 40052 | 310 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 18 | 0 | 0 | 4416 | 1 | 40038 | 16 | 16 | 1 | 25 | 164013 | 10 | 81783 | 80000 | 10 | 80000 | 80000 | 50 | 1840048 | 650903 | 0 | 40029 | 0 | 40052 | 40054 | 19989 | 0 | 3 | 20043 | 160010 | 20 | 80000 | 80000 | 20 | 160000 | 160000 | 40052 | 40054 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 80016 | 15 | 44 | 0 | 0 | 80016 | 0 | 0 | 16 | 80002 | 16 | 44 | 14 | 0 | 0 | 5020 | 0 | 1 | 2 | 16 | 0 | 1 | 1 | 40059 | 80000 | 80000 | 10 | 40054 | 40055 | 40054 | 40055 | 40052 |
160024 | 40054 | 311 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 20 | 0 | 0 | 2333 | 1 | 40037 | 16 | 16 | 0 | 25 | 162743 | 10 | 82533 | 80000 | 10 | 80000 | 80000 | 50 | 1840072 | 654851 | 0 | 40037 | 0 | 40051 | 40062 | 19988 | 0 | 3 | 20032 | 160010 | 20 | 80000 | 80000 | 20 | 160000 | 160000 | 40453 | 40264 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 80014 | 15 | 44 | 2 | 0 | 80016 | 0 | 0 | 18 | 80002 | 16 | 44 | 14 | 0 | 0 | 5020 | 0 | 1 | 2 | 16 | 0 | 1 | 1 | 40044 | 80000 | 80000 | 10 | 40055 | 40055 | 40051 | 40055 | 40054 |
160024 | 40056 | 310 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 17 | 0 | 0 | 2189 | 1 | 40038 | 16 | 16 | 1 | 25 | 161531 | 10 | 82497 | 80000 | 10 | 80000 | 80000 | 50 | 1840072 | 645531 | 0 | 40029 | 0 | 40052 | 40054 | 19989 | 0 | 3 | 20042 | 160010 | 20 | 80000 | 80000 | 20 | 160000 | 160000 | 40051 | 40054 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 80015 | 14 | 44 | 0 | 0 | 80016 | 0 | 1 | 17 | 80002 | 16 | 44 | 14 | 1 | 0 | 5020 | 0 | 2 | 2 | 16 | 0 | 1 | 1 | 40052 | 80000 | 80000 | 10 | 40054 | 40054 | 40055 | 40056 | 40048 |
160024 | 40054 | 310 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 18 | 0 | 0 | 413 | 1 | 40039 | 16 | 16 | 1 | 25 | 164104 | 10 | 84221 | 80000 | 10 | 80000 | 80000 | 50 | 1840096 | 647821 | 0 | 40038 | 0 | 40052 | 40062 | 19990 | 0 | 3 | 20031 | 160010 | 20 | 80000 | 80000 | 20 | 160000 | 160000 | 40053 | 40052 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 80014 | 15 | 43 | 0 | 0 | 80016 | 0 | 0 | 16 | 80002 | 16 | 46 | 14 | 0 | 0 | 5038 | 0 | 1 | 1 | 25 | 0 | 3 | 1 | 40059 | 80000 | 80000 | 10 | 40055 | 40054 | 40055 | 40054 | 40052 |
160024 | 40055 | 310 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 14 | 0 | 0 | 859 | 1 | 40035 | 16 | 16 | 1 | 25 | 162341 | 10 | 82261 | 80000 | 10 | 80000 | 80000 | 50 | 1840456 | 647880 | 0 | 40026 | 0 | 40053 | 40051 | 19987 | 0 | 3 | 20033 | 160010 | 20 | 80000 | 80000 | 20 | 160000 | 160000 | 40054 | 40052 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 80014 | 15 | 44 | 0 | 0 | 80016 | 0 | 1 | 16 | 80002 | 15 | 59 | 14 | 1 | 0 | 5020 | 0 | 1 | 3 | 151 | 0 | 1 | 1 | 40058 | 80000 | 80000 | 10 | 40063 | 40062 | 40063 | 40062 | 40063 |
160024 | 40052 | 322 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 20 | 0 | 0 | 1519 | 1 | 40047 | 16 | 19 | 5 | 49 | 163338 | 10 | 81597 | 80000 | 10 | 80000 | 80000 | 50 | 1840408 | 640956 | 0 | 40037 | 0 | 40066 | 40060 | 19995 | 0 | 3 | 20042 | 160010 | 20 | 80000 | 80000 | 20 | 160000 | 160000 | 40061 | 40061 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 80014 | 14 | 61 | 102 | 1 | 80015 | 0 | 1 | 16 | 80001 | 15 | 63 | 14 | 1 | 0 | 5020 | 8 | 0 | 1 | 16 | 0 | 1 | 1 | 40060 | 80000 | 80000 | 10 | 40054 | 40055 | 40055 | 40055 | 40052 |
160024 | 40054 | 322 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 21 | 0 | 0 | 1586 | 1 | 40036 | 0 | 16 | 1 | 25 | 160254 | 10 | 82186 | 80000 | 10 | 80000 | 80000 | 50 | 1840120 | 646557 | 0 | 40027 | 0 | 40054 | 40052 | 19997 | 0 | 3 | 20031 | 160010 | 20 | 80000 | 80000 | 20 | 160000 | 160000 | 40051 | 40056 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 80014 | 14 | 46 | 101 | 0 | 80016 | 1 | 0 | 23 | 80002 | 16 | 44 | 14 | 0 | 0 | 5020 | 2 | 0 | 2 | 16 | 0 | 1 | 1 | 40057 | 80000 | 80000 | 10 | 40064 | 40063 | 40063 | 40063 | 40062 |
160024 | 40061 | 321 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 17 | 0 | 0 | 4461 | 1 | 40035 | 19 | 18 | 7 | 25 | 163316 | 10 | 81662 | 80000 | 10 | 80000 | 80000 | 50 | 1840408 | 649333 | 0 | 40036 | 0 | 40061 | 40055 | 19997 | 0 | 3 | 20041 | 160010 | 20 | 80000 | 80000 | 20 | 160000 | 160000 | 40060 | 40062 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 80014 | 14 | 0 | 7 | 0 | 80015 | 0 | 1 | 15 | 80001 | 16 | 44 | 14 | 0 | 0 | 5020 | 4 | 0 | 1 | 16 | 0 | 1 | 1 | 40050 | 80000 | 80000 | 10 | 40063 | 40063 | 40064 | 40063 | 40055 |
160024 | 40051 | 310 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 19 | 0 | 0 | 1039 | 1 | 40039 | 16 | 16 | 1 | 25 | 161799 | 10 | 82665 | 80000 | 10 | 80000 | 80000 | 50 | 1840096 | 647498 | 0 | 40027 | 0 | 40053 | 40051 | 19997 | 0 | 3 | 20033 | 160010 | 20 | 80000 | 80000 | 20 | 160000 | 160000 | 40054 | 40051 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 80014 | 14 | 42 | 3 | 0 | 80016 | 0 | 0 | 18 | 80002 | 16 | 44 | 14 | 1 | 0 | 5020 | 1 | 0 | 2 | 16 | 0 | 1 | 1 | 40049 | 80000 | 80000 | 10 | 40055 | 40056 | 40055 | 40055 | 40054 |