Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

ST2 (single, D)

Test 1: uops

Code:

  st2 { v0.d, v1.d }[1], [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop
  mov x0, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 2.000

Issues: 2.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)03l1i tlb fill (04)l1d tlb fill (05)mmu table walk instruction (07)mmu table walk data (08)09l2 tlb miss instruction (0a)l2 tlb miss data (0b)181e1f22233a3f464951schedule uop (52)schedule simd uop (54)schedule ldst uop (55)dispatch simd uop (57)dispatch ldst uop (58)simd uops in schedulers (5a)ldst uops in schedulers (5b)5f6061696d6emap rewind (75)map stall (76)dispatch uop (78)map ldst uop (7d)map simd uop (7e)map ldst uop inputs (80)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd store (99)inst ldst (9b)l1d tlb access (a0)l1d tlb miss (a1)l1d cache miss st (a2)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acafbcl1d cache miss st nonspec (c0)l1d tlb miss nonspec (c1)c2cfd0d2l1i cache miss demand (d3)l1i tlb miss demand (d4)d5map dispatch bubble (d6)d9dadbddfetch restart (de)e0eaebec? ldst retires (ed)? simd retires (ee)f5f6f7f8fd
6200628552211012410191130200517128207101758420001000100010001000109068000309218072814928212310200010001000200020022837128200216100110001000100120110011211000101113305925469773286852203483187381520525528219163351342415135100010002923329256292462925029357
6200429470220011601211033100464129085001834720001000100010001000109068000100217112893529387310200010001000200020002926329242116100110001000100212010010211000101112835907268693090848206273061381517535328463163241347515052100010002931929274293372925129309
620042927822001160115000100453729073001834320001000100010001000109098000200217302890829313310200010001000200020002923229215116100110001000100222210010111000221012975912668243058650207083059381820534828506163101347115148100010002928929347293402936629275
620042933821911170114000100454929140001824420001000100010001000109078000100216972896629274310200010001000200020002929729275116100110001000100122010010111000121113255903368303072356207683243381416617928061140651180013134100010002852828381283282831628412
6200428201212011210141003005249282060017253200010001000100010001090480007002179428068281863102000100010002000200028216282651161001100010001003120100100110011311139471019771163352843198353358381516454927845143031194012771100010002866528886287362883628363
6200428296212011710171002005139282760017438200010001000100010001090780006002172928153282353102000100010002000200028205283531161001100010001002230100113210001010138521006671333365649196993313381615535528047143041214913143100010002845128436284692848028370
6200428433212111510151062005104282090017270200010001000100010001090380006002175228169283513102000100010002000200028154280921161001100010001001232100110210001010138471023772803473250195473245381311465227990143501234012922100010002845428401283112835428396
6200428168213012100140062005115282100017334200010001000100010001091280005002178827922281263102000100010002000200028384282951161001100010001002231100100110001411136541023471993415651196413402381910485027963143631183513230100010002855828506282322828628189
62004284152130116077291002005003284300017433200010001000100010001090780005002178728264287693102000100010002000200028100282271161001100010001001131100100110001312138391018971613365352195983315381418485228078140921216213306100010002840728427283082841028220
6200428226212011410171001004999282910017436200010001000100010001090980006002175328080283043102000100010002000200028236282911161001100010001002120100101110001310140061031771993442750197033373381810525227845141041252512691100010002835528382283492843528328

Test 2: throughput

Count: 8

Code:

  st2 { v0.d, v1.d }[1], [x6]
  st2 { v0.d, v1.d }[1], [x6]
  st2 { v0.d, v1.d }[1], [x6]
  st2 { v0.d, v1.d }[1], [x6]
  st2 { v0.d, v1.d }[1], [x6]
  st2 { v0.d, v1.d }[1], [x6]
  st2 { v0.d, v1.d }[1], [x6]
  st2 { v0.d, v1.d }[1], [x6]
  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5005

retire uop (01)cycle (02)030f18191e1f22373f46494f51schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)rob full (74)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd store (99)inst ldst (9b)9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache miss st (a2)a4st unit uop (a7)l1d cache writeback (a8)acafbcl1d cache miss st nonspec (c0)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? ldst retires (ed)? simd retires (ee)? int retires (ef)f5f6f7f8fd
16020640042311000000138640027161602516177110082021800001008000080000500183985664546004021940532400432015603200001601002008000080000200160000160000400424004311802011009910010080000800001008000003408000202800022345110116114003980000800001004005040049400494004440043
16020440043310000030293340028161602516343610083877800001008000080000500183983264343204002140043400421995903200001601002008024080120200160000160000400424004311802011009910010080000800001008000003408000202800022345110116114004580000800001004004440043400444024740043
160204402503220001323029334002816160471615301008098780000100800008010850018398086503650400234004340048199620320000161220200800008000020016000016023840042400431180201100991001008000080000100800000341978000002800022345110125114023880000800001004004340044402484004340050
1602044004331110013230293140028161605116407810081358800001008000080000511183971265036604002140043400421995903201621601002008000080000200160000160000400484004311802011009910010080000800001008000023408000202800622345110116114003980000800001004005040050402514004940043
16020440043310000030375040027161602516284610082631800001008000080000500183971264369604002140042400421995903200071601002008000080000200160000160000400434004911802011009910010080000800001008000003608000201117800002345110116124003980000800001004004340043400444004340043
160204400423120100013272400331616025163031100818838000010080000800005001839712642847040021400434025119959011200071601002028000080000200160000160000400424004311802011009910010080000800001008006203408006202800022345110116114022980000800001004025340050400534004940043
1602044004331000003013404002716160251631831008146080000100800008000050018397126449830400234004340048199620320162160100200801208000020016000016000040042400422180201100991001008000080000100800620008006202800022345110116114023080000800001004024940043400434004340043
16020440049311000030328840028160025162731100827668000010080000800005001839832644988040023400424004319962032016516010020080120800002001600001600004004340042118020110099100100800008000010080000034080002111800002345110116114004080000800001004005040050400504005040043
16020440042310000030173840028161612516208010081116800001008000080000500183971265002004002140042400431995903200011601002008000080000200160000160000400434004211802011009910010080000800001008000003408000002800020365110116114004980000800001004004440043400444004340043
16020440042310000123036314002716002516177110083973800001008000080000500183971265128204002140043400421995903200001601002008000080000200160000160000400424004311802011009910010080000800001008000003408000202800022345110116114004080000800001004004340044400434004440044

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5005

retire uop (01)cycle (02)03mmu table walk data (08)09l2 tlb miss data (0b)18191e1f2223373f46494f51schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)5f60696d6emap stall dispatch (70)rob full (74)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd store (99)inst ldst (9b)9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache miss st (a2)a4ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acafbcl1d cache miss st nonspec (c0)c2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? ldst retires (ed)? simd retires (ee)? int retires (ef)f5f6f7f8fd
160026400423100000003004034400280160251607681084035800001080000800005018397126401820140021400424004219982032002216001020800008000020160000160000400494004311800211091010800008000010800000340080002000800020340502051675400468000080000104004340044400434004440043
1600244004831000000030054340027160025160056108362380000108000080000501839712640216014002140043400481998203200231600102080000800002016000016000040048400431180021109101080000800001080000000080002005800020340502061657400408000080000104004440043400444004342258
16002440043310000001230014564002716160251616521082907800001080000800005018398566424491140021400424004319984032002216001020800008000020160000160000400494004211800211091010800008000010800000340080002108800022340502061756400398000080000104004340043400444004340049
16002440048310000000000722400271600251630871080387800601080000800005018398086414670040021400424004919982032002216001020800008000020160000160000400434004211800211091010800008000010800000380080002108800022340502051665400398000080000104004340044400434004440048
160024400493100000003005814002716160251604591083075800001080000800005018398086422030040021400434004219982032002316001020800008000020160000160000400494004311800211091010800008000010800000340080002002800002340502061666400398000080000104024440044400434004440043
160024400483100000006006004002716160251621171084494800001080000800005018397126425810040021400424004219982032002216001020800008000020160000160000400474004211800211091010800008000010800000380080002005800022340502061657400408000080000104004440050400494004440049
160024400433100000000003223400281600251608251083081800001080000800005018397126417350040024400494004319982032002816001020800008000020160000160000400424004911800211091010800008000010800000340080002008800002340502061666400398000080000104005040049400444004340043
1600244004231000000030036784003416160251630871083875800001080000800005018397126539620040021400424004319984032002216001020800008000020160000160000400484004211800211091010800008000010800000340080002005800022440502051666400398000080000104004440049400504005040044
16002440043310000001230058040027161602516142010829048000010800008000050183980864269200400214004340048199820320023160010208000080000201600001600004004240042118002110910108000080000108000000008000210280002200502071665400398000080000104004440043400494005440043
1600244004331000000091012114002716160251601061080815800001080000800005018397126421930040021400434004819982032002316001020800008000020160000160000400494004211800211091010800008000010800000340080002125800022340502051665400408000080000104004440043400444004340043