Apple Microarchitecture Research by Dougall Johnson M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions M1/A14 E-core (Icestorm): Overview | Base Instructions | SIMD and FP Instructions
Code:
st2 { v0.b, v1.b }[1], [x6], x8 nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop
mov x0, 0 mov x8, 0
(no loop instructions)
Retires (minus 60 nops): 2.000
Issues: 3.000
Integer unit issues: 1.000
Load/store unit issues: 1.000
SIMD/FP unit issues: 1.000
retire uop (01) | cycle (02) | 03 | mmu table walk instruction (07) | mmu table walk data (08) | l2 tlb miss instruction (0a) | l2 tlb miss data (0b) | 18 | 19 | 1e | 1f | 22 | 24 | 3a | 3f | 46 | 49 | 51 | schedule uop (52) | schedule int uop (53) | schedule simd uop (54) | schedule ldst uop (55) | dispatch int uop (56) | dispatch simd uop (57) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | ldst uops in schedulers (5b) | 5f | 69 | 6d | 6e | map rewind (75) | map stall (76) | dispatch uop (78) | map ldst uop (7d) | map simd uop (7e) | map ldst uop inputs (80) | map simd uop inputs (81) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst simd store (99) | inst ldst (9b) | l1d tlb access (a0) | l1d tlb miss (a1) | l1d cache miss st (a2) | ld unit uop (a6) | st unit uop (a7) | l1d cache writeback (a8) | a9 | ac | af | bc | l1d cache miss st nonspec (c0) | c2 | c9 | cf | d0 | d2 | l1i cache miss demand (d3) | l1i tlb miss demand (d4) | d5 | map dispatch bubble (d6) | d9 | da | db | dd | fetch restart (de) | df | e0 | ? int output thing (e9) | ea | eb | ec | ? ldst retires (ed) | ? simd retires (ee) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
62006 | 28733 | 222 | 19 | 0 | 19 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 4751 | 28563 | 1 | 1 | 17607 | 3000 | 1000 | 1000 | 1000 | 1000 | 1000 | 1000 | 5000 | 10901 | 8000 | 15 | 21664 | 28302 | 28547 | 3 | 10 | 3000 | 1000 | 1000 | 3000 | 2000 | 28518 | 28576 | 1 | 1 | 61001 | 1000 | 1000 | 1000 | 0 | 0 | 0 | 1000 | 0 | 0 | 0 | 1000 | 0 | 0 | 0 | 0 | 13316 | 9400 | 6974 | 3211 | 7 | 40 | 20010 | 3200 | 3814 | 10 | 34 | 31 | 2 | 28186 | 1000 | 15537 | 12669 | 13640 | 1000 | 1000 | 1000 | 28620 | 28659 | 28643 | 28688 | 28668 |
62004 | 28573 | 221 | 15 | 0 | 15 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4711 | 28503 | 1 | 1 | 17589 | 3000 | 1000 | 1000 | 1000 | 1000 | 1000 | 1000 | 5000 | 10906 | 8000 | 15 | 21721 | 28520 | 28698 | 3 | 10 | 3000 | 1000 | 1000 | 3000 | 2000 | 28658 | 28538 | 1 | 1 | 61001 | 1000 | 1000 | 1000 | 0 | 3 | 0 | 1000 | 1 | 0 | 0 | 1000 | 0 | 3 | 0 | 0 | 13311 | 9670 | 6839 | 3208 | 9 | 42 | 19832 | 3180 | 3801 | 13 | 37 | 34 | 2 | 28193 | 1000 | 15396 | 12629 | 13470 | 1000 | 1000 | 1000 | 28613 | 28695 | 28581 | 28732 | 28609 |
62004 | 28723 | 222 | 15 | 0 | 19 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4824 | 28527 | 0 | 1 | 17667 | 3000 | 1000 | 1000 | 1000 | 1000 | 1000 | 1000 | 5000 | 10900 | 8000 | 1 | 21699 | 28364 | 28603 | 3 | 10 | 3000 | 1000 | 1000 | 3000 | 2000 | 28722 | 28695 | 1 | 1 | 61001 | 1000 | 1000 | 1000 | 0 | 3 | 0 | 1000 | 0 | 0 | 0 | 1000 | 0 | 3 | 0 | 0 | 13422 | 9563 | 6949 | 3164 | 9 | 33 | 20001 | 3111 | 3810 | 14 | 34 | 38 | 2 | 28211 | 1000 | 15491 | 12585 | 13572 | 1000 | 1000 | 1000 | 28658 | 28476 | 28643 | 28616 | 28685 |
62004 | 28656 | 222 | 16 | 0 | 16 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 4723 | 28661 | 1 | 0 | 17676 | 3000 | 1000 | 1000 | 1000 | 1000 | 1000 | 1000 | 5000 | 10902 | 8000 | 11 | 21710 | 28372 | 28669 | 3 | 10 | 3000 | 1000 | 1002 | 3000 | 2000 | 28595 | 28600 | 1 | 1 | 61001 | 1000 | 1000 | 1000 | 0 | 3 | 0 | 1000 | 0 | 0 | 0 | 1000 | 0 | 2 | 0 | 0 | 13286 | 9402 | 6898 | 3123 | 4 | 35 | 20005 | 3085 | 3804 | 16 | 30 | 30 | 2 | 28155 | 1000 | 15252 | 12472 | 13984 | 1000 | 1000 | 1000 | 28531 | 28629 | 28516 | 28567 | 28668 |
62004 | 28589 | 221 | 21 | 0 | 16 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 4780 | 28445 | 0 | 0 | 17603 | 3000 | 1000 | 1000 | 1000 | 1000 | 1000 | 1000 | 5000 | 10902 | 8000 | 6 | 21689 | 28358 | 28703 | 3 | 10 | 3000 | 1000 | 1000 | 3000 | 2000 | 28616 | 28474 | 1 | 1 | 61001 | 1000 | 1000 | 1000 | 0 | 3 | 0 | 1000 | 0 | 0 | 0 | 1000 | 0 | 3 | 0 | 0 | 13329 | 9544 | 6966 | 3106 | 10 | 34 | 19979 | 3221 | 3820 | 13 | 32 | 34 | 2 | 28284 | 1000 | 15381 | 12691 | 13821 | 1000 | 1000 | 1000 | 28665 | 28556 | 28662 | 28697 | 28624 |
62004 | 28686 | 223 | 18 | 0 | 10 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4745 | 28564 | 1 | 0 | 17592 | 3000 | 1000 | 1000 | 1000 | 1000 | 1000 | 1000 | 5000 | 10900 | 8000 | 5 | 21775 | 28451 | 28779 | 3 | 10 | 3000 | 1000 | 1000 | 3000 | 2000 | 28597 | 28639 | 1 | 1 | 61001 | 1000 | 1000 | 1000 | 0 | 2 | 0 | 1000 | 0 | 0 | 0 | 1000 | 0 | 2 | 0 | 0 | 13012 | 9482 | 7002 | 3163 | 7 | 34 | 20040 | 3197 | 3811 | 9 | 31 | 35 | 2 | 28226 | 1000 | 15227 | 12797 | 13677 | 1000 | 1000 | 1000 | 28647 | 28613 | 28709 | 28631 | 28612 |
62004 | 28734 | 221 | 12 | 0 | 18 | 0 | 0 | 0 | 9 | 0 | 0 | 0 | 4870 | 28580 | 0 | 0 | 17606 | 3000 | 1000 | 1000 | 1000 | 1000 | 1000 | 1000 | 5000 | 10906 | 8000 | 1 | 21738 | 28510 | 28700 | 3 | 10 | 3000 | 1000 | 1000 | 3000 | 2000 | 28611 | 28571 | 1 | 1 | 61001 | 1000 | 1000 | 1000 | 0 | 2 | 0 | 1000 | 0 | 0 | 0 | 1000 | 0 | 2 | 0 | 0 | 13090 | 9552 | 6950 | 3127 | 7 | 33 | 20054 | 3220 | 3817 | 19 | 33 | 35 | 2 | 28217 | 1000 | 15057 | 12640 | 13542 | 1000 | 1000 | 1000 | 28549 | 28643 | 28569 | 28645 | 28591 |
62004 | 28736 | 223 | 19 | 0 | 19 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 4757 | 28540 | 0 | 0 | 17672 | 3000 | 1000 | 1000 | 1000 | 1000 | 1000 | 1000 | 5000 | 10899 | 8000 | 3 | 21747 | 28364 | 28633 | 3 | 10 | 3000 | 1000 | 1000 | 3000 | 2000 | 28599 | 28577 | 1 | 1 | 61001 | 1000 | 1000 | 1000 | 0 | 2 | 0 | 1000 | 0 | 0 | 0 | 1000 | 0 | 2 | 0 | 0 | 13141 | 9669 | 6977 | 3198 | 5 | 31 | 19987 | 3275 | 3812 | 7 | 36 | 35 | 2 | 28153 | 1000 | 15140 | 12656 | 13306 | 1000 | 1000 | 1000 | 28685 | 28677 | 28687 | 28688 | 28627 |
62004 | 28702 | 221 | 13 | 0 | 15 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4818 | 28542 | 0 | 0 | 17672 | 3000 | 1000 | 1000 | 1000 | 1000 | 1000 | 1000 | 5000 | 10905 | 8000 | 5 | 21720 | 28510 | 28661 | 3 | 10 | 3000 | 1002 | 1000 | 3000 | 2000 | 28717 | 28616 | 1 | 1 | 61001 | 1000 | 1000 | 1000 | 0 | 0 | 0 | 1000 | 0 | 0 | 0 | 1000 | 0 | 0 | 0 | 0 | 13100 | 9706 | 6969 | 3117 | 6 | 43 | 20147 | 3234 | 3816 | 14 | 35 | 39 | 2 | 28263 | 1000 | 15546 | 12548 | 13573 | 1000 | 1000 | 1000 | 28582 | 28683 | 28717 | 28636 | 28736 |
62004 | 28647 | 222 | 18 | 0 | 12 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 4735 | 28548 | 0 | 0 | 17653 | 3000 | 1000 | 1000 | 1000 | 1000 | 1000 | 1000 | 5000 | 10905 | 8000 | 0 | 21732 | 28483 | 28670 | 3 | 10 | 3000 | 1000 | 1000 | 3000 | 2000 | 28621 | 28624 | 1 | 1 | 61001 | 1000 | 1000 | 1000 | 0 | 0 | 0 | 1000 | 0 | 0 | 0 | 1000 | 1 | 0 | 0 | 0 | 13161 | 9603 | 7014 | 3143 | 5 | 27 | 20152 | 3304 | 3814 | 10 | 32 | 34 | 2 | 28188 | 1000 | 15608 | 12377 | 13831 | 1000 | 1000 | 1000 | 28755 | 28670 | 28707 | 28808 | 28750 |
Count: 8
Code:
st2 { v0.b, v1.b }[1], [x6], x8 st2 { v0.b, v1.b }[1], [x6], x8 st2 { v0.b, v1.b }[1], [x6], x8 st2 { v0.b, v1.b }[1], [x6], x8 st2 { v0.b, v1.b }[1], [x6], x8 st2 { v0.b, v1.b }[1], [x6], x8 st2 { v0.b, v1.b }[1], [x6], x8 st2 { v0.b, v1.b }[1], [x6], x8
mov x7, x6 mov x8, x6 mov x9, x6 mov x10, x6 mov x11, x6 mov x12, x6 mov x13, x6 mov x8, 0
(fused SUBS/B.cc loop)
Result (median cycles for code divided by count): 1.0005
retire uop (01) | cycle (02) | 03 | l1d tlb fill (05) | mmu table walk data (08) | 09 | l2 tlb miss data (0b) | 18 | 19 | 1e | 1f | 24 | 37 | 3a | 3f | 46 | 49 | 4f | 51 | schedule uop (52) | schedule int uop (53) | schedule simd uop (54) | schedule ldst uop (55) | dispatch int uop (56) | dispatch simd uop (57) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | ldst uops in schedulers (5b) | 60 | 69 | 6b | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map simd uop (7e) | map int uop inputs (7f) | map ldst uop inputs (80) | map simd uop inputs (81) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int alu (97) | inst simd store (99) | inst ldst (9b) | 9f | l1d tlb access (a0) | l1d tlb miss (a1) | l1d cache miss st (a2) | a4 | ld unit uop (a6) | st unit uop (a7) | l1d cache writeback (a8) | a9 | ac | af | bc | l1d cache miss st nonspec (c0) | l1d tlb miss nonspec (c1) | c2 | branch mispred nonspec (cb) | cf | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ? int output thing (e9) | ec | ? ldst retires (ed) | ? simd retires (ee) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
160206 | 80040 | 620 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0 | 5169 | 0 | 80025 | 8 | 8 | 0 | 25 | 242958 | 80100 | 85168 | 80000 | 80100 | 80000 | 80000 | 4359014 | 3758848 | 645529 | 0 | 80015 | 3 | 80040 | 80040 | 59924 | 3 | 59998 | 240100 | 200 | 80000 | 80000 | 200 | 240000 | 160000 | 80040 | 80040 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 80000 | 0 | 0 | 0 | 0 | 80001 | 15 | 0 | 1 | 80000 | 1 | 21 | 0 | 0 | 0 | 5110 | 1 | 16 | 1 | 1 | 80143 | 80000 | 0 | 80000 | 80000 | 80100 | 80041 | 80041 | 80041 | 80041 | 80041 |
160204 | 80040 | 621 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0 | 2406 | 0 | 80025 | 0 | 8 | 1 | 25 | 241901 | 80100 | 82307 | 80000 | 80100 | 80000 | 80000 | 4359014 | 3758848 | 646889 | 0 | 80015 | 0 | 80040 | 80040 | 59924 | 3 | 59998 | 240100 | 200 | 80000 | 80000 | 200 | 240000 | 160000 | 80040 | 80040 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 80000 | 0 | 21 | 0 | 0 | 80001 | 58 | 0 | 29201 | 80001 | 0 | 21 | 0 | 0 | 0 | 5110 | 1 | 16 | 1 | 1 | 80037 | 80000 | 0 | 80000 | 80000 | 80100 | 80041 | 80041 | 80162 | 80041 | 80041 |
160204 | 80040 | 620 | 0 | 0 | 0 | 0 | 0 | 0 | 12 | 2 | 0 | 1902 | 0 | 80025 | 8 | 8 | 1 | 25 | 242399 | 80100 | 86040 | 80000 | 80100 | 80000 | 80000 | 4359014 | 3758848 | 640492 | 0 | 80015 | 0 | 80040 | 80040 | 59924 | 13 | 59998 | 240100 | 200 | 80000 | 80000 | 200 | 240000 | 160000 | 80040 | 80040 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 80000 | 0 | 21 | 0 | 0 | 80003 | 33 | 0 | 9 | 80001 | 1 | 21 | 0 | 0 | 0 | 5110 | 1 | 16 | 1 | 1 | 80037 | 80000 | 0 | 80000 | 80000 | 80100 | 80041 | 80041 | 80041 | 80041 | 80041 |
160204 | 80040 | 621 | 0 | 0 | 0 | 0 | 0 | 0 | 297 | 4 | 0 | 1957 | 0 | 80025 | 8 | 8 | 1 | 25 | 240242 | 80100 | 80161 | 80000 | 80216 | 80000 | 80000 | 4359014 | 3758848 | 645772 | 0 | 80015 | 0 | 80040 | 80163 | 59924 | 3 | 59998 | 240100 | 200 | 80000 | 80000 | 200 | 240000 | 160000 | 80040 | 80040 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 80000 | 0 | 21 | 0 | 0 | 80001 | 83 | 0 | 9 | 80001 | 1 | 21 | 0 | 0 | 0 | 5110 | 1 | 16 | 1 | 1 | 80037 | 80091 | 0 | 80000 | 80000 | 80100 | 80041 | 80041 | 80041 | 80041 | 80041 |
160204 | 80040 | 621 | 0 | 0 | 0 | 0 | 0 | 0 | 12 | 2 | 0 | 1951 | 0 | 80025 | 8 | 8 | 0 | 25 | 240262 | 80100 | 82295 | 80000 | 80100 | 80000 | 80000 | 4359014 | 3758848 | 647342 | 0 | 80015 | 0 | 80040 | 80040 | 59924 | 3 | 59998 | 240100 | 200 | 80000 | 80000 | 200 | 240357 | 160000 | 80040 | 80040 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 80000 | 0 | 21 | 0 | 0 | 80003 | 41 | 0 | 3 | 80001 | 1 | 21 | 0 | 0 | 0 | 5110 | 1 | 16 | 1 | 1 | 80037 | 80000 | 0 | 80000 | 80000 | 80100 | 80041 | 80041 | 80041 | 80041 | 80041 |
160204 | 80040 | 620 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0 | 1951 | 0 | 80025 | 8 | 8 | 0 | 25 | 243531 | 80100 | 82705 | 80000 | 80100 | 80000 | 80000 | 4359014 | 3758848 | 640426 | 1 | 80015 | 0 | 80040 | 80040 | 59924 | 3 | 59998 | 240100 | 200 | 80000 | 80000 | 200 | 240000 | 160000 | 80040 | 80040 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 80000 | 0 | 21 | 0 | 0 | 80001 | 1 | 0 | 6 | 80000 | 1 | 0 | 0 | 0 | 0 | 5110 | 1 | 16 | 1 | 1 | 80037 | 80000 | 0 | 80000 | 80000 | 80100 | 80041 | 80041 | 80041 | 80041 | 80161 |
160204 | 80040 | 621 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 4 | 0 | 4271 | 0 | 80025 | 8 | 8 | 0 | 25 | 242474 | 80100 | 84322 | 80000 | 80100 | 80000 | 80000 | 4359010 | 3758848 | 645759 | 0 | 80015 | 0 | 80040 | 80040 | 59924 | 3 | 59998 | 240100 | 200 | 80000 | 80000 | 200 | 240000 | 160000 | 80162 | 80040 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 80000 | 0 | 21 | 0 | 0 | 80001 | 23 | 0 | 3 | 80000 | 1 | 21 | 0 | 0 | 0 | 5127 | 1 | 16 | 1 | 1 | 80037 | 80093 | 0 | 80000 | 80000 | 80100 | 80041 | 80041 | 80041 | 80041 | 80041 |
160204 | 80040 | 621 | 0 | 0 | 0 | 0 | 0 | 0 | 12 | 92 | 0 | 2400 | 0 | 80025 | 8 | 8 | 3 | 25 | 242476 | 80100 | 85341 | 80000 | 80100 | 80000 | 80000 | 4359014 | 3758848 | 647184 | 0 | 80015 | 0 | 80040 | 80163 | 59924 | 3 | 59998 | 240100 | 200 | 80000 | 80000 | 200 | 240000 | 160000 | 80040 | 80040 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 80000 | 2 | 21 | 0 | 0 | 80001 | 0 | 0 | 9 | 80001 | 1 | 21 | 0 | 0 | 0 | 5110 | 3 | 16 | 1 | 2 | 80037 | 80000 | 0 | 80000 | 80000 | 80100 | 80041 | 80041 | 80041 | 80041 | 80041 |
160204 | 80040 | 620 | 0 | 0 | 0 | 0 | 1 | 2 | 9 | 4 | 0 | 2284 | 0 | 80025 | 8 | 8 | 31 | 25 | 240479 | 80100 | 81918 | 80000 | 80100 | 80000 | 80108 | 4359014 | 3758848 | 645766 | 1 | 80015 | 0 | 80040 | 80040 | 59924 | 3 | 59998 | 240100 | 200 | 80000 | 80000 | 200 | 240000 | 160256 | 80040 | 80040 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 80000 | 0 | 21 | 0 | 0 | 80003 | 37 | 0 | 3 | 80061 | 1 | 21 | 0 | 0 | 0 | 5110 | 1 | 16 | 1 | 1 | 80141 | 80000 | 0 | 80000 | 80000 | 80100 | 80041 | 80041 | 80041 | 80041 | 80041 |
160204 | 80040 | 621 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 5168 | 0 | 80025 | 0 | 8 | 3 | 25 | 241518 | 80100 | 86041 | 80000 | 80100 | 80000 | 80000 | 4359014 | 3763075 | 646943 | 0 | 80015 | 0 | 80040 | 80040 | 59924 | 3 | 59998 | 240100 | 200 | 80000 | 80000 | 200 | 240000 | 160000 | 80040 | 80040 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 80000 | 0 | 0 | 0 | 0 | 80001 | 45 | 0 | 7 | 80001 | 1 | 21 | 0 | 0 | 0 | 5110 | 1 | 16 | 1 | 1 | 80037 | 80000 | 0 | 80000 | 80000 | 80100 | 80041 | 80041 | 80041 | 80041 | 80284 |
Result (median cycles for code divided by count): 1.0005
retire uop (01) | cycle (02) | 03 | mmu table walk data (08) | 09 | 0f | 18 | 19 | 1e | 1f | 22 | 24 | 37 | 3f | 46 | 49 | 4f | 51 | schedule uop (52) | schedule int uop (53) | schedule simd uop (54) | schedule ldst uop (55) | dispatch int uop (56) | dispatch simd uop (57) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | ldst uops in schedulers (5b) | 5f | 60 | 61 | 69 | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | 79 | map int uop (7c) | map ldst uop (7d) | map simd uop (7e) | map int uop inputs (7f) | map ldst uop inputs (80) | map simd uop inputs (81) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | 91 | inst branch cond (94) | inst int alu (97) | inst simd store (99) | inst ldst (9b) | 9f | l1d tlb access (a0) | l1d tlb miss (a1) | l1d cache miss st (a2) | a4 | ld unit uop (a6) | st unit uop (a7) | l1d cache writeback (a8) | a9 | ac | af | atomic or exclusive succ (b3) | bc | l1d cache miss st nonspec (c0) | branch mispred nonspec (cb) | cf | d0 | d2 | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ? int output thing (e9) | ? ldst retires (ed) | ? simd retires (ee) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
160026 | 80040 | 620 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 4698 | 80025 | 8 | 8 | 0 | 25 | 244707 | 80010 | 81150 | 80000 | 80010 | 80000 | 80000 | 4358429 | 3758848 | 651266 | 0 | 0 | 0 | 80015 | 80040 | 80040 | 59946 | 3 | 60020 | 240010 | 0 | 20 | 80000 | 80000 | 20 | 240000 | 160000 | 80040 | 80040 | 1 | 1 | 80021 | 10 | 9 | 0 | 10 | 10 | 80000 | 80000 | 10 | 80000 | 0 | 21 | 0 | 0 | 80000 | 0 | 0 | 7 | 80000 | 0 | 1 | 21 | 0 | 5020 | 0 | 0 | 3 | 16 | 3 | 3 | 80037 | 80000 | 80000 | 80000 | 80010 | 80041 | 80041 | 80041 | 80041 | 80041 |
160024 | 80040 | 620 | 0 | 0 | 0 | 0 | 0 | 6 | 4 | 0 | 0 | 5637 | 80025 | 8 | 8 | 0 | 25 | 245647 | 80010 | 84694 | 80000 | 80010 | 80000 | 80000 | 4358429 | 3758848 | 654099 | 0 | 0 | 0 | 80015 | 80040 | 80040 | 59946 | 3 | 60020 | 240010 | 0 | 20 | 80000 | 80000 | 20 | 240000 | 160000 | 80040 | 80040 | 1 | 1 | 80021 | 10 | 9 | 0 | 10 | 10 | 80000 | 80000 | 10 | 80000 | 0 | 21 | 0 | 0 | 80001 | 1 | 0 | 0 | 80000 | 0 | 1 | 21 | 0 | 5020 | 0 | 0 | 3 | 16 | 4 | 6 | 80037 | 80000 | 80000 | 80000 | 80010 | 80041 | 80164 | 80284 | 80041 | 80041 |
160024 | 80040 | 622 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 5637 | 80025 | 8 | 8 | 3 | 25 | 244704 | 80010 | 81148 | 80000 | 80010 | 80000 | 80000 | 4358429 | 3758848 | 654085 | 0 | 0 | 0 | 80015 | 80040 | 80040 | 59946 | 3 | 60020 | 240010 | 0 | 20 | 80000 | 80000 | 20 | 240000 | 160000 | 80040 | 80040 | 1 | 1 | 80021 | 10 | 9 | 0 | 10 | 10 | 80000 | 80000 | 10 | 80000 | 0 | 21 | 0 | 0 | 80001 | 0 | 0 | 3 | 80001 | 0 | 1 | 21 | 0 | 5020 | 0 | 0 | 3 | 16 | 3 | 3 | 80037 | 80000 | 80000 | 80000 | 80010 | 80041 | 80041 | 80041 | 80041 | 80041 |
160024 | 80040 | 620 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 5633 | 80025 | 8 | 8 | 0 | 25 | 244703 | 80010 | 84694 | 80000 | 80010 | 80000 | 80000 | 4358429 | 3758848 | 654085 | 0 | 0 | 0 | 80015 | 80040 | 80040 | 59946 | 3 | 60020 | 240010 | 0 | 20 | 80000 | 80000 | 20 | 240000 | 160000 | 80040 | 80040 | 1 | 1 | 80021 | 10 | 9 | 0 | 10 | 10 | 80000 | 80000 | 10 | 80000 | 0 | 21 | 0 | 0 | 80001 | 0 | 0 | 3 | 80001 | 0 | 1 | 21 | 0 | 5020 | 0 | 0 | 3 | 16 | 3 | 3 | 80037 | 80000 | 80000 | 80000 | 80010 | 80041 | 80041 | 80041 | 80041 | 80041 |
160024 | 80040 | 621 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 5637 | 80025 | 8 | 8 | 0 | 25 | 244707 | 80010 | 80007 | 80000 | 80010 | 80000 | 80000 | 4358429 | 3758848 | 654085 | 0 | 0 | 0 | 80015 | 80040 | 80040 | 59946 | 3 | 60020 | 240010 | 0 | 20 | 80000 | 80000 | 20 | 240000 | 160000 | 80040 | 80040 | 1 | 1 | 80021 | 10 | 9 | 0 | 10 | 10 | 80000 | 80000 | 10 | 80000 | 0 | 21 | 0 | 0 | 80001 | 0 | 0 | 3 | 80001 | 0 | 0 | 21 | 0 | 5020 | 0 | 0 | 3 | 16 | 3 | 3 | 80037 | 80000 | 80000 | 80000 | 80010 | 80041 | 80041 | 80041 | 80041 | 80041 |
160024 | 80040 | 621 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 4694 | 80025 | 8 | 8 | 1 | 25 | 244704 | 80010 | 84694 | 80000 | 80010 | 80000 | 80000 | 4358429 | 3758848 | 654095 | 0 | 0 | 0 | 80015 | 80040 | 80040 | 59946 | 3 | 60020 | 240010 | 0 | 20 | 80000 | 80000 | 20 | 240000 | 160000 | 80040 | 80040 | 1 | 1 | 80021 | 10 | 9 | 0 | 10 | 10 | 80000 | 80000 | 10 | 80000 | 0 | 21 | 0 | 0 | 80001 | 0 | 0 | 0 | 80001 | 0 | 1 | 21 | 0 | 5020 | 0 | 0 | 3 | 16 | 3 | 3 | 80037 | 80000 | 80000 | 80000 | 80010 | 80041 | 80041 | 80041 | 80041 | 80041 |
160024 | 80040 | 620 | 0 | 0 | 0 | 0 | 0 | 6 | 2 | 0 | 0 | 5637 | 80025 | 8 | 8 | 0 | 25 | 244704 | 80010 | 81148 | 80000 | 80010 | 80000 | 80000 | 4358429 | 3758848 | 643444 | 0 | 0 | 0 | 80015 | 80040 | 80040 | 59946 | 3 | 60020 | 240010 | 0 | 20 | 80000 | 80000 | 20 | 240000 | 160000 | 80040 | 80040 | 1 | 1 | 80021 | 10 | 9 | 0 | 10 | 10 | 80000 | 80000 | 10 | 80000 | 0 | 22 | 0 | 0 | 80001 | 0 | 0 | 3 | 80002 | 0 | 1 | 21 | 0 | 5092 | 0 | 0 | 3 | 16 | 3 | 3 | 80037 | 80000 | 80000 | 80000 | 80010 | 80041 | 80041 | 80041 | 80041 | 80041 |
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