Apple Microarchitecture Research by Dougall Johnson M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions M1/A14 E-core (Icestorm): Overview | Base Instructions | SIMD and FP Instructions
Code:
st2 { v0.s, v1.s }[1], [x6], x8 nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop
mov x0, 0 mov x8, 0
(no loop instructions)
Retires (minus 60 nops): 2.000
Issues: 3.000
Integer unit issues: 1.000
Load/store unit issues: 1.000
SIMD/FP unit issues: 1.000
retire uop (01) | cycle (02) | 03 | mmu table walk instruction (07) | mmu table walk data (08) | 09 | l2 tlb miss instruction (0a) | l2 tlb miss data (0b) | 18 | 19 | 1e | 1f | 22 | 24 | 3a | 3f | 46 | 49 | 51 | schedule uop (52) | schedule int uop (53) | schedule simd uop (54) | schedule ldst uop (55) | dispatch int uop (56) | dispatch simd uop (57) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | ldst uops in schedulers (5b) | 5e | 5f | 60 | 61 | 69 | 6d | 6e | map rewind (75) | map stall (76) | dispatch uop (78) | map ldst uop (7d) | map simd uop (7e) | map ldst uop inputs (80) | map simd uop inputs (81) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst simd store (99) | inst ldst (9b) | l1d tlb access (a0) | l1d tlb miss (a1) | l1d cache miss st (a2) | ld unit uop (a6) | st unit uop (a7) | l1d cache writeback (a8) | a9 | ac | af | l1d cache miss st nonspec (c0) | c2 | c9 | cf | d0 | d2 | l1i cache miss demand (d3) | l1i tlb miss demand (d4) | d5 | map dispatch bubble (d6) | d9 | da | db | dd | fetch restart (de) | df | e0 | ? int output thing (e9) | ea | eb | ec | ? ldst retires (ed) | ? simd retires (ee) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
62006 | 29382 | 227 | 22 | 0 | 0 | 22 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4606 | 29081 | 0 | 0 | 18275 | 3000 | 1000 | 1000 | 1000 | 1000 | 1000 | 1000 | 5000 | 10917 | 8000 | 0 | 5 | 0 | 0 | 21737 | 28987 | 29393 | 3 | 10 | 3000 | 1000 | 1000 | 3000 | 2000 | 29365 | 29189 | 1 | 1 | 61001 | 1000 | 1000 | 1000 | 0 | 2 | 0 | 1000 | 0 | 0 | 0 | 1000 | 2 | 0 | 0 | 13388 | 9657 | 6893 | 3151 | 14 | 50 | 20689 | 3271 | 3815 | 12 | 49 | 48 | 2 | 28576 | 1000 | 16188 | 13236 | 14519 | 1000 | 1000 | 1000 | 29326 | 29363 | 29358 | 29273 | 29323 |
62004 | 29209 | 227 | 25 | 0 | 0 | 17 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 4669 | 29207 | 0 | 0 | 18364 | 3000 | 1000 | 1000 | 1000 | 1000 | 1000 | 1000 | 5000 | 10907 | 8000 | 0 | 3 | 0 | 8 | 21770 | 28968 | 29313 | 3 | 10 | 3000 | 1000 | 1000 | 3000 | 2000 | 29190 | 29250 | 1 | 1 | 61001 | 1000 | 1000 | 1000 | 0 | 2 | 0 | 1000 | 0 | 0 | 0 | 1000 | 2 | 0 | 0 | 13118 | 9413 | 6873 | 3190 | 8 | 43 | 20628 | 3180 | 3814 | 13 | 49 | 47 | 2 | 28595 | 1000 | 16112 | 13448 | 14268 | 1000 | 1000 | 1000 | 29357 | 29272 | 29333 | 29292 | 29379 |
62004 | 29455 | 227 | 24 | 0 | 0 | 20 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4524 | 29151 | 0 | 0 | 18246 | 3000 | 1000 | 1000 | 1000 | 1000 | 1000 | 1000 | 5000 | 10908 | 8000 | 0 | 17 | 0 | 0 | 21692 | 28925 | 29382 | 3 | 10 | 3000 | 1000 | 1000 | 3000 | 2000 | 29163 | 29206 | 1 | 1 | 61001 | 1000 | 1000 | 1000 | 0 | 0 | 0 | 1000 | 0 | 0 | 0 | 1000 | 0 | 0 | 0 | 13016 | 9301 | 6899 | 3111 | 14 | 49 | 20651 | 3256 | 3806 | 9 | 49 | 48 | 4 | 28602 | 1000 | 16258 | 13337 | 14419 | 1000 | 1000 | 1000 | 29381 | 29277 | 29181 | 29353 | 29426 |
62004 | 29388 | 229 | 22 | 1 | 0 | 18 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4533 | 29219 | 0 | 0 | 18289 | 3000 | 1000 | 1000 | 1000 | 1000 | 1000 | 1000 | 5000 | 10903 | 8000 | 0 | 2 | 0 | 0 | 21716 | 28963 | 29331 | 3 | 10 | 3000 | 1000 | 1000 | 3000 | 2000 | 29248 | 29190 | 1 | 1 | 61001 | 1000 | 1000 | 1000 | 0 | 0 | 0 | 1000 | 0 | 0 | 0 | 1000 | 2 | 0 | 0 | 13305 | 9311 | 6887 | 3096 | 14 | 49 | 20764 | 3167 | 3812 | 19 | 46 | 43 | 2 | 28506 | 1000 | 16210 | 13162 | 14249 | 1000 | 1000 | 1000 | 29233 | 29283 | 29163 | 29431 | 29263 |
62004 | 29202 | 228 | 18 | 0 | 0 | 25 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 4591 | 29067 | 0 | 0 | 18276 | 3000 | 1000 | 1000 | 1000 | 1000 | 1000 | 1000 | 5000 | 10902 | 8000 | 0 | 8 | 0 | 0 | 21722 | 29084 | 29274 | 3 | 10 | 3000 | 1000 | 1000 | 3000 | 2000 | 29210 | 29242 | 1 | 1 | 61001 | 1000 | 1000 | 1004 | 0 | 2 | 0 | 1000 | 0 | 0 | 0 | 1000 | 2 | 0 | 0 | 13045 | 9146 | 6947 | 3206 | 12 | 43 | 20743 | 3245 | 3809 | 12 | 51 | 50 | 2 | 28546 | 1000 | 16076 | 13028 | 14149 | 1000 | 1000 | 1000 | 29296 | 29437 | 29319 | 29335 | 29477 |
62004 | 29499 | 227 | 15 | 0 | 0 | 21 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4624 | 29111 | 0 | 0 | 18264 | 3000 | 1000 | 1000 | 1000 | 1000 | 1000 | 1000 | 5000 | 10908 | 8000 | 0 | 9 | 0 | 0 | 21756 | 29012 | 29362 | 3 | 10 | 3000 | 1000 | 1000 | 3000 | 2000 | 29253 | 29243 | 1 | 1 | 61001 | 1000 | 1000 | 1000 | 0 | 2 | 0 | 1000 | 0 | 0 | 0 | 1000 | 2 | 0 | 0 | 13040 | 9377 | 6893 | 3153 | 17 | 48 | 20677 | 3210 | 3807 | 13 | 47 | 48 | 2 | 28582 | 1000 | 16169 | 13073 | 14408 | 1000 | 1000 | 1000 | 29288 | 29366 | 29334 | 29554 | 29306 |
62004 | 29343 | 227 | 18 | 0 | 0 | 17 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 4670 | 29159 | 0 | 0 | 18403 | 3000 | 1000 | 1000 | 1000 | 1000 | 1000 | 1000 | 5000 | 10892 | 8000 | 0 | 9 | 0 | 0 | 21736 | 28912 | 29427 | 3 | 10 | 3000 | 1000 | 1000 | 3000 | 2000 | 29312 | 29262 | 1 | 1 | 61001 | 1000 | 1000 | 1000 | 0 | 3 | 0 | 1000 | 0 | 0 | 0 | 1000 | 2 | 0 | 0 | 13117 | 9399 | 6990 | 3186 | 8 | 49 | 20743 | 3248 | 3808 | 11 | 51 | 45 | 2 | 28497 | 1000 | 16366 | 13201 | 14150 | 1000 | 1000 | 1000 | 29227 | 29348 | 29310 | 29334 | 29136 |
62004 | 29307 | 227 | 24 | 0 | 0 | 19 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4543 | 29017 | 0 | 0 | 18371 | 3000 | 1000 | 1000 | 1000 | 1000 | 1000 | 1000 | 5000 | 10908 | 8000 | 0 | 3 | 0 | 0 | 21718 | 29014 | 29246 | 3 | 10 | 3000 | 1000 | 1000 | 3000 | 2000 | 29216 | 29221 | 1 | 1 | 61001 | 1000 | 1000 | 1000 | 0 | 2 | 0 | 1000 | 1 | 0 | 0 | 1000 | 2 | 0 | 0 | 13053 | 9415 | 6863 | 3180 | 12 | 41 | 20708 | 3219 | 3814 | 10 | 49 | 46 | 2 | 28604 | 1000 | 16116 | 13034 | 14304 | 1000 | 1000 | 1000 | 29479 | 29356 | 29374 | 29413 | 29265 |
62004 | 29263 | 227 | 17 | 0 | 0 | 22 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 4668 | 29096 | 0 | 0 | 18246 | 3000 | 1000 | 1000 | 1000 | 1000 | 1000 | 1000 | 5000 | 10900 | 8000 | 0 | 2 | 0 | 0 | 21731 | 28668 | 29294 | 3 | 10 | 3000 | 1000 | 1000 | 3000 | 2000 | 29280 | 29254 | 1 | 1 | 61001 | 1000 | 1000 | 1000 | 0 | 2 | 0 | 1000 | 0 | 0 | 0 | 1000 | 2 | 0 | 0 | 13025 | 9456 | 6867 | 3111 | 12 | 46 | 20599 | 3159 | 3814 | 7 | 47 | 51 | 2 | 28489 | 1000 | 16142 | 13296 | 14461 | 1000 | 1000 | 1000 | 29314 | 29289 | 29125 | 29158 | 29212 |
62004 | 29480 | 227 | 18 | 0 | 0 | 21 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 4581 | 29037 | 0 | 0 | 18405 | 3000 | 1000 | 1000 | 1000 | 1000 | 1000 | 1000 | 5000 | 10909 | 8000 | 0 | 3 | 0 | 0 | 21681 | 28984 | 29332 | 3 | 10 | 3000 | 1000 | 1000 | 3000 | 2000 | 29156 | 29260 | 1 | 1 | 61001 | 1000 | 1000 | 1000 | 0 | 2 | 0 | 1000 | 0 | 0 | 3 | 1000 | 2 | 0 | 0 | 12963 | 9288 | 6888 | 3087 | 11 | 47 | 20732 | 3111 | 3812 | 10 | 43 | 46 | 2 | 28506 | 1000 | 16172 | 13419 | 14430 | 1000 | 1000 | 1000 | 29410 | 29349 | 29288 | 29306 | 29313 |
Count: 8
Code:
st2 { v0.s, v1.s }[1], [x6], x8 st2 { v0.s, v1.s }[1], [x6], x8 st2 { v0.s, v1.s }[1], [x6], x8 st2 { v0.s, v1.s }[1], [x6], x8 st2 { v0.s, v1.s }[1], [x6], x8 st2 { v0.s, v1.s }[1], [x6], x8 st2 { v0.s, v1.s }[1], [x6], x8 st2 { v0.s, v1.s }[1], [x6], x8
mov x7, x6 mov x8, x6 mov x9, x6 mov x10, x6 mov x11, x6 mov x12, x6 mov x13, x6 mov x8, 0
(fused SUBS/B.cc loop)
Result (median cycles for code divided by count): 1.0005
retire uop (01) | cycle (02) | 03 | l1d tlb fill (05) | mmu table walk data (08) | 09 | l2 tlb miss data (0b) | 18 | 19 | 1e | 1f | 37 | 3a | 3f | 46 | 49 | 4f | 51 | schedule uop (52) | schedule int uop (53) | schedule simd uop (54) | schedule ldst uop (55) | dispatch int uop (56) | dispatch simd uop (57) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | ldst uops in schedulers (5b) | 60 | 69 | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map simd uop (7e) | map int uop inputs (7f) | map ldst uop inputs (80) | map simd uop inputs (81) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int alu (97) | inst simd store (99) | inst ldst (9b) | 9f | l1d tlb access (a0) | l1d tlb miss (a1) | l1d cache miss st (a2) | a4 | ld unit uop (a6) | st unit uop (a7) | l1d cache writeback (a8) | a9 | ac | af | bc | l1d cache miss st nonspec (c0) | l1d tlb miss nonspec (c1) | c2 | branch cond mispred nonspec (c5) | cf | d5 | map dispatch bubble (d6) | d9 | dd | fetch restart (de) | e0 | ? int output thing (e9) | ? ldst retires (ed) | ? simd retires (ee) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
160206 | 80040 | 620 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 9 | 4233 | 0 | 80025 | 0 | 0 | 1 | 25 | 245451 | 80100 | 84341 | 80000 | 80216 | 80000 | 80108 | 4358990 | 3775084 | 646537 | 0 | 80015 | 80040 | 80040 | 59924 | 3 | 60082 | 240108 | 200 | 80000 | 80000 | 200 | 240000 | 160000 | 80040 | 80040 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 80007 | 7 | 17 | 0 | 0 | 80008 | 1 | 0 | 14 | 80000 | 1 | 17 | 0 | 0 | 0 | 5110 | 1 | 16 | 3 | 1 | 1 | 80037 | 80000 | 80000 | 80000 | 80100 | 80041 | 80041 | 80041 | 80041 | 80041 |
160204 | 80040 | 652 | 1 | 0 | 0 | 0 | 0 | 0 | 21 | 12 | 183 | 1 | 80025 | 11 | 11 | 2 | 25 | 240239 | 80100 | 81767 | 80000 | 80100 | 80464 | 82808 | 4358994 | 3758848 | 640429 | 0 | 80015 | 80040 | 80040 | 59924 | 6 | 59998 | 240100 | 200 | 80000 | 80000 | 200 | 240000 | 160000 | 80040 | 80040 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 80007 | 7 | 0 | 0 | 1 | 80008 | 1 | 1 | 2205 | 80000 | 8 | 25 | 7 | 1 | 0 | 5110 | 1 | 34 | 0 | 1 | 1 | 80037 | 80000 | 80000 | 80000 | 80100 | 80041 | 80041 | 80041 | 80041 | 80041 |
160204 | 80040 | 652 | 1 | 1 | 0 | 0 | 1 | 1 | 12 | 9 | 1035 | 0 | 80146 | 8 | 8 | 1 | 25 | 240190 | 80284 | 80851 | 80000 | 80100 | 80000 | 80000 | 4359014 | 3758848 | 643100 | 0 | 80015 | 80162 | 80040 | 59924 | 3 | 59998 | 240440 | 200 | 80000 | 80000 | 200 | 240000 | 160000 | 80165 | 80040 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 80000 | 0 | 17 | 27 | 0 | 80001 | 1 | 0 | 5 | 80061 | 1 | 0 | 0 | 0 | 0 | 5110 | 2 | 16 | 1 | 1 | 1 | 80037 | 80000 | 80000 | 80000 | 80100 | 80041 | 80041 | 80041 | 80041 | 80041 |
160204 | 80040 | 647 | 0 | 0 | 0 | 0 | 0 | 1 | 12 | 3 | 3612 | 0 | 80025 | 8 | 11 | 3 | 25 | 241135 | 80191 | 83439 | 80000 | 80100 | 80000 | 80000 | 4359014 | 3758848 | 640258 | 0 | 80015 | 80040 | 80040 | 59924 | 3 | 59998 | 240100 | 200 | 80000 | 80000 | 200 | 240000 | 160000 | 80040 | 80040 | 2 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 80060 | 0 | 17 | 0 | 0 | 80001 | 1 | 0 | 1105 | 80001 | 1 | 17 | 0 | 0 | 0 | 5110 | 1 | 16 | 1 | 1 | 1 | 80037 | 80000 | 80000 | 80000 | 80100 | 80041 | 80041 | 80041 | 80161 | 80041 |
160204 | 80040 | 652 | 0 | 0 | 0 | 0 | 0 | 0 | 12 | 91 | 850 | 0 | 80025 | 8 | 8 | 1 | 25 | 240997 | 80100 | 80233 | 80000 | 80100 | 80000 | 80000 | 4359014 | 3758848 | 642551 | 0 | 80117 | 80040 | 80040 | 59987 | 3 | 59998 | 240100 | 200 | 80000 | 80000 | 200 | 240000 | 160000 | 80040 | 80040 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 80000 | 0 | 17 | 0 | 0 | 80000 | 1 | 0 | 5 | 80001 | 1 | 0 | 0 | 0 | 0 | 5110 | 1 | 16 | 1 | 1 | 1 | 80142 | 80000 | 80000 | 80000 | 80100 | 80041 | 80041 | 80041 | 80041 | 83577 |
160204 | 80040 | 638 | 0 | 0 | 0 | 0 | 0 | 0 | 12 | 3 | 1035 | 0 | 80025 | 8 | 8 | 1 | 25 | 241260 | 80100 | 81160 | 80060 | 80216 | 80000 | 80000 | 4361386 | 3758848 | 652738 | 0 | 80015 | 80040 | 80040 | 59924 | 13 | 59998 | 240100 | 200 | 80000 | 80000 | 200 | 240360 | 160000 | 80040 | 80040 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 80000 | 0 | 17 | 0 | 2 | 80001 | 1 | 0 | 7 | 80061 | 1 | 17 | 0 | 0 | 0 | 5110 | 1 | 16 | 0 | 1 | 1 | 80037 | 80000 | 80000 | 80000 | 80100 | 80041 | 80041 | 80041 | 80164 | 80041 |
160204 | 80040 | 647 | 0 | 0 | 0 | 0 | 0 | 0 | 153 | 3 | 4242 | 0 | 80148 | 0 | 11 | 1 | 25 | 240232 | 80100 | 82084 | 80000 | 80216 | 80000 | 80000 | 4359014 | 3762988 | 655316 | 1 | 80015 | 80040 | 80040 | 59988 | 3 | 60080 | 240100 | 200 | 80000 | 80000 | 200 | 240000 | 160480 | 80040 | 80040 | 2 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 80120 | 0 | 17 | 30 | 0 | 80061 | 1 | 0 | 4 | 80001 | 1 | 18 | 0 | 0 | 0 | 5128 | 2 | 16 | 1 | 1 | 1 | 80037 | 80000 | 80000 | 80000 | 80100 | 80041 | 80041 | 80041 | 80041 | 80285 |
160204 | 80040 | 652 | 0 | 0 | 0 | 0 | 1 | 0 | 135 | 3 | 82 | 0 | 80025 | 8 | 8 | 0 | 25 | 242514 | 80100 | 81035 | 80060 | 80216 | 80000 | 80000 | 4359014 | 3758848 | 643483 | 0 | 80015 | 80040 | 80161 | 59924 | 13 | 59998 | 240100 | 200 | 80000 | 80000 | 200 | 240000 | 160238 | 80040 | 80040 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 80000 | 0 | 17 | 0 | 0 | 80001 | 0 | 0 | 1099 | 80062 | 1 | 17 | 0 | 0 | 0 | 5110 | 1 | 16 | 1 | 1 | 1 | 80037 | 80000 | 80000 | 80000 | 80100 | 80041 | 80041 | 80041 | 80041 | 80041 |
160204 | 80040 | 642 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 850 | 0 | 80025 | 8 | 0 | 1 | 25 | 241260 | 80100 | 80664 | 80000 | 80100 | 80000 | 80000 | 4359014 | 3758848 | 640345 | 0 | 80015 | 80040 | 80040 | 59924 | 3 | 59998 | 240100 | 200 | 80000 | 80000 | 200 | 240000 | 160000 | 80040 | 80040 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 80000 | 0 | 17 | 0 | 0 | 80001 | 1 | 0 | 2 | 80000 | 1 | 17 | 0 | 0 | 0 | 5110 | 1 | 16 | 1 | 1 | 1 | 80037 | 80000 | 80000 | 80000 | 80100 | 80041 | 80041 | 80041 | 80041 | 80041 |
160204 | 80040 | 643 | 0 | 0 | 0 | 0 | 0 | 0 | 36 | 3 | 874 | 0 | 80025 | 8 | 8 | 0 | 25 | 241135 | 80100 | 80803 | 80000 | 80100 | 80000 | 80000 | 4359014 | 3758848 | 644412 | 0 | 80015 | 80040 | 80040 | 59924 | 3 | 59998 | 240100 | 200 | 80000 | 80000 | 200 | 240000 | 160000 | 80040 | 80040 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 80000 | 0 | 17 | 0 | 0 | 80001 | 2 | 0 | 5 | 80001 | 1 | 17 | 0 | 0 | 0 | 5110 | 1 | 16 | 1 | 1 | 1 | 80037 | 80000 | 80000 | 80000 | 80100 | 80041 | 80041 | 80041 | 80041 | 80041 |
Result (median cycles for code divided by count): 1.0005
retire uop (01) | cycle (02) | 03 | l1d tlb fill (05) | mmu table walk data (08) | l2 tlb miss instruction (0a) | l2 tlb miss data (0b) | 18 | 19 | 1e | 1f | 22 | 24 | 37 | 3a | 3f | 46 | 49 | 4f | 51 | schedule uop (52) | schedule int uop (53) | schedule simd uop (54) | schedule ldst uop (55) | dispatch int uop (56) | dispatch simd uop (57) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | ldst uops in schedulers (5b) | 60 | 69 | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map simd uop (7e) | map int uop inputs (7f) | map ldst uop inputs (80) | map simd uop inputs (81) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int alu (97) | inst simd store (99) | inst ldst (9b) | 9f | l1d tlb access (a0) | l1d tlb miss (a1) | l1d cache miss st (a2) | a4 | ld unit uop (a6) | st unit uop (a7) | l1d cache writeback (a8) | a9 | ac | af | bc | l1d cache miss st nonspec (c0) | l1d tlb miss nonspec (c1) | c2 | branch cond mispred nonspec (c5) | branch mispred nonspec (cb) | cf | d2 | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ? int output thing (e9) | ? ldst retires (ed) | ? simd retires (ee) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
160026 | 80040 | 620 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 12 | 0 | 0 | 1148 | 1 | 80025 | 0 | 11 | 0 | 25 | 241163 | 80010 | 81113 | 80000 | 80010 | 80000 | 80000 | 4358409 | 3758848 | 643438 | 0 | 80015 | 80040 | 80040 | 59946 | 3 | 60020 | 240010 | 20 | 80000 | 80000 | 20 | 240000 | 160000 | 80040 | 80040 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 80007 | 7 | 26 | 0 | 0 | 80008 | 0 | 0 | 8 | 80001 | 8 | 25 | 7 | 0 | 0 | 0 | 5020 | 0 | 7 | 16 | 4 | 5 | 80037 | 80000 | 80000 | 80000 | 80010 | 80041 | 80041 | 80041 | 80041 | 80041 |
160024 | 80161 | 621 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 12 | 1 | 0 | 1482 | 1 | 80025 | 11 | 0 | 1 | 25 | 241157 | 80010 | 80021 | 80000 | 80010 | 80000 | 80000 | 4358409 | 3758848 | 643438 | 0 | 80015 | 80040 | 80040 | 59946 | 3 | 60020 | 240010 | 20 | 80000 | 80120 | 20 | 240000 | 160000 | 80040 | 80040 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 80007 | 7 | 25 | 0 | 0 | 80008 | 1 | 1 | 7 | 80001 | 8 | 0 | 7 | 1 | 0 | 0 | 5020 | 0 | 4 | 16 | 5 | 5 | 80143 | 80000 | 80000 | 80000 | 80010 | 80041 | 80041 | 80041 | 80162 | 80041 |
160024 | 80040 | 622 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 12 | 1 | 0 | 1153 | 1 | 80025 | 0 | 0 | 1 | 25 | 244705 | 80010 | 81147 | 80000 | 80010 | 80000 | 80000 | 4360922 | 3758848 | 648471 | 0 | 80015 | 80040 | 80040 | 59946 | 3 | 60020 | 240010 | 20 | 80000 | 80000 | 20 | 240000 | 160000 | 80040 | 80040 | 2 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 80007 | 9 | 25 | 0 | 1 | 80008 | 1 | 0 | 11 | 80001 | 8 | 25 | 7 | 0 | 0 | 0 | 5020 | 0 | 5 | 16 | 5 | 5 | 80037 | 80000 | 80000 | 80000 | 80010 | 80041 | 80041 | 80041 | 80041 | 80041 |
160024 | 80040 | 620 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 12 | 0 | 0 | 1658 | 1 | 80025 | 11 | 9 | 2 | 25 | 241156 | 80010 | 84695 | 80000 | 80010 | 80000 | 80000 | 4358405 | 3758848 | 643444 | 1 | 80015 | 80040 | 80040 | 59946 | 3 | 60020 | 240010 | 20 | 80000 | 80000 | 20 | 240000 | 160000 | 80040 | 80040 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 80007 | 7 | 25 | 0 | 1 | 80008 | 0 | 1 | 8 | 80001 | 8 | 25 | 7 | 1 | 0 | 0 | 5020 | 0 | 4 | 16 | 6 | 5 | 80037 | 80000 | 80000 | 80000 | 80010 | 80041 | 80041 | 80041 | 80041 | 80041 |
160024 | 80040 | 621 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 7 | 0 | 0 | 1378 | 1 | 80025 | 11 | 11 | 2 | 25 | 241158 | 80010 | 81148 | 80000 | 80010 | 80000 | 80000 | 4358409 | 3758848 | 643441 | 0 | 80015 | 80040 | 80040 | 59946 | 3 | 60020 | 240010 | 20 | 80000 | 80000 | 20 | 240000 | 160000 | 80040 | 80040 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 80007 | 7 | 0 | 0 | 1 | 80008 | 1 | 0 | 11 | 80000 | 8 | 25 | 7 | 0 | 0 | 0 | 5020 | 0 | 6 | 16 | 5 | 6 | 80037 | 80000 | 80000 | 80000 | 80010 | 80041 | 80041 | 80041 | 80041 | 80041 |
160024 | 80040 | 621 | 1 | 0 | 0 | 0 | 0 | 0 | 12 | 12 | 0 | 0 | 1471 | 1 | 80025 | 11 | 11 | 2 | 25 | 241163 | 80010 | 84742 | 80000 | 80010 | 80000 | 80000 | 4358405 | 3758848 | 640076 | 0 | 80015 | 80040 | 80040 | 59946 | 3 | 60020 | 240010 | 20 | 80000 | 80000 | 20 | 240000 | 160000 | 80040 | 80040 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 80008 | 7 | 0 | 0 | 0 | 80008 | 1 | 0 | 8 | 80001 | 8 | 25 | 7 | 0 | 0 | 0 | 5020 | 0 | 6 | 16 | 7 | 6 | 80037 | 80000 | 80000 | 80000 | 80010 | 80041 | 80041 | 80041 | 80041 | 80041 |
160024 | 80040 | 620 | 1 | 0 | 0 | 0 | 0 | 0 | 12 | 7 | 0 | 0 | 1780 | 1 | 80025 | 11 | 11 | 2 | 25 | 240032 | 80010 | 81146 | 80000 | 80010 | 80000 | 80000 | 4358405 | 3758848 | 643438 | 0 | 80015 | 80040 | 80040 | 59946 | 3 | 60020 | 240010 | 20 | 80000 | 80000 | 20 | 240000 | 160000 | 80040 | 80040 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 80008 | 7 | 26 | 0 | 0 | 80007 | 0 | 1 | 11 | 80001 | 7 | 0 | 7 | 1 | 0 | 0 | 5020 | 0 | 4 | 16 | 4 | 5 | 80037 | 80000 | 80000 | 80000 | 80010 | 80041 | 80041 | 80041 | 80041 | 80041 |
160024 | 80040 | 620 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 12 | 0 | 0 | 2566 | 1 | 80025 | 0 | 0 | 2 | 25 | 240932 | 80010 | 81147 | 80000 | 80010 | 80000 | 80000 | 4358397 | 3758848 | 642070 | 0 | 80015 | 80040 | 80040 | 59946 | 3 | 60020 | 240010 | 20 | 80000 | 80000 | 20 | 240000 | 160000 | 80040 | 80040 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 80007 | 7 | 25 | 0 | 0 | 80008 | 1 | 0 | 8 | 80001 | 8 | 25 | 7 | 0 | 0 | 0 | 5020 | 0 | 5 | 16 | 4 | 4 | 80037 | 80000 | 80000 | 80000 | 80010 | 80041 | 80041 | 80041 | 80041 | 80041 |
160024 | 80040 | 621 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 1167 | 1 | 80025 | 11 | 11 | 2 | 25 | 241113 | 80010 | 80012 | 80000 | 80010 | 80000 | 80000 | 4358409 | 3758848 | 644998 | 0 | 80015 | 80040 | 80040 | 59946 | 3 | 60020 | 240010 | 20 | 80000 | 80000 | 20 | 240000 | 160000 | 80040 | 80040 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 80008 | 7 | 25 | 0 | 1 | 80008 | 0 | 0 | 8 | 80001 | 8 | 25 | 7 | 0 | 0 | 0 | 5020 | 0 | 3 | 16 | 4 | 6 | 80037 | 80000 | 80000 | 80000 | 80010 | 80041 | 80041 | 80041 | 80041 | 80041 |
160024 | 80040 | 620 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 9 | 0 | 0 | 3197 | 1 | 80025 | 10 | 9 | 6 | 25 | 240019 | 80010 | 81471 | 80000 | 80010 | 80000 | 80000 | 4358405 | 3758848 | 643444 | 0 | 80015 | 80040 | 80040 | 59946 | 17 | 60020 | 240010 | 20 | 80000 | 80000 | 20 | 240000 | 160000 | 80040 | 80040 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 80009 | 8 | 25 | 0 | 0 | 80008 | 0 | 0 | 14 | 80001 | 8 | 25 | 7 | 0 | 0 | 0 | 5020 | 0 | 7 | 16 | 5 | 5 | 80037 | 80000 | 80000 | 80000 | 80010 | 80041 | 80041 | 80041 | 80041 | 80041 |