Firestorm: ST3 (multiple, 16B) measurements

Code:

  st3 { v0.16b, v1.16b, v2.16b }, [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 6.000

Issues: 6.000

Integer unit issues: 0.000

Load/store unit issues: 3.000

SIMD/FP unit issues: 3.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	1f	22	24	37	3a	3f	46	49	51	schedule uop (52)	schedule simd uop (54)	schedule ldst uop (55)	dispatch simd uop (57)	dispatch ldst uop (58)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	5f	60	61	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd store (99)	inst ldst (9b)	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	c9	cf	d0	d2	l1i cache miss demand (d3)	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	f5	f6	f7	f8	fd
66008	30432	245	0	27	2	25	2	28	26	2955	1148	0	0	0	4403	29805	0	0	17395	6000	3000	3000	3000	3000	33041	24000	2	0	0	22847	29230	29693	3	144	6030	3000	3000	6000	9000	29472	29456	1	1	61001	1000	1000	3000	0	3	0	3000	2	2	4030	3012	0	3	0	2	0	13146	9518	6921	3101	13	56	20280	3215	3819	36	63	60	29794	17494	13738	15241	3000	3000	29505	29569	29523	29540	30110
66004	29988	241	0	17	0	25	0	19	17	141	1	0	0	0	4658	29705	0	0	17453	6000	3000	3000	3000	3000	33004	24024	1	0	0	22805	29252	29655	3	10	6000	3000	3000	6000	9000	29549	29582	1	1	61001	1000	1000	3002	0	3	0	3000	0	0	0	3000	0	3	0	0	0	13440	9441	6928	3141	16	58	20526	3346	3820	30	61	58	28832	16481	13009	14960	3000	3000	29653	29684	29521	29552	29742
66004	29686	238	0	24	0	18	0	0	0	0	89	0	0	0	4618	29802	0	0	15909	6000	3000	3000	3000	3000	33041	24000	1	0	0	22762	29329	29910	3	10	6000	3000	3000	6000	9000	29415	29462	1	1	61001	1000	1000	3000	0	3	0	3000	0	0	0	3000	0	0	0	0	0	13166	9552	6869	3154	12	54	20353	3256	3819	32	57	62	28763	16135	12707	14958	3000	3000	29544	29552	29463	29561	29602
66004	29558	228	0	27	0	19	0	0	1	0	1	0	0	0	4602	29437	0	0	17376	6000	3000	3000	3000	3000	33054	24000	1	0	0	22750	29277	29583	3	30	6000	3000	3000	6000	9000	29552	29446	1	1	61001	1000	1000	3000	0	0	0	3000	0	0	3	3000	0	3	0	0	0	13173	9433	6903	3163	10	53	20636	3328	3815	24	59	58	29036	16348	13322	14635	3000	3000	29712	29564	29773	29633	29725
66004	29634	238	0	22	0	24	0	0	0	0	88	0	0	0	4593	28784	0	0	16753	6000	3000	3000	3000	3000	33019	24000	3	0	0	22754	28636	28978	8	10	6000	3000	3000	6000	9000	28946	28837	1	1	61001	1000	1000	3000	0	3	0	3000	0	0	0	3003	0	3	0	0	0	13183	9500	6864	3163	12	63	19747	3233	3821	33	61	51	28257	16091	12428	14274	3000	3000	28912	28947	28834	28959	28971
66004	28895	224	0	28	0	20	0	0	1	0	1	0	0	0	4586	28783	0	0	16757	6006	3000	3000	3000	3000	33061	24024	2	0	0	22784	28632	28982	3	10	6000	3000	3000	6000	9000	28862	28896	1	1	61001	1000	1000	3000	0	3	2	3000	0	0	0	3000	0	3	0	0	0	13237	9585	6919	3106	13	58	19648	3167	3818	32	53	56	28365	15523	12398	14037	3000	3000	28953	28793	28938	28863	28895
66004	28923	225	0	27	0	23	0	0	0	0	89	0	0	0	4676	28862	0	0	16851	6000	3000	3000	3000	3000	33052	24000	4	0	0	22728	28696	28777	3	10	6000	3000	3000	6000	9000	28867	28887	2	1	61001	1000	1000	3002	0	0	0	3000	0	4	0	3000	0	0	0	0	0	13142	9404	6953	3169	14	64	19796	3208	3821	42	56	58	28333	15825	12544	14308	3000	3000	29049	28875	28982	28864	28965
66004	28920	224	0	27	0	24	0	1	0	0	1	0	0	0	4738	28793	0	0	16798	6000	3000	3000	3000	3003	33076	24000	4	0	0	22750	28641	28989	3	10	6000	3000	3000	6000	9000	28849	28923	1	1	61001	1000	1000	3000	0	3	0	3000	0	0	0	3000	0	3	0	0	0	13122	9253	6929	3153	11	59	19688	3167	3818	35	55	66	28510	15798	12477	14470	3000	3000	28987	28961	28934	28999	28850
66004	28977	224	0	29	0	21	0	1	0	6	1	0	0	0	4680	28988	0	0	16876	6000	3000	3000	3000	3000	33058	24000	4	0	0	22757	28922	29202	3	10	6000	3000	3000	6000	9000	29171	29103	1	1	61001	1000	1000	3000	0	3	0	3000	0	0	0	3000	0	3	0	0	0	13486	9912	6985	3135	10	59	19547	3144	3820	33	63	63	28486	15539	12224	14401	3000	3000	28937	29049	28974	29008	28615
66004	28649	223	0	22	0	20	0	0	0	0	1	0	0	0	4928	28711	0	0	16777	6000	3000	3000	3000	3000	33053	24000	3	0	0	22788	28661	28890	3	10	6000	3000	3000	6000	9000	28746	28706	1	1	61001	1000	1000	3000	0	3	0	3000	0	0	0	3000	0	3	0	0	0	13340	9642	6915	3081	14	58	19589	3225	3824	22	59	59	28304	15400	12293	13791	3000	3000	28771	28736	28836	28689	28685

Count: 8

Code:

  st3 { v0.16b, v1.16b, v2.16b }, [x6]
  st3 { v0.16b, v1.16b, v2.16b }, [x6]
  st3 { v0.16b, v1.16b, v2.16b }, [x6]
  st3 { v0.16b, v1.16b, v2.16b }, [x6]
  st3 { v0.16b, v1.16b, v2.16b }, [x6]
  st3 { v0.16b, v1.16b, v2.16b }, [x6]
  st3 { v0.16b, v1.16b, v2.16b }, [x6]
  st3 { v0.16b, v1.16b, v2.16b }, [x6]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.5005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	18	19	1e	1f	22	24	37	3a	3f	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd store (99)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	cd	ce	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	da	db	dd	fetch restart (de)	e0	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
480208	120047	964	0	0	0	0	0	3	0	0	5413	0	120028	16	16	0	25	485821	100	245220	240000	100	240000	240000	500	5519663	1943633	120021	120043	120049	39984	3	40025	480100	200	240000	240000	200	480000	720000	120042	120042	1	1	80201	100	99	100	100	80000	80000	100	240000	0	34	0	0	240002	0	0	2	240002	2	0	0	0	0	0	5109	0	0	0	8	17	0	0	8	8	120046	240000	240000	100	120049	120133	120043	120051	120050
480204	120048	964	0	0	0	0	0	6	0	0	7856	0	120028	16	16	1	25	489292	100	245039	240000	100	240000	240000	500	5519567	1944045	120021	120042	120043	39987	3	40024	480100	200	240000	240000	200	480000	720000	120043	120042	1	1	80201	100	99	100	100	80000	80000	100	240000	0	34	0	0	240000	0	0	2	240002	0	34	0	0	0	0	5110	0	0	0	8	17	0	0	7	7	120039	240000	240000	100	120043	120043	120058	120052	120044
480204	120042	964	0	0	0	0	0	0	0	0	4303	0	120027	16	0	0	25	487956	100	245705	240000	100	240000	240000	500	5519687	1959716	120033	120043	120043	39984	3	40024	480100	200	240000	240000	200	480000	720000	120042	120052	1	1	80201	100	99	100	100	80000	80000	100	240000	0	38	0	0	240002	1	0	2	240000	2	0	0	0	1	0	5110	0	0	0	8	17	0	0	8	11	120040	240000	240000	100	120043	120049	120059	120051	120050
480204	120042	965	0	0	0	0	0	3	0	0	6085	0	120034	16	16	0	25	486439	100	246912	240000	100	240000	240000	500	5519567	1948167	120021	120042	120049	39986	3	40025	480100	200	240000	240000	200	480000	720000	120043	120042	1	1	80201	100	99	100	100	80000	80000	100	240000	0	38	0	0	240002	0	0	2	240002	2	40	0	0	0	0	5110	0	0	0	7	17	0	0	8	8	120040	240000	240000	100	120043	120043	120051	120050	120049
480204	120049	964	0	0	0	0	0	0	0	0	2899	0	120027	16	16	0	25	486769	100	244340	240000	100	240000	240000	500	5519663	1966989	120024	120042	144857	39984	3	40025	480100	200	240000	240000	200	480000	720000	120043	120048	1	1	80201	100	99	100	100	80000	80000	100	240000	0	34	0	0	240002	0	0	8	240002	2	34	0	0	0	0	5110	0	0	0	8	17	0	0	7	8	120040	240000	240000	100	120043	120050	120060	120051	120050
480204	120042	964	0	0	0	0	12	3	0	0	10924	0	120027	16	0	0	25	487242	100	246669	240000	100	240000	240000	500	5519567	1933986	120021	120048	120043	39984	3	40024	480100	200	240000	240000	200	480000	720000	120049	120042	1	1	80201	100	99	100	100	80000	80000	100	240000	0	34	0	0	240002	0	0	2	240002	2	34	0	0	0	0	5110	0	0	0	8	17	0	0	4	8	120039	240000	240000	100	120044	120043	120057	120656	120043
480204	120043	964	0	0	0	0	0	0	0	0	8542	0	120037	16	16	0	25	485341	100	245360	240000	100	240000	240000	500	5519567	1927222	120021	120048	120042	39984	3	40025	480100	200	240000	240000	200	480000	720000	120049	120042	1	1	80201	100	99	100	100	80000	80000	100	240122	0	34	410	1	240122	0	0	1732	240182	2	34	0	0	0	0	5123	0	0	0	5	26	0	0	17	15	120467	240000	240000	100	120352	120502	120504	120352	120350
480204	120352	967	1	1	1	4	396	91	0	0	4703	0	120336	16	16	180	71	486785	100	245811	240120	102	240351	240216	500	5525482	1945556	120445	120349	120507	40165	10	40236	480550	200	240240	240360	200	480720	720720	120352	120356	3	1	80201	100	99	100	100	80000	80000	100	240000	0	34	0	0	240002	0	0	9	240002	2	34	0	0	0	0	5110	0	0	0	8	17	0	0	7	8	120040	240000	240000	100	120043	120049	120043	120050	120049
480204	120042	964	0	0	0	0	0	3	1	0	6260	0	120028	16	16	41	25	483215	100	245961	240000	100	240000	240000	500	5519567	1942128	120021	120042	120049	39984	3	40025	480100	200	240000	240000	200	480000	720000	120043	120042	1	1	80201	100	99	100	100	80000	80000	100	240000	0	34	0	0	240002	0	0	2	240002	2	34	0	0	0	0	5110	0	0	0	8	17	0	0	4	8	120039	240000	240000	100	120044	120050	120044	120043	120050
480204	120043	964	0	0	0	0	12	3	0	0	8794	0	120027	16	16	0	25	485288	100	244052	240000	100	240000	240000	500	5519567	1930798	120021	120048	120043	39984	3	40024	480100	200	240000	240000	200	480000	720000	120048	120042	1	1	80201	100	99	100	100	80000	80000	100	240000	0	34	2	2	240542	63	0	2	240002	2	34	0	0	0	4	5164	1	367	55	8	26	248	2	9	253	122369	240000	240000	100	120045	120043	120043	120050	120050

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.5007

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	23	37	3a	3f	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd store (99)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	branch cond mispred nonspec (c5)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
480028	120052	930	1	0	0	1	0	0	0	14	0	5661	0	120028	16	16	0	25	484544	10	244999	240000	10	240000	240000	50	5519567	1936725	120023	120048	120042	39984	3	40034	480010	20	240000	240000	20	480000	720000	120042	120058	1	1	80021	10	9	10	10	80000	80000	10	240000	0	34	0	0	240000	0	0	0	240002	2	34	0	0	0	5020	1	17	1	1	120039	0	240000	240000	10	120050	120044	120044	120050	120050
480024	120043	931	0	0	0	0	0	0	132	3	0	8032	0	120488	16	0	270	94	486454	10	244140	240060	10	240117	240216	50	5525386	1942687	123396	120198	120358	40164	9	40340	480685	20	240240	240360	20	480720	720720	120657	120206	4	1	80021	10	9	10	10	80000	80000	10	240182	0	34	104	0	240182	0	7	1743	240182	2	34	0	0	0	5058	1	44	2	1	120181	0	240000	240000	10	120360	120350	120508	120509	120512
480024	120352	967	0	0	0	0	0	0	0	3	0	5926	1	120038	16	16	1	25	487735	10	242860	240000	10	240000	240000	50	5519908	1938805	120037	120062	120051	39992	3	40036	480010	20	240000	240000	20	480000	720000	145103	120052	1	1	80021	10	9	10	10	80000	80000	10	240014	14	44	0	1	240016	4	1	16	240002	16	44	14	0	0	5020	1	17	1	1	120050	0	240000	240000	10	120053	120054	120149	120052	120053
480024	120054	931	1	1	0	1	0	0	12	17	0	5463	1	120037	16	16	1	25	486346	10	243007	240000	10	240000	240000	50	5519860	1960646	120027	120047	120053	39992	3	40044	480010	20	240000	240000	20	480000	720000	120049	120053	1	1	80021	10	9	10	10	80000	80000	10	240014	15	44	0	0	240016	0	1	17	240002	16	44	14	0	0	5019	1	17	1	1	120050	0	240000	240000	10	120051	120063	120054	120054	120054
480024	120055	931	1	1	1	1	0	0	9	19	0	5603	1	120036	16	16	1	25	483345	10	246666	240000	10	240000	240000	50	5519788	1934670	120025	120053	120052	39989	3	40034	480010	20	240000	240000	20	480000	720000	120048	120053	1	1	80021	10	9	10	10	80000	80000	10	240014	14	44	0	1	240016	1	1	18	240002	16	44	14	0	0	5020	1	17	1	1	120050	0	240000	240000	10	120054	120052	120055	120054	120055
480024	120054	930	1	1	0	0	0	0	0	18	0	6136	1	120047	16	16	1	25	486887	10	243597	240000	10	240000	240000	50	5520364	1936226	120026	120051	120054	39991	3	40034	480010	20	240000	240000	20	480000	720000	120051	120054	1	1	80021	10	9	10	10	80000	80000	10	240015	15	44	0	0	240016	0	0	21	240002	16	44	14	0	0	5020	2	17	1	1	120050	0	240000	240000	10	120063	120054	120053	120063	120052
480024	120047	931	1	1	1	0	0	0	6	20	0	9331	1	120037	16	16	7	25	483213	10	248534	240000	10	240000	240000	50	5519668	1941012	120028	120054	120062	39989	3	40035	480010	20	240000	240000	20	480000	720000	120053	120052	1	1	80021	10	9	10	10	80000	80000	10	240014	14	44	0	0	240016	0	0	16	240002	16	44	14	0	1	5019	1	17	1	1	120050	0	240000	240000	10	120053	120055	120052	120051	120063
480024	120051	930	1	1	1	1	0	0	0	19	0	3209	1	120036	16	16	0	25	483213	10	243571	240000	10	240000	240000	50	5519567	1952370	120021	120043	120043	39984	3	40024	480010	20	240000	240000	20	480000	720000	144744	120052	1	1	80021	10	9	10	10	80000	80000	10	240014	15	48	0	0	240016	2	0	17	240002	16	44	14	1	0	5020	1	17	1	1	120049	0	240000	240000	10	120055	120054	120053	120055	120055
480024	120052	930	1	1	1	0	0	0	0	17	0	6796	1	120036	16	16	1	25	483351	10	244249	240000	10	240000	240000	50	5519808	1936331	120026	120051	120054	39990	3	40035	480010	20	240000	240000	20	480000	720000	145341	120054	1	1	80021	10	9	10	10	80000	80000	10	240014	15	44	0	0	240016	0	0	16	240002	16	44	14	0	0	5019	1	17	1	1	120051	0	240000	240000	10	120062	120054	120052	120063	120063
480024	120051	931	1	0	1	0	0	0	0	17	0	5335	1	120038	16	16	8	25	489207	10	244331	240000	10	240000	240000	50	5519884	1946065	120029	120053	120049	39990	3	40036	480010	20	240000	240000	20	480000	720000	120053	120048	1	1	80021	10	9	10	10	80000	80000	10	240015	14	44	0	1	240016	0	0	19	240002	14	0	14	0	0	5020	1	17	1	1	120051	0	240000	240000	10	120054	120054	120054	120053	120052

ST3 (multiple, 16B)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations