Firestorm: ST3 (multiple, 2D) measurements

Code:

  st3 { v0.2d, v1.2d, v2.2d }, [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 6.000

Issues: 6.000

Integer unit issues: 0.000

Load/store unit issues: 3.000

SIMD/FP unit issues: 3.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	1f	22	23	37	3a	3f	46	49	51	schedule uop (52)	schedule simd uop (54)	schedule ldst uop (55)	dispatch simd uop (57)	dispatch ldst uop (58)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	5f	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch ret (8f)	inst simd store (99)	inst ldst (9b)	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	branch ret indir mispred nonspec (c8)	c9	cf	d0	d2	l1i cache miss demand (d3)	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	f5	f6	f7	f8	fd
66008	29645	239	1	28	2	1	27	1	0	1	282	92	0	0	0	4632	29661	2	0	17434	6000	3003	3009	3003	3000	33117	24000	18	22689	29270	29666	9	28	6000	3006	3000	6000	9027	29423	29411	1	1	61001	56	1000	1000	3011	4	6	3	3007	0	1	403	3000	3	9	3	0	0	0	13182	9335	6899	3151	7	48	20505	3298	3810	21	49	51	29019	16275	13153	15066	3000	3000	29693	29668	29667	29730	29723
66004	29656	238	1	18	2	2	21	2	1	1	135	92	0	0	0	4615	29605	0	3	17647	6006	3006	3006	3006	3000	33138	24048	11	22725	29360	29752	15	49	6012	3006	3003	6000	9000	29449	29630	2	1	61001	0	1000	1000	3004	3	0	2	3003	2	1	6	3000	3	0	3	2	0	0	13219	9483	6962	3199	8	44	20586	3331	3808	17	50	48	29023	16367	13049	14936	3000	3000	29333	29446	29646	29538	30135
66004	29469	238	1	24	1	1	23	0	0	0	12	4	1	0	0	4748	29210	0	0	17263	6000	3000	3000	3000	3000	33021	24000	4	22760	57142	29748	3	10	6000	3000	3000	6000	9000	29385	29342	1	1	61001	0	1000	1000	3003	3	0	1	3003	0	0	3	3000	3	0	3	1	0	0	13198	9321	6975	3126	4	54	20219	3252	3810	9	50	50	28777	16131	13456	14709	3000	3000	29398	29503	29512	29420	29302
66004	29343	236	1	20	1	1	15	0	0	0	3	4	0	0	0	4666	29324	0	0	21333	6000	3000	3000	3000	3000	32999	24000	5	22782	28993	29365	3	10	6000	3000	3000	6000	9000	29363	29280	1	1	61001	0	1000	1000	3005	4	9	1	3003	0	1	3	3000	3	6	3	0	0	0	12990	9560	6868	3127	7	44	20143	3182	3816	13	53	54	28763	16209	12725	14872	3000	3000	29345	29255	29393	29475	29392
66004	29788	243	1	17	1	1	22	0	0	1	0	4	0	0	0	4769	29269	0	0	17267	7605	3000	3000	3000	3000	33001	24000	4	22815	29021	29270	3	10	6000	3000	3000	6000	9000	29318	29305	1	1	61001	0	1000	1000	3004	4	9	0	3004	0	2	6	3000	3	6	3	0	19	0	13113	9301	6934	3095	8	43	20155	3259	3816	13	54	55	28579	16212	12869	14825	3000	3000	29339	29319	29250	29426	29476
66004	29488	237	1	25	1	1	13	1	0	1	0	4	0	0	0	4718	29259	3	0	17203	6000	3000	3000	3000	3000	33043	24000	5	22732	28959	29275	3	10	6000	3003	3000	6000	9000	29296	29274	1	1	61001	0	1000	1000	3003	4	0	1	3003	0	1	3	3000	3	9	3	0	0	0	13228	9497	6946	3142	9	45	20029	3207	3810	5	48	51	28556	16027	12666	14773	3000	3000	29394	29359	29239	29420	29256
66004	29283	227	1	22	1	1	21	1	0	0	132	4	0	0	1612	4702	29293	3	0	17211	6000	3000	3000	3000	3000	33035	24000	2	24107	29076	29402	3	10	6000	3000	3000	6000	9000	29303	29184	2	1	61001	0	1000	1000	3006	5	0	1	3003	0	1	3	3000	3	9	3	3	0	0	13307	9434	6946	3113	8	48	20220	3230	3809	9	38	49	28652	16063	12648	14750	3000	3000	29243	29448	29342	29309	29244
66004	29267	228	1	17	1	1	19	0	0	1	0	3	0	0	0	4681	29228	0	0	17180	6000	3000	3000	3000	3000	33014	24000	1	22719	29059	29396	7	10	6000	3000	3003	6000	9000	29341	29264	1	1	61001	0	1000	1000	3004	4	0	1	3003	0	1	448	3000	3	9	3	0	0	0	13099	9636	6907	3190	7	53	20216	3282	3810	17	43	50	28694	16243	12853	14555	3000	3000	29284	29323	29327	29405	29487
66004	29513	227	1	15	1	1	13	1	1	0	0	3	0	0	0	4639	29249	3	3	17276	6000	4608	3000	3000	3001	33038	24000	5	22822	29014	29336	3	10	6000	3000	3000	6000	9000	29352	29300	1	1	61001	0	1000	1000	3009	4	0	1	3003	0	3	3	3000	3	9	3	1	0	0	13122	9525	6945	3196	7	45	20215	3254	3819	10	47	46	28669	16178	12615	14669	3000	3000	29389	29331	29351	29369	29304
66004	29402	228	1	19	1	1	17	1	0	0	0	92	0	0	0	4692	29291	0	0	17376	6000	3000	3000	3000	3000	33028	24000	7	22906	28949	29383	3	10	6000	3000	3000	6000	9000	29240	29357	1	1	61001	0	1000	1000	3004	4	9	2	3003	0	1	3	3000	3	9	3	0	0	0	13221	9380	6955	3152	12	39	20174	3302	3816	13	45	41	28732	16299	12673	14738	3000	3000	29344	29358	29350	29438	29365

Count: 8

Code:

  st3 { v0.2d, v1.2d, v2.2d }, [x6]
  st3 { v0.2d, v1.2d, v2.2d }, [x6]
  st3 { v0.2d, v1.2d, v2.2d }, [x6]
  st3 { v0.2d, v1.2d, v2.2d }, [x6]
  st3 { v0.2d, v1.2d, v2.2d }, [x6]
  st3 { v0.2d, v1.2d, v2.2d }, [x6]
  st3 { v0.2d, v1.2d, v2.2d }, [x6]
  st3 { v0.2d, v1.2d, v2.2d }, [x6]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.5007

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	22	24	37	3a	3f	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd store (99)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
480208	120052	930	0	0	0	0	0	12	3	0	0	7377	0	120027	16	16	0	25	485834	100	245705	240000	100	240000	240000	500	5519567	1954271	120021	0	120043	120043	39984	3	40025	480100	200	240000	240000	200	480000	720000	120043	120043	1	1	80201	100	99	100	100	80000	80000	100	240000	0	0	0	0	240002	5	0	2	240002	2	42	0	0	5110	1	17	1	1	120040	0	240000	240000	100	120044	120044	120043	120044	120043
480204	120043	930	0	0	0	0	0	12	3	0	0	3622	0	120028	16	16	0	25	484845	100	244840	240000	100	240000	240000	500	5519567	1942853	120021	0	120043	120042	39984	3	40033	480100	200	240000	240000	200	480000	720000	120043	120137	1	1	80201	100	99	100	100	80000	80000	100	240000	0	0	0	0	240002	88	0	2	240000	2	0	0	0	5110	1	17	1	1	120040	0	240000	240000	100	120043	120044	120043	120043	120047
480204	120044	930	0	0	0	0	0	0	0	0	0	4524	0	120028	0	16	0	25	488082	100	247139	240000	100	240000	240000	500	5519567	1942853	120021	0	120043	120043	39984	3	40129	480100	200	240000	240000	200	480000	720000	120044	120043	1	1	80201	100	99	100	100	80000	80000	100	240000	0	42	0	0	240002	50	0	2	240002	2	42	0	0	5110	1	17	1	1	120040	0	240000	240000	100	120043	120043	120053	120044	120043
480204	120043	932	0	0	0	0	0	12	3	0	0	4763	0	120027	16	16	0	25	489094	100	244494	240000	100	240000	240000	500	5525530	1958761	120021	0	120043	120043	39984	3	40025	480100	200	240120	240000	200	480000	720000	120043	120043	1	1	80201	100	99	100	100	80000	80000	100	240000	0	0	0	0	240006	10	0	8	240002	2	42	0	0	5110	1	17	1	1	120040	0	240000	240000	100	120197	120043	120043	120044	120043
480204	145352	930	0	0	0	1	0	0	3	0	0	7707	0	120028	16	16	0	25	485670	100	246427	240000	100	240000	240000	500	5519567	1959394	120021	0	120043	120043	39984	3	40024	480100	200	240000	240000	200	480240	720000	120043	120043	1	1	80201	100	99	100	100	80000	80000	100	240000	0	42	0	2	240016	52	0	18	240002	16	44	14	0	5109	1	26	1	1	120049	0	240000	240000	100	120055	120054	120053	120054	120062
480204	120054	931	1	1	2	0	0	0	19	0	0	3000	1	120038	16	16	94	33	481965	100	250987	240000	100	240000	240000	500	5519812	1932794	120029	0	120054	120062	39990	3	40035	480100	200	240000	240000	200	480000	720000	120054	120205	1	1	80201	100	99	100	100	80000	80000	100	240014	14	44	0	0	240016	45	1	17	240002	16	44	14	0	5110	1	17	1	1	120049	0	240000	240000	100	120053	120053	120055	120054	120063
480204	120053	931	1	1	0	0	0	0	17	0	0	5741	1	120040	16	16	1	48	484300	100	249994	240000	100	240000	240000	500	5519932	1933001	120037	0	120050	120052	39991	3	40034	480100	200	240000	240000	200	480000	720000	120052	120053	2	1	80201	100	99	100	100	80000	80000	100	240014	14	44	0	0	240016	53	2	21	240002	16	44	14	0	5109	1	17	1	1	120049	0	240000	240000	100	120053	120052	120054	120054	120052
480204	120053	930	1	1	0	0	0	21	19	0	0	7194	1	120038	16	16	0	25	488897	100	247462	240000	100	240000	240000	500	5519932	1941402	120026	0	120062	120052	39988	7	40036	480100	200	240000	240000	200	480000	720000	120051	120053	1	1	80201	100	99	100	100	80000	80000	100	240015	15	44	0	1	240016	33	0	18	240002	16	46	14	0	5110	1	17	1	1	120049	0	240000	240000	100	120054	120054	120053	120055	120056
480204	120052	931	1	1	0	0	0	12	108	0	0	8987	1	120038	16	16	1	47	484972	100	248662	240000	100	240000	240000	500	5519956	1947002	120028	0	120054	120052	39990	3	40035	480100	200	240000	240000	200	480000	720000	120055	120052	2	1	80201	100	99	100	100	80000	80000	100	240014	15	44	2	0	240016	8	0	19	240002	16	44	14	3	5109	1	17	1	1	120048	0	240000	240000	100	120054	120053	120053	120055	120053
480204	120052	931	1	1	0	0	0	0	20	0	0	7996	1	120039	16	16	0	25	490823	100	248041	240000	100	240000	240216	500	5532240	1933596	120026	0	120051	120053	39988	3	40034	480100	200	240000	240000	200	480000	720000	120207	120052	1	1	80201	100	99	100	100	80000	80000	100	240014	14	44	52	0	240016	78	1	20	240002	16	44	14	1	5110	1	17	1	1	120048	0	240000	240000	100	120055	120054	120208	120054	120054

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.5005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	20	23	24	37	3a	3f	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd store (99)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	c2	branch cond mispred nonspec (c5)	cd	cf	d5	map dispatch bubble (d6)	d9	da	dd	fetch restart (de)	e0	e2	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
480028	120052	931	0	0	0	0	0	91	0	0	0	6854	0	120029	16	0	0	25	488722	10	244052	240000	10	240000	240000	50	5519567	1957165	0	120021	120043	120043	39984	3	40025	480010	20	240000	240000	20	480000	720000	120042	120198	1	1	80021	10	9	10	10	80000	80000	10	240000	0	42	0	3	240002	0	0	0	240002	2	0	0	0	0	5020	5	17	0	7	6	5	120039	0	240000	240000	10	120043	120353	120044	120199	120201
480024	122648	967	1	1	3	2	264	264	0	0	0	5070	0	120485	0	16	271	92	484258	10	243787	240120	10	240117	240216	50	5537024	1948027	0	120440	120351	120349	40073	123	42632	485410	20	240120	240120	20	480480	720360	120508	120351	5	1	80021	10	9	10	10	80000	80000	10	240180	0	42	154	2	240122	0	2	862	240062	2	42	2	0	0	5031	7	17	0	4	6	5	120040	0	240000	240000	10	120044	120045	120044	120045	120044
480024	120042	964	0	0	0	0	6	3	0	0	0	8582	0	120036	16	16	0	25	486437	10	246848	240000	10	240000	240000	50	5519567	1949507	0	120021	120042	120043	39984	3	40026	480010	20	240000	240000	20	480000	720000	120043	120042	1	1	80021	10	9	10	10	80000	80000	10	240000	0	42	0	0	240002	1	0	2	240002	2	42	0	0	0	5020	5	17	0	2	6	5	120040	0	240000	240000	10	120044	120045	120044	120045	120044
480024	120043	964	0	0	0	0	0	3	0	0	0	11906	0	120028	16	16	0	25	485011	10	245001	240000	10	240000	240000	50	5519567	2851683	0	120021	120043	120043	39984	3	40025	480010	20	240000	240000	20	480000	720000	120043	120043	1	1	80021	10	9	10	10	80000	80000	10	240000	0	42	0	0	240002	1	0	2	240002	0	42	0	0	0	5020	5	17	0	1	5	4	120040	0	240000	240000	10	120222	120734	120044	120044	120044
480024	120043	964	0	0	0	0	0	3	0	0	0	5571	0	120028	16	16	0	25	486171	10	246430	240000	10	240000	240000	50	5519567	1956402	0	120021	120043	120043	39984	3	40026	480010	20	240000	240000	20	480000	720000	120043	120044	1	1	80021	10	9	10	10	80000	80000	10	240000	0	42	0	0	240002	3	0	2	240002	2	42	0	0	0	5020	4	17	0	0	6	3	120039	0	240000	240000	10	120047	120044	120048	120044	120044
480024	120043	965	0	0	0	0	0	4	0	0	0	3353	0	120028	16	16	0	25	484299	10	246430	240000	10	240000	240000	50	5519567	1938087	0	120021	120043	120043	39984	3	40026	480010	20	240000	240000	20	480000	720000	120134	120042	1	1	80021	10	9	10	10	80000	80000	10	240000	0	0	0	0	240000	0	0	5	240000	0	44	0	0	0	5020	5	17	0	1	6	5	120040	0	240000	240000	10	120044	120044	120044	120044	120044
480024	120043	964	0	0	0	0	12	3	0	0	0	4285	0	120028	16	0	0	25	486437	10	249285	240000	10	240000	240000	50	5519567	1946419	0	120021	120136	120042	39984	3	40025	480010	20	240000	240000	20	480000	720000	120042	120043	1	1	80021	10	9	10	10	80000	80000	10	240000	0	42	0	0	240002	1	0	2	240002	2	44	0	0	0	5020	9	17	0	1	6	4	120039	0	240000	240000	10	120044	120044	120044	120045	120044
480024	120043	964	0	0	0	0	0	4	0	0	0	7140	0	120029	16	0	0	25	484302	10	245721	240000	10	240000	240117	50	5519567	1958729	0	120021	120043	120043	39984	3	40025	480010	20	240000	240000	20	480000	720000	120043	120043	1	1	80021	10	9	10	10	80000	80000	10	240000	0	42	0	0	240002	0	0	3	240002	2	0	0	0	0	5020	5	17	0	0	5	5	120040	0	240000	240000	10	120044	120044	120044	120044	120044
480024	120043	964	0	0	0	0	0	3	0	0	0	5726	0	120028	0	16	0	25	492149	10	245998	240000	10	240000	240000	50	5519567	1947618	0	120021	120043	120043	39984	3	40025	480010	20	240000	240000	20	480000	720000	120043	144597	1	1	80021	10	9	10	10	80000	80000	10	240000	0	0	0	0	240002	0	0	2	240002	2	42	0	0	0	5020	4	17	0	1	5	3	120039	0	240000	240000	10	120053	120044	120044	120044	120044
480024	120042	964	0	0	0	0	0	3	0	0	1	7447	0	120028	16	16	0	25	486435	10	246427	240000	10	240000	240000	50	5519567	1942389	0	144885	120043	120042	39984	3	40025	480010	20	240000	240000	20	480000	720000	120043	120043	1	1	80021	10	9	10	10	80000	80000	10	240000	0	42	0	0	240002	0	0	2	240002	2	42	0	0	0	5020	5	17	0	0	6	5	120039	0	240000	240000	10	120046	120045	120043	120044	120044

ST3 (multiple, 2D)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations