Firestorm: ST3 (multiple, 2S) measurements

Code:

  st3 { v0.2s, v1.2s, v2.2s }, [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 4.000

Issues: 4.000

Integer unit issues: 0.000

Load/store unit issues: 2.000

SIMD/FP unit issues: 2.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	1f	22	23	24	3a	3f	46	49	51	schedule uop (52)	schedule simd uop (54)	schedule ldst uop (55)	dispatch simd uop (57)	dispatch ldst uop (58)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	5f	60	69	6b	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd store (99)	inst ldst (9b)	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	st unit uop (a7)	l1d cache writeback (a8)	ac	af	l1d cache miss st nonspec (c0)	cf	d0	d2	l1i cache miss demand (d3)	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	f5	f6	f7	f8	fd
64007	29475	228	21	14	0	0	0	51	1	0	0	0	4491	29052	2	2	18221	4000	2000	2000	2000	2000	21611	16000	10	0	21786	0	28912	29225	3	10	4000	2000	2000	4000	6000	29223	29288	1	1	61001	1000	1000	2000	0	0	2000	0	0	2000	6	13133	9332	6887	3116	4	39	20299	3136	3814	7	29	35	28644	16307	13233	14987	2000	2000	29310	29241	29194	29213	29293
64004	29177	227	16	9	0	0	0	12	0	1	0	0	4635	29136	2	2	18407	4000	2000	2000	2000	2000	21612	16000	5	0	21837	0	29002	29327	8	30	4000	2000	2000	4000	6000	29206	29287	1	1	61001	1000	1000	2000	0	6	2000	0	0	2000	6	13126	9359	6956	3084	9	36	20440	3300	3819	16	34	34	28731	16166	13360	14767	2000	2000	29224	29312	29371	29204	29495
64004	29459	228	16	14	0	0	0	12	0	1	0	0	4665	29123	0	2	18141	4000	2000	2000	2000	2000	21607	16000	14	0	21767	0	28833	29244	3	10	4000	2000	2000	4000	6000	29218	29105	1	1	61001	1000	1000	2000	0	6	2000	0	0	2000	0	12864	9209	6871	3032	6	41	20285	3106	3803	14	38	35	28465	16351	13350	15140	2000	2000	29118	29146	29148	29207	29195
64004	29114	219	12	15	0	0	0	9	1	0	0	0	4495	28985	0	2	18047	4000	2000	2000	2000	2000	21633	16000	8	0	21780	0	28943	29246	3	10	4000	2000	2000	4000	6000	29191	29140	1	1	61001	1000	1000	2002	2	6	2000	0	0	2000	6	13026	9099	6835	3019	6	38	20221	3049	3809	10	30	38	28454	16281	13319	14941	2000	2000	29191	29208	29203	29141	29311
64004	29258	219	19	14	0	1	0	3	0	0	0	0	4590	29012	0	2	18159	4000	2000	2000	2000	2000	21623	16000	11	0	21833	0	28847	29124	3	10	4000	2000	2000	4008	6000	29228	29282	2	1	61001	1000	1000	2000	0	6	2000	0	0	2000	0	12847	9161	6842	3033	4	36	20244	3087	3806	6	34	33	28398	16333	13426	15075	2000	2000	29168	29205	29165	29221	29185
64004	29208	219	15	13	0	0	0	3	1	0	0	0	4544	28981	2	2	18087	4000	2000	2000	2000	2000	21611	16000	13	0	21766	0	28772	29204	3	10	4000	2000	2000	4000	6000	29142	29082	1	1	61001	1000	1000	2000	0	0	2000	1	3	2000	0	12873	9185	6873	3071	8	35	20251	3108	3802	9	33	30	28473	16313	13353	15119	2000	2000	29209	29191	29197	29141	29177
64004	29237	218	13	14	0	0	0	0	1	0	0	0	4513	29043	2	2	18290	4000	2000	2000	2000	2000	21618	16000	7	0	21774	0	29162	29198	3	10	4000	2000	2000	4000	6000	29260	29266	1	1	61001	1000	1000	2000	0	0	2000	2	3	2000	6	12868	9030	6859	3047	4	32	20182	3080	3812	8	37	36	28588	16191	13206	15157	2000	2000	29253	29191	29230	29150	29221
64004	29193	218	10	15	0	0	0	0	0	0	0	0	4636	28962	0	0	18117	4000	2000	2000	2000	2000	21614	16000	13	0	21742	0	28845	29159	3	10	4000	2000	2000	4000	6000	29120	29182	1	1	61001	1000	1000	2000	0	6	2000	0	0	2000	6	12890	9216	6794	3012	3	36	20238	3031	3816	7	32	35	28358	16479	13436	14963	2000	2000	29252	29197	29158	29262	29166
64004	29145	218	9	13	0	0	0	12	1	0	0	0	4497	28962	0	0	18125	4000	2000	2000	2000	2000	21612	16000	8	0	21765	0	28887	29266	3	10	4000	2000	2000	4000	6000	29171	29186	1	1	61001	1000	1000	2000	0	6	2000	0	0	2000	6	12786	9220	6833	3074	6	39	20182	3038	3796	11	34	33	28373	16211	13149	15228	2000	2000	29256	29292	29289	29248	29278
64004	29306	219	17	15	0	0	0	3	0	0	0	0	4654	28966	0	0	18063	4000	2000	2000	2000	2000	21604	16000	8	0	21758	0	28956	29224	3	10	4000	2000	2000	4000	6000	29135	29226	1	1	61001	1000	1000	2000	0	0	2000	0	0	2000	6	12798	9238	6816	3008	5	33	20142	3074	3810	2	33	32	28524	16246	13247	15009	2000	2000	29128	29156	29166	29187	29225

Count: 8

Code:

  st3 { v0.2s, v1.2s, v2.2s }, [x6]
  st3 { v0.2s, v1.2s, v2.2s }, [x6]
  st3 { v0.2s, v1.2s, v2.2s }, [x6]
  st3 { v0.2s, v1.2s, v2.2s }, [x6]
  st3 { v0.2s, v1.2s, v2.2s }, [x6]
  st3 { v0.2s, v1.2s, v2.2s }, [x6]
  st3 { v0.2s, v1.2s, v2.2s }, [x6]
  st3 { v0.2s, v1.2s, v2.2s }, [x6]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0006

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	20	22	24	37	3a	3f	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd store (99)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	c2	branch mispred nonspec (cb)	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	e7	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
320207	80071	620	0	0	0	0	0	0	0	3	0	0	0	6367	0	80030	16	16	0	25	324699	100	165862	160000	100	160000	160000	500	2079591	1293946	80024	0	80045	80047	0	3	26	320100	200	160000	160000	200	320000	480000	80046	80043	1	1	80201	100	99	100	100	80000	80000	100	160000	0	42	0	0	160002	2	0	2	160000	2	42	0	0	5113	0	1	17	1	1	80041	0	160000	160000	100	80045	80045	80046	80045	80045
320204	80044	620	0	0	0	0	0	0	12	3	0	0	0	4149	0	80030	16	0	0	25	324262	100	166291	160000	100	160000	160000	500	2238276	1308520	80024	0	80044	80045	0	3	27	320100	200	160000	160000	200	320000	480000	80045	80044	1	1	80201	100	99	100	100	80000	80000	100	160000	0	42	0	0	160002	0	0	5	160002	2	42	0	0	5109	0	1	17	1	1	80042	0	160000	160000	100	80046	80046	80045	80045	80045
320204	80045	621	0	0	0	0	0	0	12	0	0	0	0	4576	0	80029	0	0	0	25	324222	100	163782	160000	100	160000	160000	500	2078914	1302221	80024	0	80045	80043	0	3	124	320100	200	160000	160000	200	320000	480000	80044	80045	1	1	80201	100	99	100	100	80000	80000	100	160000	0	42	0	0	160062	0	0	5	160000	2	42	0	0	5109	0	1	17	1	1	80199	0	160000	160000	100	80047	81581	80045	80047	80045
320204	80044	620	0	0	0	0	0	0	0	3	0	1	0	5704	0	80029	0	16	0	25	324479	100	164092	160000	100	160000	160000	500	1919895	1306458	80025	0	80045	80044	0	3	26	320100	200	160000	160000	200	320000	480000	80045	80212	1	1	80201	100	99	100	100	80000	80000	100	160000	0	42	0	0	160002	0	0	2	160002	2	42	0	0	5110	0	1	17	1	1	80042	0	160000	160000	100	80044	80046	81885	80045	80045
320204	80044	621	0	0	0	0	0	0	0	3	0	0	0	5278	0	80030	16	16	0	25	327173	100	165007	160000	100	160000	160000	500	2079441	1306387	80023	0	80044	80046	0	11	26	320100	200	160000	160000	200	320000	480000	80046	80044	1	1	80201	100	99	100	100	80000	80000	100	160000	0	42	0	0	160002	0	0	0	160002	2	42	0	0	5109	0	1	17	1	1	80041	0	160000	160000	100	80045	80045	80046	80046	80046
320204	80044	621	0	0	0	0	0	0	0	3	0	0	0	4530	0	80030	0	16	0	25	324409	100	162864	160000	100	160000	160000	500	2157038	1294341	80023	0	80045	80044	0	3	27	320100	200	160000	160000	200	320000	480000	80045	80044	1	1	80201	100	99	100	100	80000	80000	100	160000	0	42	0	0	160002	1	0	5	160000	0	42	0	0	5109	0	1	17	1	1	80041	0	160000	160000	100	80045	80045	80044	80046	80045
320204	80211	621	0	0	0	0	0	0	0	0	0	0	0	5626	0	80030	16	16	0	25	326366	100	163834	160000	100	160000	160000	500	2159500	1292719	80024	0	80044	80045	0	3	26	320100	200	160000	160000	200	320000	480000	80045	80045	1	1	80201	100	99	100	100	80000	80000	100	160000	0	0	0	0	160002	2	0	925	160002	2	42	0	0	5109	0	1	17	1	1	80043	0	160000	160000	100	80046	80045	80045	80047	80045
320204	80044	620	0	0	0	0	0	0	0	4	0	0	0	4336	0	80196	16	16	0	25	327236	100	164583	160000	100	160118	160000	500	2078300	1297231	80024	0	80044	80044	0	3	26	320100	200	160000	160000	200	320000	480000	80045	80045	1	1	80201	100	99	100	100	80000	80000	100	160000	0	42	0	0	160002	1	0	2	160002	0	42	0	0	5109	0	1	17	1	1	80042	0	160000	160000	100	80045	80223	80046	80046	80047
320204	80206	621	0	0	0	0	0	0	0	3	0	0	0	4221	0	80030	16	16	0	25	325804	100	163968	160000	100	160000	160000	500	2079788	1296549	80023	0	80045	80045	0	3	26	320100	200	160000	160000	200	320000	480000	80044	80045	1	1	80201	100	99	100	100	80000	80000	100	160000	0	42	0	0	160002	0	0	0	160000	0	42	0	0	5109	0	1	17	1	1	80042	0	160000	160000	100	80046	80045	80045	80047	80046
320204	80044	621	0	0	0	0	0	0	6	3	0	0	0	5571	0	80029	16	16	0	25	326421	100	166102	160060	100	160000	160000	500	2079508	1293850	80024	0	80209	80045	0	3	26	320100	200	160000	160000	200	320000	480000	80045	80045	1	1	80201	100	99	100	100	80000	80000	100	160000	0	42	0	0	160002	1	0	2	160002	2	42	0	0	5367	0	1	17	1	1	80042	0	160000	160000	100	80045	80045	80045	80046	80046

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0006

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	22	24	37	3a	3f	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd store (99)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	branch mispred nonspec (cb)	cd	cf	d0	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
320027	80050	600	1	1	1	0	0	0	0	19	0	0	6	1	80036	16	16	0	25	326386	10	163139	160000	10	160000	160000	50	3679149	1297584	80033	80058	80051	0	3	33	320010	20	160000	160000	20	320000	480000	80050	80050	1	1	80021	10	9	10	10	80000	80000	10	160014	15	36	1	0	160016	0	0	17	160002	16	36	14	0	0	0	5019	0	12	17	0	0	0	12	10	80042	160000	160000	10	80045	80045	80046	80045	80045
320024	80045	621	0	0	0	0	0	0	0	0	0	0	4232	0	80029	0	16	0	25	326656	10	165659	160000	10	160000	160000	50	2158943	1295139	80023	80044	80045	0	3	26	320010	20	160000	160000	20	320000	480000	80044	80044	1	1	80021	10	9	10	10	80000	80000	10	160000	0	34	0	0	160002	0	0	0	160002	2	34	0	0	0	0	5019	0	13	17	0	0	0	12	12	80041	160000	160000	10	80046	80050	80046	80045	80046
320024	80044	621	1	1	0	0	0	0	6	19	0	0	6192	1	80044	0	16	0	25	324685	10	166603	160000	10	160000	160000	50	2639847	1297612	80026	80057	80058	0	3	41	320010	20	160000	160000	20	320000	480000	80058	80060	1	1	80021	10	9	10	10	80000	80000	10	160014	14	36	62	3	160076	1	0	20	160002	16	36	14	0	0	0	5019	0	6	17	0	0	0	13	7	80047	160000	160000	10	80051	80051	80050	80051	80059
320024	80059	621	1	1	0	0	0	0	0	20	0	0	4218	1	80033	16	16	0	25	322391	10	165494	160000	10	160000	160000	50	2399876	1298795	80026	80059	80059	0	3	29	320010	20	160000	160000	20	320000	480000	80058	80049	1	1	80021	10	9	10	10	80000	80000	10	160015	14	36	1	0	160016	0	0	18	160002	16	36	14	0	0	0	5019	0	13	17	0	0	0	12	12	80047	160000	160000	10	80050	80060	80059	80051	80060
320024	80050	620	1	1	0	0	0	0	0	19	0	0	1455	1	80034	16	16	0	25	326719	10	164848	160000	10	160000	160000	50	3679362	1300210	80033	80051	80050	0	3	32	320010	20	160000	160000	20	320000	480000	80052	80052	1	1	80021	10	9	10	10	80000	80000	10	160014	14	34	0	1	160016	0	1	17	160002	16	36	14	0	0	0	5019	0	13	17	0	0	0	5	13	80056	160000	160000	10	80051	80051	80051	80050	80051
320024	80051	621	1	1	0	0	0	0	0	14	0	0	3419	1	80043	16	16	0	25	324525	10	160001	160000	10	160000	160000	50	3679347	1292478	80034	80050	80050	0	3	40	320010	20	160000	160000	20	320000	480000	80059	80051	1	1	80021	10	9	10	10	80000	80000	10	160014	14	44	0	0	160016	0	0	16	160002	16	36	14	0	0	0	5019	0	15	17	0	0	0	5	12	80048	160000	160000	10	80052	80059	80061	80051	80059
320024	80051	621	1	1	0	0	0	0	12	21	0	0	5905	1	80037	0	16	0	25	325208	10	164766	160000	10	160000	160000	50	3679345	1290188	80034	80050	80050	0	3	40	320010	20	160000	160000	20	320000	480000	80044	80045	1	1	80021	10	9	10	10	80000	80000	10	160000	0	34	0	0	160002	1	0	14	160000	2	34	0	0	0	0	5019	0	13	17	0	0	0	6	12	80047	160000	160000	10	80051	80060	80052	80051	80059
320024	80058	621	1	0	0	0	0	0	0	3	0	0	3843	1	80029	16	16	0	25	325487	10	166080	160000	10	160000	160000	50	2316926	1294694	80024	80045	80045	0	3	26	320010	20	160000	160000	22	320000	480000	80050	80051	1	1	80021	10	9	10	10	80000	80000	10	160000	0	0	0	0	160002	0	0	5	160002	16	34	0	0	0	0	5019	0	6	17	0	0	0	13	11	80055	160000	160000	10	80059	80051	80051	80059	80060
320024	80058	620	1	1	1	1	0	0	0	6	0	0	3906	1	80035	16	16	0	25	323978	10	160008	160000	10	160000	160000	50	2399920	1289702	80023	80049	80045	0	3	27	320010	20	160000	160000	20	320000	480000	80060	80058	1	1	80021	10	9	10	10	80000	80000	10	160000	0	36	0	0	160002	0	0	2	160002	0	36	0	0	0	0	5019	0	9	17	0	0	0	12	7	80055	160000	160000	10	80140	80046	80046	80049	80045
320024	80044	620	0	0	0	0	0	0	0	3	0	0	2840	0	80029	0	0	0	25	324500	10	164338	160000	10	160000	160000	50	1919775	1300789	80023	80044	80049	0	3	30	320010	20	160000	160000	20	320000	480000	80058	80058	1	1	80021	10	9	10	10	80000	80000	10	160014	14	36	3	0	160016	0	0	20	160002	0	0	0	0	0	0	5019	0	14	17	0	0	0	5	13	80055	160000	160000	10	80061	80052	80059	80061	80051

ST3 (multiple, 2S)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations