Apple Microarchitecture Research by Dougall Johnson M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions M1/A14 E-core (Icestorm): Overview | Base Instructions | SIMD and FP Instructions
Code:
st3 { v0.4h, v1.4h, v2.4h }, [x6] nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop
mov x0, 0
(no loop instructions)
Retires (minus 60 nops): 4.000
Issues: 4.000
Integer unit issues: 0.000
Load/store unit issues: 2.000
SIMD/FP unit issues: 2.000
retire uop (01) | cycle (02) | 03 | l1i tlb fill (04) | mmu table walk instruction (07) | mmu table walk data (08) | l2 tlb miss instruction (0a) | 18 | 19 | 1e | 1f | 22 | 24 | 3a | 3f | 46 | 49 | 51 | schedule uop (52) | schedule simd uop (54) | schedule ldst uop (55) | dispatch simd uop (57) | dispatch ldst uop (58) | simd uops in schedulers (5a) | ldst uops in schedulers (5b) | 5f | 60 | 61 | 69 | 6d | 6e | map rewind (75) | map stall (76) | dispatch uop (78) | map ldst uop (7d) | map simd uop (7e) | map ldst uop inputs (80) | map simd uop inputs (81) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst simd store (99) | inst ldst (9b) | l1d tlb access (a0) | l1d tlb miss (a1) | l1d cache miss st (a2) | ld unit uop (a6) | st unit uop (a7) | l1d cache writeback (a8) | a9 | ac | af | l1d cache miss st nonspec (c0) | c2 | c9 | cf | d0 | d2 | l1i cache miss demand (d3) | l1i tlb miss demand (d4) | d5 | map dispatch bubble (d6) | d9 | da | db | dd | fetch restart (de) | e0 | ea | eb | ec | ? ldst retires (ed) | ? simd retires (ee) | f5 | f6 | f7 | f8 | fd |
64007 | 29447 | 236 | 2 | 21 | 0 | 20 | 0 | 0 | 144 | 0 | 0 | 0 | 4595 | 29201 | 0 | 0 | 18294 | 4000 | 2000 | 2000 | 2000 | 2000 | 21612 | 16000 | 3 | 0 | 0 | 21782 | 29093 | 29534 | 3 | 10 | 4000 | 2000 | 2000 | 4000 | 6000 | 29408 | 29441 | 1 | 1 | 61001 | 1000 | 1000 | 2000 | 0 | 4 | 0 | 2000 | 0 | 0 | 470 | 2000 | 4 | 0 | 0 | 13164 | 9430 | 6954 | 3165 | 11 | 59 | 20490 | 3314 | 3815 | 14 | 51 | 53 | 28777 | 16356 | 13294 | 14812 | 2000 | 2000 | 29476 | 29489 | 29358 | 29526 | 29430 |
64004 | 29351 | 235 | 0 | 15 | 0 | 21 | 0 | 0 | 12 | 1 | 0 | 0 | 4796 | 29280 | 0 | 0 | 18189 | 4000 | 2000 | 2000 | 2000 | 2000 | 21627 | 16000 | 3 | 0 | 0 | 21805 | 29038 | 29357 | 3 | 10 | 4000 | 2000 | 2000 | 4000 | 6000 | 29420 | 29354 | 1 | 1 | 61001 | 1000 | 1000 | 2000 | 0 | 0 | 3 | 2000 | 0 | 0 | 0 | 2000 | 0 | 0 | 0 | 13218 | 9351 | 6949 | 3164 | 9 | 53 | 20369 | 3238 | 3818 | 10 | 48 | 58 | 28692 | 16311 | 13169 | 14709 | 2000 | 2000 | 29363 | 29322 | 29430 | 29521 | 29524 |
64004 | 29378 | 236 | 0 | 17 | 0 | 20 | 0 | 0 | 0 | 88 | 0 | 0 | 4735 | 29175 | 0 | 0 | 18319 | 4000 | 2000 | 2000 | 2000 | 2000 | 21609 | 16000 | 1 | 0 | 0 | 21798 | 29116 | 29469 | 3 | 10 | 4000 | 2000 | 2000 | 4004 | 6000 | 29327 | 29415 | 2 | 1 | 61001 | 1000 | 1000 | 2000 | 0 | 4 | 0 | 2000 | 0 | 0 | 0 | 2000 | 4 | 0 | 0 | 13382 | 9637 | 6904 | 3096 | 10 | 54 | 20385 | 3395 | 3817 | 12 | 52 | 55 | 28754 | 15983 | 13131 | 14757 | 2000 | 2000 | 29434 | 29428 | 29413 | 29455 | 29414 |
64004 | 29526 | 236 | 0 | 24 | 0 | 16 | 0 | 0 | 0 | 0 | 1 | 0 | 4727 | 29186 | 0 | 0 | 18217 | 4000 | 2000 | 2000 | 2000 | 2000 | 21630 | 16016 | 0 | 0 | 0 | 21844 | 29109 | 29350 | 3 | 10 | 4000 | 2000 | 2000 | 4000 | 6000 | 29331 | 29464 | 1 | 1 | 61001 | 1000 | 1000 | 2000 | 0 | 4 | 0 | 2000 | 0 | 0 | 0 | 2000 | 4 | 0 | 526 | 13349 | 9517 | 6880 | 3171 | 8 | 54 | 20672 | 3326 | 3815 | 10 | 49 | 50 | 28865 | 16201 | 13308 | 15551 | 2000 | 2000 | 29374 | 29284 | 29356 | 29300 | 29324 |
64004 | 29334 | 236 | 0 | 17 | 0 | 14 | 0 | 0 | 0 | 0 | 0 | 0 | 4812 | 29192 | 0 | 0 | 18192 | 4000 | 2000 | 2000 | 2000 | 2000 | 21702 | 16000 | 2 | 0 | 0 | 21847 | 29139 | 29495 | 3 | 10 | 4000 | 2000 | 2000 | 4000 | 6000 | 29320 | 29444 | 1 | 1 | 61001 | 1000 | 1000 | 2000 | 0 | 4 | 0 | 2000 | 0 | 0 | 0 | 2000 | 4 | 2 | 0 | 13410 | 9343 | 6930 | 3180 | 7 | 52 | 20385 | 3252 | 3816 | 13 | 60 | 58 | 28676 | 16116 | 13253 | 14887 | 2000 | 2000 | 29445 | 29454 | 29380 | 29471 | 29360 |
64004 | 29458 | 236 | 0 | 23 | 1 | 20 | 0 | 1 | 132 | 0 | 0 | 0 | 4731 | 29227 | 0 | 0 | 18269 | 4000 | 2000 | 2002 | 2002 | 2002 | 21611 | 16016 | 0 | 0 | 8 | 21852 | 29150 | 29323 | 3 | 29 | 4004 | 2002 | 2000 | 4000 | 6000 | 29321 | 29293 | 3 | 1 | 61001 | 1000 | 1000 | 2000 | 2 | 0 | 2 | 2000 | 0 | 0 | 3 | 2000 | 4 | 2 | 988 | 13246 | 9655 | 7022 | 3163 | 8 | 52 | 20378 | 3232 | 3815 | 8 | 53 | 58 | 28741 | 16066 | 13562 | 15043 | 2000 | 2000 | 29485 | 29451 | 29495 | 29437 | 29439 |
64004 | 29482 | 236 | 0 | 23 | 0 | 15 | 0 | 0 | 132 | 1 | 0 | 0 | 4733 | 29200 | 0 | 0 | 18239 | 4008 | 2000 | 2000 | 2002 | 2000 | 21608 | 16000 | 0 | 0 | 0 | 21854 | 29101 | 29325 | 3 | 30 | 4000 | 2002 | 2002 | 4000 | 6006 | 29316 | 29394 | 2 | 1 | 61001 | 1000 | 1000 | 2000 | 0 | 0 | 2 | 2000 | 0 | 2 | 0 | 2000 | 4 | 0 | 0 | 13173 | 9387 | 6952 | 3122 | 9 | 61 | 20459 | 3268 | 3815 | 12 | 53 | 57 | 28738 | 16119 | 13256 | 14792 | 2000 | 2000 | 29510 | 29453 | 29117 | 29827 | 29560 |
64004 | 29697 | 238 | 0 | 17 | 0 | 20 | 0 | 0 | 0 | 0 | 0 | 0 | 4729 | 29312 | 0 | 0 | 18209 | 4000 | 2000 | 2000 | 2000 | 2000 | 21622 | 16000 | 0 | 0 | 0 | 21803 | 28982 | 29463 | 3 | 10 | 4000 | 2000 | 2000 | 4000 | 6000 | 29357 | 29274 | 1 | 1 | 61001 | 1000 | 1000 | 2000 | 0 | 4 | 0 | 2000 | 0 | 0 | 0 | 2000 | 4 | 0 | 0 | 13085 | 9441 | 6919 | 3138 | 6 | 51 | 20398 | 3254 | 3817 | 12 | 49 | 41 | 28621 | 16282 | 13193 | 14825 | 2000 | 2000 | 29457 | 29397 | 29517 | 29281 | 29244 |
64004 | 29410 | 237 | 0 | 18 | 0 | 15 | 0 | 0 | 0 | 0 | 0 | 0 | 4698 | 29278 | 0 | 0 | 18275 | 4000 | 2000 | 2000 | 2000 | 2000 | 21608 | 16000 | 1 | 0 | 0 | 21863 | 29017 | 29399 | 3 | 10 | 4000 | 2000 | 2000 | 4000 | 6000 | 29367 | 29299 | 1 | 1 | 61001 | 1000 | 1000 | 2000 | 0 | 4 | 0 | 2000 | 0 | 0 | 3 | 2000 | 4 | 0 | 0 | 13315 | 9392 | 6961 | 3130 | 8 | 50 | 20406 | 3212 | 3814 | 9 | 50 | 50 | 28623 | 16287 | 13176 | 14769 | 2000 | 2000 | 29341 | 29381 | 29364 | 29316 | 29397 |
64004 | 29445 | 235 | 0 | 18 | 0 | 21 | 0 | 0 | 0 | 1 | 0 | 0 | 4687 | 29376 | 0 | 0 | 18281 | 4000 | 2000 | 2000 | 2000 | 2000 | 21617 | 16000 | 2 | 0 | 0 | 21853 | 29040 | 29324 | 3 | 10 | 4000 | 2000 | 2000 | 4000 | 6000 | 29374 | 29430 | 1 | 1 | 61001 | 1000 | 1000 | 2000 | 0 | 4 | 0 | 2000 | 1 | 0 | 0 | 2000 | 4 | 0 | 0 | 13201 | 9408 | 6932 | 3089 | 5 | 50 | 20364 | 3262 | 3818 | 18 | 49 | 46 | 28906 | 16043 | 13267 | 15094 | 2000 | 2000 | 29403 | 29486 | 29396 | 29450 | 29404 |
Count: 8
Code:
st3 { v0.4h, v1.4h, v2.4h }, [x6] st3 { v0.4h, v1.4h, v2.4h }, [x6] st3 { v0.4h, v1.4h, v2.4h }, [x6] st3 { v0.4h, v1.4h, v2.4h }, [x6] st3 { v0.4h, v1.4h, v2.4h }, [x6] st3 { v0.4h, v1.4h, v2.4h }, [x6] st3 { v0.4h, v1.4h, v2.4h }, [x6] st3 { v0.4h, v1.4h, v2.4h }, [x6]
mov x7, x6 mov x8, x6 mov x9, x6 mov x10, x6 mov x11, x6 mov x12, x6 mov x13, x6
(fused SUBS/B.cc loop)
Result (median cycles for code divided by count): 1.0006
retire uop (01) | cycle (02) | 03 | l1d tlb fill (05) | mmu table walk data (08) | l2 tlb miss data (0b) | 18 | 19 | 1e | 1f | 22 | 37 | 3a | 3f | 46 | 49 | 4f | 51 | schedule uop (52) | schedule int uop (53) | schedule simd uop (54) | schedule ldst uop (55) | dispatch int uop (56) | dispatch simd uop (57) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | ldst uops in schedulers (5b) | 69 | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map simd uop (7e) | map int uop inputs (7f) | map ldst uop inputs (80) | map simd uop inputs (81) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int alu (97) | inst simd store (99) | inst ldst (9b) | 9f | l1d tlb access (a0) | l1d tlb miss (a1) | l1d cache miss st (a2) | a4 | ld unit uop (a6) | st unit uop (a7) | l1d cache writeback (a8) | a9 | ac | af | bc | l1d cache miss st nonspec (c0) | l1d tlb miss nonspec (c1) | c2 | cf | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ? ldst retires (ed) | ? simd retires (ee) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
320207 | 80059 | 652 | 1 | 2 | 0 | 0 | 0 | 12 | 17 | 0 | 3477 | 1 | 80037 | 16 | 16 | 0 | 48 | 325069 | 100 | 162936 | 160000 | 100 | 160000 | 160000 | 500 | 2559741 | 1300039 | 80037 | 80221 | 80050 | 0 | 3 | 34 | 320100 | 200 | 160120 | 160000 | 200 | 320000 | 480000 | 80050 | 80053 | 2 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 160016 | 20 | 44 | 0 | 1 | 160016 | 2 | 3 | 19 | 160002 | 16 | 44 | 14 | 0 | 5109 | 13 | 17 | 13 | 6 | 80048 | 160000 | 160000 | 100 | 80063 | 80053 | 80052 | 80053 | 80052 |
320204 | 80051 | 643 | 1 | 1 | 1 | 0 | 0 | 12 | 18 | 0 | 6108 | 1 | 80036 | 16 | 16 | 0 | 25 | 324418 | 100 | 164978 | 160000 | 100 | 160000 | 160000 | 500 | 2719794 | 1300184 | 80027 | 80050 | 80051 | 0 | 3 | 33 | 320100 | 200 | 160000 | 160000 | 200 | 320000 | 480000 | 80051 | 80051 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 160014 | 14 | 0 | 0 | 0 | 160016 | 0 | 1 | 21 | 160002 | 14 | 44 | 14 | 0 | 5109 | 15 | 17 | 15 | 15 | 80048 | 160000 | 160000 | 100 | 80052 | 80053 | 80061 | 80051 | 80053 |
320204 | 80051 | 642 | 1 | 0 | 0 | 0 | 0 | 15 | 18 | 0 | 7462 | 1 | 80037 | 16 | 16 | 0 | 25 | 325944 | 100 | 164313 | 160000 | 100 | 160000 | 160000 | 500 | 2799791 | 1300868 | 80027 | 80062 | 80063 | 0 | 3 | 29 | 320100 | 200 | 160000 | 160000 | 200 | 320000 | 480000 | 80051 | 80053 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 160015 | 14 | 0 | 0 | 0 | 160016 | 0 | 0 | 14 | 160000 | 16 | 44 | 14 | 0 | 5109 | 14 | 17 | 12 | 13 | 80049 | 160000 | 160000 | 100 | 80052 | 80051 | 80052 | 80052 | 80052 |
320204 | 80050 | 643 | 1 | 1 | 1 | 0 | 0 | 15 | 17 | 0 | 3636 | 1 | 80048 | 16 | 0 | 0 | 25 | 320108 | 100 | 164131 | 160000 | 100 | 160000 | 160000 | 500 | 2479917 | 1313350 | 80026 | 80052 | 80050 | 0 | 3 | 34 | 320100 | 200 | 160000 | 160000 | 200 | 320000 | 480000 | 80053 | 80051 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 160014 | 14 | 44 | 0 | 1 | 160016 | 0 | 0 | 20 | 160000 | 14 | 44 | 14 | 0 | 5109 | 13 | 17 | 14 | 14 | 80048 | 160000 | 160000 | 100 | 80063 | 80054 | 80053 | 80051 | 80052 |
320204 | 80047 | 643 | 1 | 1 | 1 | 0 | 0 | 3 | 17 | 0 | 3143 | 1 | 80036 | 16 | 16 | 0 | 25 | 327153 | 100 | 164232 | 160000 | 100 | 160000 | 160000 | 500 | 2559884 | 1303504 | 80027 | 80062 | 80050 | 0 | 3 | 33 | 320100 | 200 | 160000 | 160000 | 200 | 320000 | 480000 | 80052 | 80052 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 160014 | 14 | 44 | 0 | 2 | 160016 | 1 | 0 | 16 | 160002 | 16 | 44 | 14 | 0 | 5109 | 13 | 17 | 13 | 13 | 80182 | 160000 | 160000 | 100 | 80052 | 80048 | 80053 | 80052 | 80050 |
320204 | 80050 | 643 | 1 | 1 | 0 | 0 | 0 | 6 | 17 | 0 | 3728 | 1 | 80036 | 16 | 16 | 0 | 25 | 324521 | 100 | 161939 | 160000 | 100 | 160000 | 160000 | 500 | 2399920 | 1787898 | 80025 | 80047 | 80050 | 0 | 3 | 34 | 320100 | 200 | 160000 | 160000 | 200 | 320000 | 480000 | 80053 | 80051 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 160015 | 14 | 44 | 0 | 0 | 160016 | 0 | 2 | 23 | 160002 | 14 | 0 | 14 | 1 | 5109 | 13 | 17 | 14 | 13 | 80046 | 160000 | 160000 | 100 | 80054 | 80051 | 80052 | 80053 | 80051 |
320204 | 80053 | 643 | 1 | 0 | 0 | 0 | 0 | 15 | 17 | 0 | 5981 | 1 | 80036 | 15 | 16 | 0 | 25 | 323238 | 100 | 164987 | 160000 | 100 | 160000 | 160000 | 500 | 3679498 | 1300007 | 80026 | 80052 | 80052 | 1 | 3 | 35 | 320100 | 200 | 160000 | 160000 | 200 | 320000 | 480000 | 80051 | 80051 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 160015 | 14 | 46 | 0 | 0 | 160016 | 0 | 1 | 14 | 160002 | 16 | 44 | 14 | 0 | 5109 | 13 | 17 | 8 | 14 | 80049 | 160000 | 160000 | 100 | 80054 | 80063 | 80049 | 80054 | 80063 |
320204 | 80051 | 643 | 1 | 1 | 0 | 0 | 0 | 15 | 19 | 0 | 3917 | 1 | 80037 | 16 | 16 | 0 | 25 | 321920 | 100 | 165451 | 160000 | 100 | 160000 | 160000 | 500 | 2799764 | 1297457 | 80029 | 80062 | 80050 | 0 | 3 | 33 | 320100 | 200 | 160000 | 160000 | 200 | 320000 | 480000 | 80052 | 80052 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 160015 | 15 | 44 | 0 | 1 | 160016 | 0 | 0 | 17 | 160002 | 14 | 44 | 14 | 0 | 5109 | 8 | 17 | 14 | 10 | 80049 | 160000 | 160000 | 100 | 80052 | 80052 | 80053 | 80051 | 80052 |
320204 | 80062 | 643 | 1 | 1 | 1 | 0 | 0 | 3 | 18 | 0 | 5641 | 1 | 80035 | 16 | 16 | 0 | 25 | 325723 | 100 | 164707 | 160000 | 100 | 160000 | 160000 | 500 | 2559749 | 1297316 | 80026 | 80053 | 80053 | 0 | 3 | 33 | 320100 | 200 | 160000 | 160000 | 200 | 320000 | 480000 | 80051 | 80051 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 160015 | 14 | 42 | 0 | 1 | 160016 | 0 | 1 | 17 | 160002 | 16 | 44 | 14 | 0 | 5109 | 13 | 17 | 13 | 13 | 80049 | 160000 | 160000 | 100 | 80051 | 80052 | 80053 | 80064 | 80048 |
320204 | 80050 | 643 | 1 | 0 | 1 | 0 | 0 | 3 | 18 | 0 | 3996 | 1 | 80036 | 16 | 16 | 0 | 25 | 324797 | 100 | 161616 | 160000 | 100 | 160000 | 160000 | 500 | 2479902 | 1290039 | 81487 | 80051 | 80052 | 0 | 3 | 32 | 320100 | 200 | 160000 | 160000 | 200 | 320000 | 480000 | 80051 | 80051 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 160015 | 14 | 44 | 0 | 0 | 160016 | 2 | 0 | 22 | 160002 | 16 | 44 | 14 | 0 | 5109 | 11 | 17 | 15 | 15 | 80047 | 160000 | 160000 | 100 | 80051 | 80052 | 80054 | 80063 | 80048 |
Result (median cycles for code divided by count): 1.0006
retire uop (01) | cycle (02) | 03 | l1d tlb fill (05) | mmu table walk data (08) | l2 tlb miss instruction (0a) | l2 tlb miss data (0b) | 18 | 19 | 1e | 1f | 24 | 37 | 3a | 3f | 46 | 49 | 4f | 51 | schedule uop (52) | schedule int uop (53) | schedule simd uop (54) | schedule ldst uop (55) | dispatch int uop (56) | dispatch simd uop (57) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | ldst uops in schedulers (5b) | 60 | 61 | 69 | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map simd uop (7e) | map int uop inputs (7f) | map ldst uop inputs (80) | map simd uop inputs (81) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | 91 | inst branch cond (94) | inst int alu (97) | inst simd store (99) | inst ldst (9b) | 9f | l1d tlb access (a0) | l1d tlb miss (a1) | l1d cache miss st (a2) | a4 | ld unit uop (a6) | st unit uop (a7) | l1d cache writeback (a8) | a9 | ac | af | bc | l1d cache miss st nonspec (c0) | l1d tlb miss nonspec (c1) | c2 | branch mispred nonspec (cb) | cf | d0 | d2 | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ? ldst retires (ed) | ? simd retires (ee) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
320027 | 80058 | 620 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 19 | 0 | 3640 | 1 | 80036 | 0 | 16 | 0 | 25 | 323900 | 10 | 164870 | 160000 | 10 | 160000 | 160000 | 50 | 2157526 | 1295316 | 0 | 0 | 80025 | 80045 | 80045 | 0 | 3 | 27 | 320010 | 20 | 160000 | 160000 | 20 | 320000 | 480000 | 80044 | 80044 | 1 | 1 | 80021 | 10 | 9 | 0 | 10 | 10 | 80000 | 80000 | 10 | 160000 | 0 | 44 | 0 | 0 | 160002 | 0 | 0 | 2 | 160000 | 2 | 42 | 0 | 0 | 0 | 5019 | 0 | 0 | 3 | 17 | 3 | 3 | 80042 | 160000 | 160000 | 10 | 80052 | 80063 | 80052 | 80052 | 80052 |
320024 | 80062 | 643 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 18 | 0 | 4546 | 1 | 80038 | 0 | 16 | 0 | 25 | 322759 | 10 | 166106 | 160000 | 10 | 160000 | 160000 | 50 | 2559860 | 1295437 | 0 | 0 | 80026 | 80052 | 80052 | 1 | 3 | 33 | 320010 | 20 | 160000 | 160000 | 20 | 320000 | 480000 | 80052 | 80050 | 1 | 1 | 80021 | 10 | 9 | 0 | 10 | 10 | 80000 | 80000 | 10 | 160000 | 0 | 42 | 0 | 0 | 160002 | 1 | 0 | 3 | 160002 | 2 | 42 | 0 | 0 | 0 | 5019 | 0 | 2 | 3 | 17 | 3 | 2 | 80039 | 160000 | 160000 | 10 | 80045 | 80044 | 80045 | 80045 | 80045 |
320024 | 80046 | 642 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0 | 5626 | 0 | 80048 | 16 | 16 | 0 | 25 | 324320 | 10 | 164391 | 160000 | 10 | 160000 | 160000 | 50 | 2719782 | 1283674 | 0 | 0 | 80027 | 80051 | 80051 | 0 | 3 | 33 | 320010 | 20 | 160000 | 160000 | 20 | 320000 | 480000 | 80063 | 80050 | 1 | 1 | 80021 | 10 | 9 | 0 | 10 | 10 | 80000 | 80000 | 10 | 160000 | 0 | 44 | 0 | 0 | 160002 | 1 | 0 | 2 | 160002 | 2 | 42 | 0 | 0 | 0 | 5019 | 0 | 0 | 3 | 17 | 3 | 3 | 80042 | 160000 | 160000 | 10 | 80048 | 80046 | 80045 | 80047 | 80045 |
320024 | 80045 | 643 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0 | 3875 | 0 | 80030 | 0 | 16 | 0 | 25 | 325810 | 10 | 164646 | 160000 | 10 | 160000 | 160000 | 50 | 2079027 | 1295978 | 0 | 0 | 80024 | 80044 | 80045 | 0 | 3 | 27 | 320010 | 20 | 160000 | 160000 | 20 | 320000 | 480000 | 80045 | 80044 | 1 | 1 | 80021 | 10 | 9 | 2 | 10 | 10 | 80000 | 80000 | 10 | 160000 | 0 | 0 | 0 | 0 | 160002 | 0 | 0 | 2 | 160002 | 2 | 42 | 0 | 0 | 0 | 5019 | 0 | 0 | 3 | 17 | 3 | 3 | 80040 | 160000 | 160000 | 10 | 80046 | 80046 | 80045 | 80046 | 80045 |
320024 | 80045 | 643 | 0 | 0 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 4098 | 0 | 80029 | 16 | 16 | 0 | 25 | 326138 | 10 | 165298 | 160000 | 10 | 160000 | 160000 | 50 | 2234462 | 1290586 | 1 | 0 | 80024 | 80043 | 80044 | 0 | 3 | 27 | 320010 | 20 | 160000 | 160000 | 20 | 320000 | 480000 | 80045 | 80045 | 1 | 1 | 80021 | 10 | 9 | 0 | 10 | 10 | 80000 | 80000 | 10 | 160000 | 0 | 42 | 0 | 0 | 160000 | 1 | 0 | 2 | 160002 | 0 | 0 | 0 | 0 | 0 | 5019 | 0 | 0 | 2 | 17 | 3 | 2 | 80041 | 160000 | 160000 | 10 | 80046 | 80046 | 80046 | 80047 | 80045 |
320024 | 80044 | 643 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0 | 5704 | 0 | 80029 | 0 | 0 | 0 | 25 | 325719 | 10 | 164578 | 160000 | 10 | 160000 | 160000 | 50 | 2078874 | 1301628 | 0 | 0 | 80024 | 80045 | 80045 | 0 | 3 | 27 | 320010 | 20 | 160000 | 160000 | 20 | 320000 | 480000 | 80045 | 80044 | 1 | 1 | 80021 | 10 | 9 | 0 | 10 | 10 | 80000 | 80000 | 10 | 160000 | 0 | 42 | 0 | 0 | 160000 | 1 | 0 | 2 | 160002 | 2 | 42 | 0 | 0 | 0 | 5019 | 0 | 0 | 3 | 17 | 3 | 3 | 80041 | 160000 | 160000 | 10 | 80046 | 80046 | 80045 | 80046 | 80046 |
320024 | 80046 | 642 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0 | 6266 | 0 | 80045 | 0 | 16 | 0 | 25 | 325946 | 10 | 166470 | 160000 | 10 | 160000 | 160000 | 50 | 1998802 | 1293557 | 0 | 0 | 80024 | 80045 | 80044 | 0 | 3 | 27 | 320010 | 20 | 160000 | 160000 | 20 | 320000 | 480000 | 80044 | 80048 | 1 | 1 | 80021 | 10 | 9 | 0 | 10 | 10 | 80000 | 80000 | 10 | 160000 | 0 | 42 | 0 | 0 | 160002 | 0 | 0 | 2 | 160002 | 2 | 42 | 0 | 0 | 0 | 5019 | 0 | 0 | 3 | 17 | 3 | 3 | 80041 | 160000 | 160000 | 10 | 80045 | 80045 | 80046 | 80045 | 80046 |
320024 | 80044 | 643 | 0 | 0 | 0 | 0 | 0 | 0 | 6 | 3 | 0 | 4345 | 0 | 80029 | 16 | 0 | 0 | 25 | 323068 | 10 | 163700 | 160000 | 10 | 160000 | 160000 | 50 | 2079591 | 1301968 | 0 | 0 | 80023 | 80046 | 80045 | 0 | 3 | 26 | 320010 | 20 | 160000 | 160000 | 20 | 320000 | 480000 | 80046 | 80045 | 1 | 1 | 80021 | 10 | 9 | 0 | 10 | 10 | 80000 | 80000 | 10 | 160000 | 0 | 42 | 0 | 0 | 160002 | 0 | 0 | 6 | 160002 | 2 | 42 | 0 | 0 | 0 | 5019 | 0 | 0 | 3 | 17 | 3 | 3 | 80042 | 160000 | 160000 | 10 | 80045 | 80046 | 80046 | 80045 | 80047 |
320024 | 80044 | 642 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0 | 5847 | 0 | 80037 | 16 | 16 | 0 | 25 | 327225 | 10 | 164517 | 160000 | 10 | 160000 | 160000 | 50 | 2236386 | 1302297 | 0 | 0 | 80024 | 80045 | 80045 | 0 | 3 | 27 | 320010 | 20 | 160000 | 160000 | 20 | 320000 | 480000 | 80045 | 80045 | 1 | 1 | 80021 | 10 | 9 | 0 | 10 | 10 | 80000 | 80000 | 10 | 160000 | 0 | 42 | 0 | 0 | 160002 | 1 | 0 | 6 | 160002 | 0 | 42 | 0 | 0 | 0 | 5019 | 0 | 0 | 3 | 17 | 2 | 3 | 80042 | 160000 | 160000 | 10 | 80046 | 80046 | 80045 | 80046 | 80046 |
320024 | 80045 | 643 | 0 | 0 | 0 | 0 | 0 | 0 | 33 | 3 | 0 | 5034 | 0 | 80032 | 16 | 0 | 0 | 25 | 422077 | 10 | 166158 | 160000 | 10 | 160000 | 160000 | 50 | 2306429 | 1294266 | 0 | 0 | 80028 | 80044 | 80044 | 0 | 3 | 28 | 320010 | 20 | 160000 | 160000 | 20 | 320000 | 480360 | 80045 | 80044 | 1 | 1 | 80021 | 10 | 9 | 0 | 10 | 10 | 80000 | 80000 | 10 | 160000 | 0 | 42 | 0 | 0 | 160002 | 1 | 0 | 2 | 160002 | 2 | 42 | 0 | 0 | 0 | 5047 | 0 | 0 | 5 | 26 | 3 | 3 | 80197 | 160000 | 160000 | 10 | 80212 | 80213 | 80211 | 80208 | 80376 |