Firestorm: ST3 (multiple, 4S) measurements

Code:

  st3 { v0.4s, v1.4s, v2.4s }, [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 6.000

Issues: 6.000

Integer unit issues: 0.000

Load/store unit issues: 3.000

SIMD/FP unit issues: 3.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0e	18	19	1e	1f	22	23	37	3a	3f	46	49	51	schedule uop (52)	schedule simd uop (54)	schedule ldst uop (55)	dispatch simd uop (57)	dispatch ldst uop (58)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	5f	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd store (99)	inst ldst (9b)	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	c2	c9	cf	d0	d2	l1i cache miss demand (d3)	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	f5	f6	f7	f8	fd
66008	29250	233	22	0	0	15	0	0	0	0	0	0	0	0	0	4763	28741	0	3	16620	6000	3000	3000	3000	3000	33045	24000	13	22709	28689	28854	3	10	6000	3000	3000	6000	9000	28652	28582	2	1	61001	1000	1000	3003	9	7	0	0	3002	1	0	402	3000	0	0	0	0	13278	9451	6939	3125	7	37	19554	3286	3819	19	34	33	28114	15267	12256	14190	3000	3000	28934	28892	28945	29016	28841
66004	28923	231	8	0	0	17	1	0	1	1	132	1	0	0	0	4772	28487	1	2	16597	6000	3003	3000	3009	3009	33104	24096	7	22881	29325	29584	33	121	6018	3006	3012	6024	9054	29429	29608	7	1	61001	1000	1000	3000	0	7	0	0	3000	0	0	0	3000	1	9	0	0	13302	9424	6991	3175	6	39	19612	3166	3817	15	37	40	28378	15299	13465	15753	3000	3000	29069	29171	29236	29091	29147
66004	29055	233	13	1	0	18	0	0	0	1	0	89	0	0	0	4740	28991	0	2	16966	6000	3000	3003	3000	3003	33059	24000	0	22771	28893	29065	12	10	6000	3000	3000	6000	9009	29077	28917	2	1	61001	1000	1000	3000	2	0	0	0	3000	0	0	4	3000	0	6	0	0	13067	9479	6902	3129	7	36	19952	3205	3813	15	38	38	28570	16068	12693	14572	3000	3000	29037	29057	29024	29149	29161
66004	29111	234	15	1	0	15	0	0	1	1	12	1	0	0	0	4765	29249	0	0	17097	6000	3000	3000	3003	3000	33933	24000	8	22757	28797	29030	3	10	6000	3000	3000	6000	9000	28880	28867	1	1	61001	1000	1000	3000	0	0	0	0	3000	0	0	0	3000	0	6	0	0	13122	9433	6974	3109	7	37	19666	3307	3820	19	39	41	28382	15821	12442	14399	3000	3000	28901	28890	29109	28867	28882
66004	28936	231	12	0	0	12	1	0	0	0	132	1	0	0	0	4760	28921	0	0	16777	6000	3000	3000	3000	3000	32998	24000	5	24148	28633	28913	3	10	6000	3000	3000	6000	9000	28886	28905	1	1	61001	1000	1000	3000	0	0	0	0	3000	0	0	1	3000	0	0	0	0	13078	9436	6944	3160	7	41	19631	3256	3810	10	38	36	28353	15770	12470	14512	3000	3000	28908	28933	28848	28844	28809
66004	28800	232	15	0	0	11	0	0	0	0	0	0	1	0	0	4740	28871	0	0	16722	6000	3003	3000	3000	3000	33030	24000	10	22810	28695	28916	3	10	6000	3000	3000	6000	9000	29306	29215	1	1	61001	1000	1000	3000	0	9	0	0	3000	1	0	1	3001	0	0	0	0	13120	9241	6907	3119	5	38	19940	3327	3816	10	42	40	28656	16126	12460	14398	3000	3000	29217	28960	28947	28897	28915
66004	29042	234	15	0	0	9	0	0	0	1	24	1	0	0	0	4711	28939	1	2	16836	6000	3000	3000	3000	3000	33010	24024	2	22769	28653	29011	3	10	6000	3000	3000	6000	9000	28742	28826	1	1	61001	1000	1000	3000	0	0	0	0	3000	0	0	1	3004	0	6	0	0	13171	9308	6889	3112	7	42	19689	3274	3815	11	44	34	28417	15628	12416	14275	3000	3000	28977	28889	28933	28891	28979
66004	28858	232	18	0	0	13	0	0	0	0	0	1	0	0	0	4787	28814	0	0	16838	7621	3000	3000	3000	3000	33039	24000	5	22798	28694	29031	3	28	6006	3000	3000	6000	9000	28936	28809	2	1	61001	1000	1000	3000	2	6	0	0	3000	0	0	0	3000	0	7	0	0	13177	9550	6951	3104	9	35	19774	3310	3814	9	35	35	28440	15662	12502	14422	3000	3000	28928	28942	28890	28956	28982
66004	28810	231	10	0	0	9	0	0	0	0	0	0	0	0	0	4742	28951	0	2	16792	6006	3000	3000	3000	3000	33040	24024	4	22684	28674	28904	3	10	6000	3000	3000	6006	9000	28957	28856	1	1	61001	1000	1000	3000	0	0	0	0	3000	0	0	0	3000	0	6	0	0	13175	9463	6922	3046	3	41	19765	3249	3817	8	37	39	28473	15415	12429	14470	3000	3000	28922	28958	28922	28872	28896
66004	28969	233	18	0	0	17	1	0	0	0	0	1	0	0	0	4738	28916	0	0	16837	6000	3000	3000	3000	3000	33009	24000	4	22717	28638	29053	3	10	6000	3000	3000	6000	9000	29145	28882	1	1	61001	1000	1000	3000	2	6	0	0	3001	0	2	1	3000	1	6	0	0	13441	9355	6980	3132	7	39	19634	3180	3819	14	41	41	28326	15546	12386	13911	3000	3000	28732	28749	28821	28672	28576

Count: 8

Code:

  st3 { v0.4s, v1.4s, v2.4s }, [x6]
  st3 { v0.4s, v1.4s, v2.4s }, [x6]
  st3 { v0.4s, v1.4s, v2.4s }, [x6]
  st3 { v0.4s, v1.4s, v2.4s }, [x6]
  st3 { v0.4s, v1.4s, v2.4s }, [x6]
  st3 { v0.4s, v1.4s, v2.4s }, [x6]
  st3 { v0.4s, v1.4s, v2.4s }, [x6]
  st3 { v0.4s, v1.4s, v2.4s }, [x6]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.5007

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	22	23	24	37	3a	3f	46	49	4f	50	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd store (99)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
480208	120052	931	1	0	0	1	1	0	30	21	0	0	0	8129	1	120043	16	16	0	0	25	488906	100	245602	240000	100	240015	240010	500	5519878	1948561	0	120026	120052	120058	39999	7	40032	480128	200	240018	240138	200	480036	720054	120058	120051	1	1	80201	100	99	100	100	80000	80000	100	240014	14	36	0	0	240016	0	0	158	240002	0	34	0	2	1	1	1	5117	1	16	0	0	120046	0	240000	240000	100	120044	120050	120043	120043	120044
480204	120057	930	1	1	1	1	0	0	9	19	0	0	0	2334	1	120033	16	16	0	0	25	485438	100	245401	240000	100	240018	240010	500	5525740	1957246	0	120024	120048	120043	39987	7	40014	480124	200	240138	240018	200	480036	720054	120048	120042	1	1	80201	100	99	100	100	80000	80000	100	240000	0	34	0	0	240002	0	0	26	240060	16	36	14	1	1	1	1	5117	0	16	0	0	120039	0	240000	240000	100	120043	120043	120044	120044	120043
480204	120058	931	1	0	1	0	0	0	0	19	0	0	0	6007	1	120033	0	0	0	0	25	481444	100	241567	240000	100	240015	240010	500	5519729	1929272	0	120023	120049	120042	39987	7	40015	480128	200	240018	240018	200	480036	720054	120049	120043	1	1	80201	100	99	100	100	80000	80000	100	240000	0	34	0	0	240000	0	0	18	240002	16	36	14	1	1	1	1	5117	0	16	0	0	120040	0	240000	240000	100	120043	120043	120049	120044	120043
480204	120058	931	1	0	0	1	0	0	132	18	0	0	0	7219	1	120044	16	16	0	0	25	486844	100	244766	240000	100	240018	240010	500	5519615	1941733	0	120021	120043	120042	39987	7	40014	480128	200	240018	240018	200	480036	720054	120193	120048	1	1	80201	100	99	100	100	80000	80000	100	240000	0	34	0	0	240000	1	0	18	240002	16	0	0	0	1	1	1	5117	0	16	0	0	120039	0	240000	240000	100	120206	120043	120043	120049	120049
480204	120059	930	1	1	0	0	0	0	0	18	0	0	0	4146	1	120035	16	16	4	0	25	486765	100	246516	240000	100	240015	240010	500	5519615	1939063	0	120024	120202	120043	39987	7	40014	480128	200	240120	240000	200	480000	720000	120042	120042	1	1	80201	100	99	100	100	80000	80000	100	240000	0	34	0	0	240002	0	0	18	240122	2	34	0	0	0	0	0	5110	1	17	1	1	120040	0	240000	240000	100	120043	120043	120043	120043	120043
480204	120066	932	1	0	1	0	0	0	0	19	0	0	0	7207	1	120035	16	16	3	0	25	486766	100	245137	240000	100	240000	240000	500	5519567	1956111	0	120021	120043	120042	39984	3	40129	480100	200	240000	240000	200	480000	720000	120042	120049	1	1	80201	100	99	100	100	80000	80000	100	240000	0	34	0	0	240002	0	0	23	240000	14	36	14	1	0	0	0	5110	1	17	1	1	120047	0	240000	240000	100	120059	120052	120052	120050	120059
480204	120048	931	0	0	0	0	0	0	0	3	0	0	0	2245	0	120027	0	16	0	0	25	488907	100	245802	240000	100	240000	240000	500	5519692	1947314	0	120026	120050	120053	39996	3	40039	480100	200	240000	240000	200	480000	720000	120050	120060	1	1	80201	100	99	100	100	80000	80000	100	240000	0	34	0	0	240002	0	0	21	240002	16	36	14	1	0	0	0	5109	1	17	1	1	120056	0	240000	240000	100	120050	120059	120053	120049	120050
480204	120048	931	0	0	0	0	0	0	6	3	0	0	0	4811	0	120028	16	16	0	0	25	489424	100	243000	240000	100	240000	240000	500	5519764	1940325	0	120033	120058	120061	39986	3	40136	480100	200	240000	240000	200	480000	720000	120058	120057	1	1	80201	100	99	100	100	80000	80000	100	240015	14	36	0	0	240016	1	0	2	240000	0	0	0	0	0	0	0	5110	1	17	1	1	120039	0	240000	240000	100	120043	120044	120049	120043	120044
480204	120051	930	1	1	0	0	0	0	6	18	0	0	0	6797	1	120043	16	16	4	0	25	482432	100	248796	240000	100	240000	240000	500	5519567	1952835	1	120164	120196	120049	39984	9	40132	480325	200	240258	240000	200	480000	720000	120197	120042	1	1	80201	100	99	100	100	80000	80000	100	240062	0	0	102	0	240120	0	0	23364	240120	14	36	14	0	0	0	0	5134	2	26	2	1	120339	1	240000	240000	100	123588	123872	124205	124206	120464
480204	120353	933	0	1	1	1	3	1	264	267	0	0	0	5267	0	120335	16	16	2	0	25	483683	100	244581	240000	100	240000	240000	500	5519618	1932803	0	120035	120060	120052	39997	3	40041	480100	200	240000	240000	200	480000	720000	120050	120059	1	1	80201	100	99	100	100	80000	80000	100	240014	15	36	1	0	240014	0	1	5	240002	2	34	0	0	0	0	0	5110	1	17	1	1	120040	0	240000	240000	100	120043	120043	120043	120050	120043

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.5007

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	18	19	1e	1f	24	37	3a	3f	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd store (99)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
480028	120058	964	1	0	0	1	0	0	0	0	19	0	8076	1	120045	0	16	4	25	487473	10	248885	240000	10	240000	240000	50	5520170	1931680	0	120024	0	120049	120050	39996	3	40033	480010	20	240000	240000	20	480000	720414	120049	120052	1	1	80021	10	9	10	10	80000	80000	10	240014	14	0	0	1	240016	0	0	17	240002	16	36	14	0	5019	1	17	1	1	120056	55	240000	240000	10	120060	120051	120061	120059	120051
480024	120057	964	1	1	0	0	0	0	0	6	15	0	7200	1	120044	16	16	3	25	485002	10	242136	240000	10	240000	240000	50	5520148	1932619	0	120034	3	120050	120058	39999	3	40033	480010	20	240000	240000	20	480000	720000	120058	120060	1	1	80021	10	9	10	10	80000	80000	10	240014	17	0	0	0	240014	0	0	18	240000	14	36	14	0	5020	1	17	1	1	120047	20	240000	240000	10	120059	120052	120062	120051	120060
480024	120058	964	1	1	0	0	0	0	0	3	21	0	4665	1	120044	16	16	0	25	483916	10	246385	240000	10	240000	240000	50	5520244	1948365	0	120035	0	120048	120059	39996	3	40042	480010	20	240000	240000	20	480000	720000	120050	120058	1	1	80021	10	9	10	10	80000	80000	10	240014	14	40	0	1	240016	0	1	20	240002	14	36	14	0	5019	1	17	1	2	120049	17	240000	240000	10	120051	120060	120053	120050	120052
480024	120052	964	1	1	0	0	0	0	0	3	19	0	11870	1	120037	16	0	0	25	483743	10	246990	240000	10	240000	240000	50	5519812	1947668	0	120033	0	120211	120061	39988	3	40032	480010	20	240000	240000	20	480000	720000	120058	120202	1	1	80021	10	9	10	10	80000	80000	10	240014	14	36	0	0	240016	1	0	23	240002	16	40	14	0	5019	1	26	1	1	120193	18	240000	240000	10	120052	120060	120359	120050	120208
480024	120052	966	1	0	0	0	0	1	0	0	14	0	3348	1	120043	16	16	6	47	487556	10	243997	240000	10	240117	240108	50	5519860	1954287	0	120034	0	120168	120047	39989	7	40041	480235	20	240120	240000	20	480000	720000	120203	120050	1	1	80021	10	9	10	10	80000	80000	10	240074	14	36	0	1	240016	0	0	20	240002	16	36	14	3	5032	1	17	1	1	120058	17	240000	240000	10	120059	120053	120216	120059	120059
480024	120059	966	1	0	0	1	0	3	1	132	109	0	4144	1	120200	16	16	276	92	484277	10	247525	240120	10	240234	240108	50	5526279	1961569	0	120182	0	120057	120205	39988	7	40147	480235	20	240120	240120	20	480000	720720	120047	120358	2	1	80021	10	9	10	10	80000	80000	10	240794	14	43	102	2	240136	0	3	890	240182	14	36	14	3	5058	1	44	1	2	120342	18	240000	240000	10	120051	120052	120214	120051	120051
480024	120147	964	1	1	0	0	0	0	0	0	19	0	6001	1	120037	15	16	0	25	485679	10	245600	240000	10	240000	240000	50	5519764	1957334	0	120035	0	120058	120052	39996	3	40032	480010	20	240000	240000	20	480000	720000	120050	120058	1	1	80021	10	9	10	10	80000	80000	10	240015	14	0	0	0	240016	1	0	18	240062	14	36	14	0	5019	1	17	1	1	120047	17	240000	240000	10	120051	120054	120049	120060	120051
480024	120050	964	1	0	0	0	0	0	0	0	106	0	4905	1	120187	16	0	92	25	482312	10	248265	240060	10	240000	240108	50	5538207	1941206	0	120025	0	120080	120703	39994	3	40021	480010	20	240000	240000	20	480000	720000	120048	120050	1	1	80021	10	9	10	10	80000	80000	10	240014	14	44	0	1	240014	1	0	19	240002	14	0	14	1	5020	1	17	1	1	120047	0	240000	240000	10	120055	120053	120056	120054	120055
480024	120055	964	1	0	1	1	0	0	1	21	17	0	2933	1	120047	16	16	2	25	486671	10	244797	240000	10	240000	240000	50	5519908	1950906	1	120036	0	120050	120052	39991	3	40036	480010	20	240000	240000	20	480000	720000	120210	120053	1	1	80021	10	9	10	10	80000	80000	10	240015	14	44	0	3	240014	1	0	20	240002	16	0	14	1	5020	1	17	1	1	120050	0	240000	240000	10	120053	120210	120051	120052	120052
480024	120208	964	1	0	1	0	0	0	1	12	17	0	6007	1	120047	16	16	1	25	485571	10	244209	240060	10	240000	240000	50	5519764	1959071	0	120185	0	120052	120050	39990	3	40033	480010	20	240000	240000	20	480000	720720	120208	120053	1	1	80021	10	9	10	10	80000	80000	10	240014	15	44	0	2	240014	1	0	20	240002	14	0	14	0	5019	1	17	1	1	120189	0	240000	240000	10	120209	120054	120053	120051	120211

ST3 (multiple, 4S)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations