Apple Microarchitecture Research by Dougall Johnson M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions M1/A14 E-core (Icestorm): Overview | Base Instructions | SIMD and FP Instructions
Code:
st3 { v0.8b, v1.8b, v2.8b }, [x6] nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop
mov x0, 0
(no loop instructions)
Retires (minus 60 nops): 4.000
Issues: 4.000
Integer unit issues: 0.000
Load/store unit issues: 2.000
SIMD/FP unit issues: 2.000
retire uop (01) | cycle (02) | 03 | l1i tlb fill (04) | mmu table walk instruction (07) | l2 tlb miss instruction (0a) | l2 tlb miss data (0b) | 18 | 19 | 1e | 1f | 23 | 24 | 3a | 3f | 46 | 49 | 51 | schedule uop (52) | schedule simd uop (54) | schedule ldst uop (55) | dispatch simd uop (57) | dispatch ldst uop (58) | simd uops in schedulers (5a) | ldst uops in schedulers (5b) | 5f | 69 | 6d | 6e | map rewind (75) | map stall (76) | dispatch uop (78) | map ldst uop (7d) | map simd uop (7e) | map ldst uop inputs (80) | map simd uop inputs (81) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst simd store (99) | inst ldst (9b) | l1d tlb access (a0) | l1d tlb miss (a1) | l1d cache miss st (a2) | st unit uop (a7) | l1d cache writeback (a8) | ac | af | l1d cache miss st nonspec (c0) | cf | d0 | d2 | l1i cache miss demand (d3) | l1i tlb miss demand (d4) | d5 | map dispatch bubble (d6) | d9 | da | db | dd | fetch restart (de) | e0 | ea | eb | ec | ? ldst retires (ed) | ? simd retires (ee) | f5 | f6 | f7 | f8 | fd |
64004 | 29562 | 344 | 1 | 3 | 3 | 0 | 0 | 0 | 9 | 3 | 0 | 1 | 4655 | 28552 | 0 | 0 | 18286 | 4000 | 2000 | 2000 | 2000 | 2000 | 21610 | 16000 | 27 | 21794 | 28921 | 29402 | 3 | 10 | 4000 | 2000 | 2000 | 4000 | 6000 | 29147 | 29212 | 1 | 1 | 61001 | 1000 | 1000 | 2000 | 0 | 6 | 2002 | 65 | 9 | 2000 | 0 | 12878 | 9528 | 6921 | 3093 | 8 | 46 | 20398 | 3196 | 3815 | 15 | 51 | 46 | 28439 | 16044 | 13067 | 14739 | 2000 | 2000 | 29351 | 29366 | 29281 | 29393 | 29245 |
64004 | 29293 | 227 | 0 | 20 | 15 | 0 | 1 | 0 | 3 | 1 | 0 | 0 | 4535 | 29099 | 0 | 0 | 18335 | 4000 | 2000 | 2000 | 2000 | 2000 | 21623 | 16000 | 1 | 21759 | 28949 | 29422 | 3 | 28 | 4000 | 2000 | 2000 | 4000 | 6000 | 29289 | 29112 | 1 | 1 | 61001 | 1000 | 1000 | 2000 | 0 | 0 | 2000 | 65 | 3 | 2000 | 0 | 13161 | 9238 | 6846 | 3082 | 5 | 47 | 20386 | 3300 | 3815 | 11 | 50 | 52 | 28612 | 16321 | 13157 | 15071 | 2000 | 2000 | 29295 | 29426 | 29315 | 29400 | 29366 |
64004 | 29486 | 228 | 0 | 16 | 24 | 0 | 0 | 0 | 132 | 1 | 1 | 0 | 4675 | 29039 | 0 | 0 | 18246 | 4000 | 2000 | 2000 | 2000 | 2000 | 21612 | 16000 | 9 | 21798 | 28887 | 29305 | 3 | 10 | 4000 | 2000 | 2000 | 4000 | 6000 | 29227 | 29283 | 2 | 1 | 61001 | 1000 | 1000 | 2000 | 0 | 4 | 2000 | 76 | 3 | 2000 | 4 | 13374 | 9210 | 6904 | 3169 | 6 | 50 | 20253 | 3262 | 3813 | 13 | 47 | 41 | 28578 | 15964 | 13170 | 14809 | 2000 | 2000 | 29329 | 29292 | 29145 | 29401 | 29407 |
64004 | 29333 | 228 | 0 | 16 | 14 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 4727 | 29037 | 0 | 0 | 18153 | 4000 | 2000 | 2000 | 2000 | 2000 | 21617 | 16000 | 5 | 21779 | 28853 | 29242 | 3 | 10 | 4000 | 2000 | 2000 | 4000 | 6000 | 29287 | 29144 | 1 | 1 | 61001 | 1000 | 1000 | 2000 | 0 | 0 | 2000 | 61 | 6 | 2000 | 4 | 12832 | 9162 | 6850 | 3016 | 9 | 51 | 20341 | 3329 | 3815 | 14 | 47 | 48 | 28578 | 16300 | 13369 | 14675 | 2000 | 2000 | 29292 | 29397 | 29231 | 29344 | 29455 |
64004 | 29345 | 228 | 0 | 16 | 20 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4559 | 28975 | 0 | 2 | 18174 | 4000 | 2000 | 2000 | 2000 | 2000 | 21619 | 16000 | 1 | 21828 | 28944 | 29245 | 3 | 10 | 4000 | 2000 | 2000 | 4000 | 6000 | 29182 | 29106 | 1 | 1 | 61001 | 1000 | 1000 | 2000 | 0 | 0 | 2000 | 2 | 0 | 2000 | 4 | 12996 | 9277 | 6885 | 3171 | 11 | 50 | 20342 | 3258 | 3808 | 15 | 54 | 47 | 28533 | 16137 | 13125 | 14583 | 2000 | 2000 | 29680 | 29525 | 29883 | 29569 | 29459 |
64004 | 29401 | 238 | 0 | 21 | 17 | 0 | 0 | 0 | 45 | 105 | 0 | 0 | 4723 | 29252 | 0 | 0 | 18393 | 4000 | 2000 | 2000 | 2000 | 2000 | 21600 | 16000 | 0 | 21861 | 29162 | 29451 | 3 | 10 | 4000 | 2000 | 2000 | 4000 | 6000 | 28871 | 28979 | 1 | 1 | 61001 | 1000 | 1000 | 2000 | 0 | 6 | 2002 | 3 | 0 | 2002 | 0 | 13046 | 9516 | 6982 | 3157 | 9 | 49 | 19691 | 3239 | 3807 | 21 | 49 | 49 | 28338 | 15174 | 12393 | 14053 | 2000 | 2000 | 28691 | 28749 | 28849 | 28647 | 28685 |
64004 | 28597 | 221 | 0 | 16 | 14 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 4787 | 28514 | 2 | 2 | 17727 | 4000 | 2000 | 2000 | 2000 | 2000 | 21612 | 16000 | 21 | 21777 | 28497 | 28823 | 3 | 10 | 4000 | 2000 | 2000 | 4000 | 6000 | 28843 | 28773 | 1 | 1 | 61001 | 1000 | 1000 | 2000 | 0 | 6 | 2000 | 0 | 2 | 2000 | 4 | 13271 | 9319 | 6899 | 3080 | 4 | 46 | 19837 | 3242 | 3818 | 10 | 52 | 49 | 28241 | 15702 | 12716 | 14416 | 2000 | 2000 | 28839 | 28894 | 28916 | 28905 | 28763 |
64004 | 28751 | 232 | 0 | 16 | 21 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 4630 | 28682 | 2 | 2 | 17859 | 4000 | 2000 | 2000 | 2000 | 2000 | 21628 | 16000 | 10 | 21760 | 28651 | 28886 | 3 | 10 | 4000 | 2000 | 2000 | 4004 | 6000 | 28943 | 28936 | 2 | 1 | 61001 | 1000 | 1000 | 2000 | 0 | 4 | 2000 | 0 | 0 | 2000 | 0 | 13330 | 9471 | 6883 | 3138 | 6 | 50 | 19764 | 3226 | 3807 | 20 | 45 | 46 | 28242 | 15173 | 12618 | 14159 | 2000 | 2000 | 28743 | 28666 | 28742 | 28802 | 28785 |
64004 | 28817 | 223 | 0 | 22 | 18 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 4688 | 28759 | 2 | 2 | 17671 | 4000 | 2000 | 2000 | 2000 | 2000 | 21611 | 16000 | 10 | 21770 | 28506 | 28678 | 3 | 10 | 4000 | 2000 | 2000 | 4000 | 6000 | 28786 | 28671 | 1 | 1 | 61001 | 1000 | 1000 | 2000 | 0 | 4 | 2000 | 3 | 0 | 2002 | 4 | 13213 | 9212 | 6971 | 3130 | 11 | 46 | 19796 | 3257 | 3808 | 18 | 48 | 53 | 28251 | 15462 | 12506 | 14152 | 2000 | 2000 | 28668 | 28875 | 28743 | 28792 | 28736 |
64004 | 28740 | 222 | 0 | 19 | 18 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 4665 | 28608 | 0 | 0 | 17666 | 4000 | 2000 | 2000 | 2000 | 2000 | 21625 | 16000 | 8 | 21786 | 28542 | 28853 | 3 | 10 | 4000 | 2000 | 2000 | 4000 | 6000 | 28726 | 28754 | 1 | 1 | 61001 | 1000 | 1000 | 2000 | 0 | 4 | 2000 | 0 | 0 | 2000 | 4 | 13203 | 9461 | 6931 | 3134 | 10 | 45 | 19777 | 3197 | 3813 | 10 | 49 | 55 | 28241 | 15762 | 12537 | 14379 | 2000 | 2000 | 28889 | 28882 | 28761 | 28791 | 28750 |
Count: 8
Code:
st3 { v0.8b, v1.8b, v2.8b }, [x6] st3 { v0.8b, v1.8b, v2.8b }, [x6] st3 { v0.8b, v1.8b, v2.8b }, [x6] st3 { v0.8b, v1.8b, v2.8b }, [x6] st3 { v0.8b, v1.8b, v2.8b }, [x6] st3 { v0.8b, v1.8b, v2.8b }, [x6] st3 { v0.8b, v1.8b, v2.8b }, [x6] st3 { v0.8b, v1.8b, v2.8b }, [x6]
mov x7, x6 mov x8, x6 mov x9, x6 mov x10, x6 mov x11, x6 mov x12, x6 mov x13, x6
(fused SUBS/B.cc loop)
Result (median cycles for code divided by count): 1.0007
retire uop (01) | cycle (02) | 03 | l1d tlb fill (05) | mmu table walk data (08) | 09 | l2 tlb miss data (0b) | 18 | 19 | 1e | 1f | 22 | 24 | 37 | 3a | 3f | 46 | 49 | 4f | 51 | schedule uop (52) | schedule int uop (53) | schedule simd uop (54) | schedule ldst uop (55) | dispatch int uop (56) | dispatch simd uop (57) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | ldst uops in schedulers (5b) | 69 | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map simd uop (7e) | map int uop inputs (7f) | map ldst uop inputs (80) | map simd uop inputs (81) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int alu (97) | inst simd store (99) | inst ldst (9b) | 9f | l1d tlb access (a0) | l1d tlb miss (a1) | l1d cache miss st (a2) | a4 | ld unit uop (a6) | st unit uop (a7) | l1d cache writeback (a8) | a9 | ac | af | bc | l1d cache miss st nonspec (c0) | l1d tlb miss nonspec (c1) | c2 | branch cond mispred nonspec (c5) | branch mispred nonspec (cb) | cf | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ? ldst retires (ed) | ? simd retires (ee) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
320207 | 80235 | 623 | 1 | 0 | 0 | 0 | 14 | 13 | 138 | 195 | 1 | 0 | 6170 | 1 | 80378 | 16 | 16 | 193 | 71 | 324845 | 100 | 166424 | 160060 | 102 | 160236 | 160108 | 500 | 2508131 | 1303974 | 80185 | 80381 | 80217 | 179 | 13 | 133 | 320326 | 200 | 160240 | 160120 | 200 | 320480 | 480720 | 80217 | 80221 | 4 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 160000 | 14 | 0 | 0 | 1 | 160016 | 0 | 0 | 20 | 160002 | 16 | 36 | 14 | 0 | 0 | 0 | 5109 | 1 | 17 | 1 | 1 | 80046 | 160000 | 160000 | 100 | 80052 | 80051 | 80060 | 80045 | 80049 |
320204 | 80060 | 620 | 1 | 1 | 0 | 0 | 0 | 0 | 12 | 14 | 1 | 0 | 2668 | 1 | 80035 | 16 | 16 | 0 | 25 | 325405 | 100 | 165010 | 160000 | 100 | 160000 | 160000 | 500 | 2639847 | 1297817 | 80035 | 80050 | 80058 | 0 | 3 | 41 | 320100 | 200 | 160000 | 160000 | 200 | 320000 | 480000 | 80057 | 80058 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 160014 | 0 | 42 | 0 | 0 | 160016 | 1 | 0 | 20 | 160002 | 16 | 0 | 0 | 0 | 0 | 0 | 5109 | 1 | 17 | 1 | 1 | 80048 | 160000 | 160000 | 100 | 80052 | 80059 | 80051 | 80059 | 80051 |
320204 | 80045 | 620 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 9 | 1 | 0 | 5019 | 0 | 80035 | 16 | 16 | 0 | 25 | 325236 | 100 | 160005 | 160000 | 100 | 160000 | 160000 | 500 | 2079378 | 1284018 | 80025 | 80058 | 80060 | 0 | 3 | 3108 | 320100 | 200 | 160000 | 160000 | 200 | 320000 | 480000 | 80045 | 80050 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 160015 | 15 | 34 | 0 | 0 | 160016 | 0 | 0 | 19 | 160002 | 14 | 36 | 14 | 0 | 0 | 0 | 5109 | 1 | 17 | 1 | 1 | 80046 | 160000 | 160000 | 100 | 80052 | 80059 | 80060 | 80051 | 80059 |
320204 | 80060 | 620 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 17 | 1 | 0 | 3575 | 1 | 80044 | 16 | 16 | 0 | 25 | 323837 | 100 | 164307 | 160000 | 100 | 160000 | 160000 | 500 | 2399889 | 1293719 | 80033 | 80058 | 80058 | 0 | 3 | 42 | 320100 | 200 | 160000 | 160000 | 200 | 320000 | 480000 | 80048 | 80045 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 160000 | 15 | 0 | 0 | 0 | 160016 | 0 | 1 | 17 | 160002 | 14 | 36 | 14 | 1 | 0 | 0 | 5109 | 1 | 17 | 1 | 1 | 80041 | 160000 | 160000 | 100 | 80059 | 80060 | 80053 | 80059 | 80052 |
320204 | 80050 | 621 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 17 | 0 | 0 | 4547 | 1 | 80043 | 16 | 16 | 0 | 25 | 326100 | 100 | 165339 | 160000 | 100 | 160000 | 160000 | 500 | 2319887 | 1299951 | 80025 | 80058 | 80058 | 0 | 3 | 32 | 320100 | 200 | 160000 | 160000 | 200 | 320000 | 480000 | 80060 | 80058 | 2 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 160015 | 0 | 34 | 0 | 1 | 160016 | 0 | 0 | 17 | 160002 | 2 | 36 | 0 | 0 | 0 | 0 | 5109 | 3 | 35 | 1 | 1 | 80055 | 160000 | 160000 | 100 | 80438 | 80231 | 80059 | 80050 | 80051 |
320204 | 80045 | 620 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 19 | 1 | 0 | 4215 | 1 | 80035 | 16 | 16 | 0 | 25 | 326574 | 100 | 162915 | 160000 | 100 | 160000 | 160000 | 500 | 2319899 | 1298031 | 80025 | 80058 | 80050 | 0 | 3 | 30 | 320100 | 200 | 160000 | 160000 | 200 | 320000 | 480000 | 80049 | 80059 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 160015 | 14 | 34 | 1 | 0 | 160016 | 0 | 0 | 18 | 160002 | 16 | 36 | 14 | 0 | 0 | 0 | 5109 | 1 | 17 | 1 | 1 | 80047 | 160000 | 160000 | 100 | 80053 | 80060 | 80049 | 80051 | 80050 |
320204 | 80060 | 621 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 14 | 1 | 0 | 4707 | 1 | 80044 | 16 | 16 | 0 | 25 | 325790 | 100 | 164226 | 160000 | 100 | 160000 | 160000 | 500 | 2479879 | 1296940 | 80033 | 80050 | 80060 | 0 | 3 | 49 | 320100 | 200 | 160000 | 160000 | 200 | 320000 | 480000 | 80059 | 80049 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 160015 | 14 | 36 | 0 | 0 | 160016 | 0 | 1 | 21 | 160002 | 16 | 36 | 14 | 0 | 0 | 0 | 5109 | 1 | 17 | 1 | 1 | 80048 | 160000 | 160000 | 100 | 80051 | 80059 | 80051 | 80051 | 80050 |
320204 | 80059 | 620 | 1 | 0 | 0 | 1 | 0 | 0 | 12 | 3 | 1 | 0 | 3636 | 1 | 80033 | 16 | 0 | 0 | 25 | 325364 | 100 | 163816 | 160000 | 100 | 160000 | 160000 | 500 | 3679144 | 1307417 | 80033 | 80050 | 80058 | 0 | 3 | 40 | 320100 | 200 | 160000 | 160000 | 200 | 320000 | 480000 | 80058 | 80057 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 160015 | 15 | 36 | 0 | 0 | 160002 | 0 | 1 | 21 | 160000 | 16 | 36 | 14 | 1 | 0 | 0 | 5109 | 1 | 17 | 1 | 1 | 80047 | 160000 | 160000 | 100 | 80052 | 80059 | 80045 | 80059 | 80050 |
320204 | 80049 | 620 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 14 | 1 | 0 | 5641 | 1 | 80044 | 16 | 16 | 0 | 25 | 323225 | 100 | 165072 | 160000 | 100 | 160000 | 160000 | 500 | 2559868 | 1307287 | 80035 | 80050 | 80058 | 0 | 3 | 31 | 320100 | 200 | 160000 | 160000 | 200 | 320000 | 480000 | 80051 | 80059 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 160014 | 15 | 42 | 2 | 0 | 160014 | 0 | 0 | 18 | 160002 | 16 | 0 | 14 | 0 | 0 | 0 | 5109 | 1 | 17 | 1 | 1 | 80046 | 160000 | 160000 | 100 | 80046 | 80059 | 80060 | 80045 | 80059 |
320204 | 80060 | 621 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 20 | 1 | 0 | 3832 | 1 | 80035 | 0 | 16 | 0 | 25 | 324843 | 100 | 164504 | 160000 | 100 | 160000 | 160000 | 500 | 2399920 | 1283686 | 80024 | 80060 | 80047 | 0 | 3 | 26 | 320100 | 200 | 160000 | 160000 | 200 | 320000 | 480000 | 80050 | 80050 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 160015 | 14 | 36 | 0 | 0 | 160016 | 1 | 0 | 18 | 160002 | 16 | 36 | 14 | 0 | 0 | 0 | 5109 | 1 | 17 | 1 | 1 | 80055 | 160000 | 160000 | 100 | 80051 | 80047 | 80053 | 80059 | 80051 |
Result (median cycles for code divided by count): 1.0006
retire uop (01) | cycle (02) | 03 | mmu table walk data (08) | l2 tlb miss data (0b) | 18 | 19 | 1e | 1f | 22 | 23 | 24 | 37 | 3f | 46 | 49 | 4f | 51 | schedule uop (52) | schedule int uop (53) | schedule simd uop (54) | schedule ldst uop (55) | dispatch int uop (56) | dispatch simd uop (57) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | ldst uops in schedulers (5b) | 60 | 61 | 69 | 6b | 6d | 6e | map stall dispatch (70) | flags prf full (73) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map simd uop (7e) | map int uop inputs (7f) | map ldst uop inputs (80) | map simd uop inputs (81) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int alu (97) | inst simd store (99) | inst ldst (9b) | 9f | l1d tlb access (a0) | l1d tlb miss (a1) | l1d cache miss st (a2) | a4 | ld unit uop (a6) | st unit uop (a7) | l1d cache writeback (a8) | a9 | ac | af | bc | l1d cache miss st nonspec (c0) | c2 | cf | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ? ldst retires (ed) | ? simd retires (ee) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
320027 | 80072 | 620 | 0 | 0 | 0 | 0 | 6 | 3 | 0 | 0 | 0 | 4556 | 80029 | 16 | 0 | 0 | 25 | 325020 | 10 | 164149 | 160000 | 10 | 160000 | 160000 | 50 | 2149985 | 1316974 | 0 | 0 | 80023 | 0 | 80045 | 80044 | 0 | 0 | 3 | 27 | 320010 | 20 | 160000 | 160000 | 20 | 320000 | 480000 | 80048 | 80048 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 160000 | 0 | 34 | 0 | 0 | 160000 | 1 | 0 | 912 | 160002 | 0 | 34 | 0 | 5019 | 3 | 17 | 4 | 3 | 80042 | 160000 | 160000 | 10 | 80046 | 80211 | 80046 | 80045 | 80045 |
320024 | 80049 | 620 | 0 | 0 | 0 | 0 | 6 | 3 | 0 | 0 | 0 | 6328 | 80034 | 0 | 16 | 0 | 25 | 324068 | 10 | 164646 | 160000 | 10 | 160000 | 160000 | 50 | 2239770 | 1302651 | 0 | 0 | 80024 | 0 | 80048 | 80044 | 0 | 0 | 3 | 31 | 320010 | 20 | 160000 | 160000 | 20 | 320000 | 480000 | 80045 | 80045 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 160000 | 0 | 34 | 0 | 0 | 160000 | 0 | 0 | 2 | 160000 | 2 | 0 | 0 | 5019 | 3 | 17 | 3 | 4 | 80387 | 160000 | 160000 | 10 | 80046 | 80046 | 80050 | 80046 | 80045 |
320024 | 80044 | 620 | 1 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | 3934 | 80034 | 16 | 16 | 0 | 25 | 326563 | 10 | 164599 | 160000 | 10 | 160000 | 160000 | 50 | 2158255 | 1295497 | 0 | 0 | 80024 | 0 | 80044 | 80043 | 0 | 0 | 3 | 26 | 320010 | 20 | 160000 | 160000 | 20 | 320000 | 480000 | 80045 | 82028 | 29 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 160000 | 0 | 34 | 0 | 0 | 160000 | 0 | 0 | 2 | 160004 | 2 | 0 | 0 | 5019 | 3 | 17 | 3 | 3 | 80042 | 160000 | 160000 | 10 | 80046 | 80045 | 80045 | 80045 | 80213 |
320024 | 80044 | 620 | 0 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | 4802 | 80030 | 16 | 16 | 0 | 25 | 324006 | 10 | 164768 | 160000 | 10 | 160000 | 160000 | 50 | 2239742 | 1295040 | 0 | 0 | 80025 | 0 | 80045 | 80045 | 0 | 0 | 3 | 31 | 320010 | 20 | 160000 | 160000 | 20 | 320000 | 480000 | 80045 | 80045 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 160000 | 0 | 34 | 0 | 0 | 160002 | 0 | 0 | 0 | 160002 | 2 | 0 | 0 | 5019 | 3 | 17 | 3 | 3 | 80042 | 160000 | 160000 | 10 | 80045 | 80045 | 80045 | 80050 | 80045 |
320024 | 80046 | 621 | 0 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | 6251 | 80030 | 0 | 16 | 0 | 25 | 324420 | 10 | 166251 | 160000 | 10 | 160118 | 160000 | 50 | 2079107 | 1290369 | 0 | 0 | 80024 | 0 | 80044 | 80045 | 89 | 0 | 3 | 26 | 320010 | 20 | 160000 | 160000 | 20 | 320000 | 480000 | 80044 | 80045 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 160060 | 0 | 34 | 0 | 0 | 160002 | 0 | 0 | 2 | 160002 | 2 | 34 | 0 | 5019 | 3 | 17 | 3 | 3 | 80042 | 160000 | 160000 | 10 | 80046 | 80046 | 80050 | 80045 | 80045 |
320024 | 80044 | 620 | 0 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | 4502 | 80030 | 16 | 16 | 0 | 25 | 324348 | 10 | 165121 | 160000 | 10 | 160000 | 160000 | 50 | 2079395 | 1294973 | 0 | 0 | 80024 | 0 | 80046 | 80044 | 0 | 0 | 3 | 26 | 320010 | 20 | 160000 | 160000 | 20 | 320000 | 480000 | 80049 | 80044 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 160000 | 0 | 34 | 0 | 0 | 160002 | 0 | 0 | 5 | 160000 | 0 | 0 | 0 | 5019 | 3 | 17 | 3 | 3 | 80046 | 160000 | 160000 | 10 | 80046 | 80045 | 80049 | 80045 | 80045 |
320024 | 80044 | 621 | 0 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | 3960 | 80034 | 0 | 0 | 0 | 25 | 324199 | 10 | 163996 | 160000 | 10 | 160118 | 160000 | 50 | 2217011 | 1310680 | 0 | 0 | 80023 | 0 | 80045 | 80043 | 0 | 0 | 3 | 26 | 320010 | 20 | 160000 | 160000 | 20 | 320000 | 480000 | 80049 | 80049 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 160000 | 0 | 34 | 0 | 0 | 160000 | 1 | 0 | 8 | 160002 | 2 | 34 | 0 | 5019 | 3 | 17 | 3 | 3 | 80046 | 160000 | 160000 | 10 | 80045 | 80050 | 80045 | 80045 | 80044 |
320024 | 80044 | 620 | 0 | 0 | 0 | 1 | 0 | 3 | 0 | 0 | 0 | 5847 | 80031 | 16 | 16 | 0 | 25 | 324358 | 10 | 167562 | 160000 | 10 | 160000 | 160000 | 50 | 2078935 | 1300508 | 0 | 0 | 80025 | 0 | 80045 | 80044 | 0 | 0 | 3 | 26 | 320010 | 20 | 160000 | 160000 | 20 | 320000 | 480000 | 80044 | 80045 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 160000 | 0 | 34 | 0 | 0 | 160002 | 0 | 0 | 2 | 160002 | 2 | 34 | 2 | 5019 | 3 | 17 | 9 | 3 | 80041 | 160000 | 160000 | 10 | 80045 | 80046 | 80212 | 80046 | 80044 |
320024 | 80049 | 620 | 0 | 0 | 0 | 0 | 3 | 3 | 0 | 0 | 0 | 4265 | 80035 | 16 | 16 | 0 | 25 | 325734 | 10 | 162643 | 160000 | 10 | 160000 | 160000 | 50 | 2169115 | 1296549 | 0 | 0 | 80023 | 0 | 80045 | 80045 | 0 | 0 | 3 | 27 | 320010 | 20 | 160000 | 160000 | 20 | 320000 | 480000 | 80044 | 80044 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 160000 | 0 | 34 | 0 | 0 | 160002 | 0 | 0 | 2 | 160000 | 2 | 34 | 0 | 5019 | 2 | 17 | 3 | 3 | 80041 | 160000 | 160000 | 10 | 80046 | 80050 | 80046 | 80046 | 80044 |
320024 | 80049 | 621 | 0 | 0 | 0 | 0 | 132 | 3 | 0 | 0 | 0 | 5121 | 80030 | 16 | 16 | 0 | 25 | 324289 | 10 | 166053 | 160000 | 10 | 160000 | 160000 | 50 | 2158439 | 1296387 | 0 | 0 | 80023 | 0 | 80044 | 80048 | 0 | 0 | 3 | 26 | 320268 | 20 | 160120 | 160000 | 20 | 320000 | 480000 | 80045 | 80049 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 160000 | 0 | 34 | 0 | 0 | 160000 | 0 | 0 | 20 | 160062 | 2 | 0 | 0 | 5019 | 3 | 17 | 2 | 3 | 80041 | 160000 | 160000 | 10 | 80046 | 80050 | 80208 | 80045 | 80049 |