Firestorm: ST3 (multiple, 8H) measurements

Code:

  st3 { v0.8h, v1.8h, v2.8h }, [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 6.000

Issues: 6.000

Integer unit issues: 0.000

Load/store unit issues: 3.000

SIMD/FP unit issues: 3.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	1f	22	24	37	3a	3f	51	schedule uop (52)	schedule simd uop (54)	schedule ldst uop (55)	dispatch simd uop (57)	dispatch ldst uop (58)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	5f	61	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd store (99)	inst ldst (9b)	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	st unit uop (a7)	l1d cache writeback (a8)	ac	af	l1d cache miss st nonspec (c0)	c2	cf	d0	d2	l1i cache miss demand (d3)	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	f5	f6	f7	f8	fd
66008	29283	228	24	0	0	31	0	0	0	0	0	0	0	0	4666	29256	17248	6000	3000	3000	3000	3000	33022	24000	8	0	22759	29010	29242	3	10	6000	3000	3000	6000	9000	29320	29409	1	1	61001	1000	1000	3000	0	0	3000	0	0	3000	6	0	12964	9300	6875	3115	14	49	19951	3210	3811	14	55	57	28569	16350	12616	14188	3000	3000	29292	29313	29394	29305	29406
66004	29369	227	21	0	0	23	0	0	0	0	1	0	0	0	4789	29182	17135	6000	3000	3000	3000	3000	33032	24000	9	0	22784	29022	29377	3	10	6000	3000	3000	6000	9000	29233	29215	1	1	61001	1000	1000	3000	0	6	3000	0	0	3000	6	0	13174	9280	6942	3055	14	52	20035	3193	3807	12	50	51	28692	16230	12593	14976	3000	3000	29436	29286	29331	29337	29349
66004	29377	227	21	0	0	17	0	0	0	0	1	0	0	0	4628	29195	17179	6000	4628	3000	3000	3000	33024	24000	3	0	22776	28964	29318	3	10	6000	3000	3000	6000	9000	29257	29342	1	1	61001	1000	1000	3000	0	6	3000	0	0	3000	0	0	13354	9232	6898	3049	11	49	20144	3186	3815	8	48	51	28644	16022	12767	14579	3000	3000	29370	29366	29330	29395	29171
66004	29342	227	25	0	0	23	0	0	0	0	1	0	0	0	4690	29280	17271	6000	3000	3000	3000	3000	33066	24000	4	8	22757	28946	29370	3	28	6000	3000	3000	6000	9000	29250	29322	1	1	61001	1000	1000	3000	0	0	3000	0	0	3000	6	0	13020	9267	6912	3156	11	57	20146	3188	3812	12	53	58	28703	16222	12942	14694	3000	3000	29272	29247	29341	29214	29301
66004	29502	228	24	0	0	25	0	0	0	0	0	0	0	0	4581	29270	17133	6000	3000	3000	3000	3000	33030	24000	6	0	22729	29011	29299	3	10	6000	3000	3000	6000	9000	29332	29193	1	1	61001	1000	1000	3000	0	6	3000	0	0	3000	6	0	13010	9281	6915	3126	14	46	20068	3224	3810	16	48	47	28663	16096	12704	14856	3000	3000	29369	29385	29353	29386	29393
66004	29370	236	26	0	0	22	0	0	0	0	0	0	0	0	4760	29225	17283	6000	3000	3000	3000	3000	33039	24000	5	0	22777	29018	29422	3	10	6000	3000	3000	6000	9000	29394	29277	1	1	61001	1000	1000	3000	0	6	3000	0	0	3003	6	0	12957	9260	6859	3097	13	50	20196	3244	3816	11	61	48	28605	16229	12766	14645	3000	3000	29427	29380	29248	29376	29427
66004	29264	227	19	0	0	19	0	0	0	0	89	0	0	0	4553	29213	17095	7625	3000	3000	3000	3000	33027	28821	0	0	22780	28999	29353	3	10	6000	3000	3000	6000	9000	29292	29414	1	1	61001	1000	1000	3000	0	6	3000	1	0	3000	3	0	12943	9227	6867	3148	12	49	20093	3259	3807	9	57	52	28675	16172	12900	14842	3000	3000	29319	29284	29327	29349	29251
66004	29336	227	27	0	0	20	0	0	0	0	1	0	0	0	4575	29307	17242	6000	3000	3000	3000	3000	33056	24000	5	0	22730	29096	29290	3	10	6000	3000	3000	6000	9000	29285	29410	1	1	61001	1000	1000	3000	0	0	3000	0	0	3000	6	0	13056	9231	6874	3080	11	60	20205	3214	3809	11	56	55	28569	16100	12814	14821	3000	3000	29148	29365	29294	29243	29293
66004	29278	226	24	0	0	23	0	0	0	0	0	0	0	0	4672	29231	17211	6000	3000	3000	3000	3000	33063	24000	0	0	22694	29027	29440	3	10	6000	3000	3000	6000	9000	29386	29412	1	1	61001	1000	1000	3000	0	6	3000	0	0	3000	6	0	12926	9244	6885	3098	13	48	20210	3114	3816	16	48	50	28751	16420	12715	14754	3000	3000	29427	29304	29091	29365	29357
66004	29247	227	24	0	0	26	0	0	0	6	0	1	0	0	4745	29217	17342	6000	3000	3000	3000	3000	33027	28827	0	0	22781	29086	29276	3	10	6000	3000	3000	6000	9000	29407	29238	1	1	61001	1000	1000	3000	0	0	3000	1	0	3000	6	0	13014	9170	6930	3116	6	47	20193	3182	3808	14	50	47	28634	15981	12617	14768	3000	3000	29395	29280	29389	29291	29355

Count: 8

Code:

  st3 { v0.8h, v1.8h, v2.8h }, [x6]
  st3 { v0.8h, v1.8h, v2.8h }, [x6]
  st3 { v0.8h, v1.8h, v2.8h }, [x6]
  st3 { v0.8h, v1.8h, v2.8h }, [x6]
  st3 { v0.8h, v1.8h, v2.8h }, [x6]
  st3 { v0.8h, v1.8h, v2.8h }, [x6]
  st3 { v0.8h, v1.8h, v2.8h }, [x6]
  st3 { v0.8h, v1.8h, v2.8h }, [x6]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.5007

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	1f	22	23	24	37	3a	3f	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd store (99)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	branch cond mispred nonspec (c5)	cd	cf	d5	map dispatch bubble (d6)	db	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
480208	120053	930	1	0	0	0	1	0	0	0	19	0	0	0	5075	1	120048	16	16	1	25	487164	100	241337	240000	100	240000	240000	500	5519835	1975036	0	120028	120053	120054	39990	3	40034	480100	200	240000	240000	200	480000	720000	120051	120053	1	1	80201	100	99	100	100	80000	80000	100	240014	15	44	0	2	240016	0	1	16	240002	16	44	14	1	0	0	5110	3	17	0	3	5	120192	0	240000	240000	100	120359	120208	120520	120203	120208
480204	120206	934	1	0	2	0	0	3	1	420	105	0	0	0	4388	1	120503	16	16	182	71	482492	100	244286	240180	102	243159	242916	522	5682936	1969628	0	120458	120210	120665	40351	10	40350	480775	200	240360	240240	202	480480	721080	120369	120511	4	1	80201	100	99	100	100	80000	80000	100	240437	14	44	152	3	240136	0	0	2611	240002	14	44	14	1	0	0	5109	2	17	0	3	5	120051	0	240000	240000	100	120054	120052	120053	120054	120055
480204	120052	930	1	0	0	0	1	0	0	0	18	0	0	0	5194	1	120036	0	16	0	25	485707	100	243339	240000	100	240000	240000	500	5519927	1935330	0	120028	120051	120054	39991	3	40033	480100	200	240000	240000	200	480000	720000	120049	120053	1	1	80201	100	99	100	100	80000	80000	100	240014	14	44	0	1	240016	0	0	17	240002	16	0	14	0	0	0	5109	3	17	0	3	3	120048	0	240000	240000	100	120054	120053	120053	120055	120054
480204	120054	931	1	0	1	0	0	0	0	12	17	0	0	0	6791	1	120038	16	16	0	25	486002	100	243110	240000	100	240000	240000	500	5520340	1927334	0	120026	120052	120050	39992	3	40033	480100	200	240000	240000	200	480000	720000	120053	120052	1	1	80201	100	99	100	100	80000	80000	100	240014	14	44	0	0	240016	0	1	18	240002	16	44	14	0	0	0	5110	4	17	0	3	3	120045	0	240000	240000	100	120052	120063	120055	120054	120054
480204	120054	931	1	0	1	0	1	0	0	12	17	0	0	0	5003	1	120039	16	16	0	25	484765	100	249186	240000	100	240000	240000	500	5519810	1940569	0	120023	120052	120050	39990	3	40034	480100	200	240000	240000	200	480000	720000	120053	120063	1	1	80201	100	99	100	100	80000	80000	100	240015	14	44	0	0	240016	0	0	17	240000	16	44	14	1	0	0	5109	3	17	0	3	3	120048	0	240000	240000	100	120054	120053	120054	120054	120055
480204	120053	930	1	0	0	0	0	0	0	0	20	0	0	0	7197	1	120040	16	16	7	25	483101	100	245066	240000	100	240000	240000	500	5519908	1932002	0	120028	120054	120051	39991	3	40035	480100	200	240000	240000	200	480000	720000	120052	120053	1	1	80201	100	99	100	100	80000	80000	100	240014	14	44	0	0	240016	0	1	16	240002	16	44	14	0	0	0	5109	3	17	0	3	3	120051	0	240000	240000	100	120055	120054	120053	120054	120055
480204	120055	931	1	0	0	0	0	0	0	0	17	0	0	0	5334	1	120047	16	16	1	25	484896	100	247200	240000	100	240000	240000	500	5519932	1947647	0	120027	120052	120053	39992	3	40044	480100	200	240000	240000	200	480000	720000	120051	120054	1	1	80201	100	99	100	100	80000	80000	100	240254	15	44	0	0	240016	0	0	17	240002	16	44	14	0	0	0	5110	5	17	0	2	3	120049	0	240000	240000	100	120052	120054	120054	120052	120052
480204	120051	931	1	0	0	0	0	0	0	21	21	0	0	0	6800	1	120039	16	16	1	25	486765	100	245329	240000	100	240000	240000	500	5519884	1937471	0	120027	120062	120052	39991	3	40036	480100	200	240000	240000	200	480000	720000	120051	120053	1	1	80201	100	99	100	100	80000	80000	100	240014	14	44	0	1	240014	1	0	21	240002	16	44	14	0	0	0	5109	3	17	0	2	3	120048	0	240000	240000	100	120054	120048	120053	120055	120054
480204	120054	931	1	0	0	0	0	0	0	0	14	0	0	0	6400	1	120035	16	16	1	25	487022	100	249053	240000	100	240000	240000	500	5519932	1940330	0	120037	120062	120060	39991	3	40034	480100	200	240000	240000	200	480000	720000	120051	120053	1	1	80201	100	99	100	100	80000	80000	100	240015	14	44	0	0	240016	1	1	18	240002	16	44	14	1	0	0	5109	3	17	0	3	3	120051	0	240000	240000	100	120063	120055	120052	120054	120063
480204	120052	930	1	0	0	0	0	0	0	0	18	0	0	0	6800	1	120032	16	16	1	25	483321	100	242677	240000	100	240000	240000	500	5520340	1954393	0	120027	120051	120053	39992	3	40044	480100	200	240000	240000	200	480000	720000	120053	120054	1	1	80201	100	99	100	100	80000	80000	100	240014	14	46	0	0	240014	0	1	17	240002	14	44	14	0	0	0	5109	3	17	0	2	3	145134	0	240000	240000	100	120052	120064	120055	120053	120052

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.5005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	1f	22	23	24	37	3a	3f	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	5e	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd store (99)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
480028	120050	930	0	0	0	0	0	0	1011	9	1	0	0	5469	1	120027	16	16	0	25	488581	10	246659	240000	10	240117	240000	50	5519567	1950691	1	0	120021	120043	120042	39986	3	40042	480010	20	240000	240000	20	480000	720000	120042	120042	1	1	80021	10	9	10	10	80000	80000	10	240000	0	34	0	0	240002	0	0	8	240002	2	34	0	5020	7	17	7	14	121039	240000	240000	10	120199	120050	120043	120043	120050
480024	120049	930	0	0	0	0	0	0	0	0	1	0	0	2707	0	120027	0	16	41	25	485032	10	247334	240000	10	240000	240108	50	5519567	1948101	0	0	120169	120049	120043	39984	3	40034	480010	20	240000	240000	20	480000	720000	120042	120048	1	1	80021	10	9	10	10	80000	80000	10	240000	0	34	0	0	240002	1	0	0	240002	2	0	0	5020	7	17	8	8	120039	240000	240000	10	120050	120043	120043	120050	120043
480024	120043	930	0	0	0	0	0	0	12	0	0	0	0	8864	0	120118	16	16	0	25	484707	10	244557	240000	10	240000	240000	50	5519567	1965563	0	0	120021	120042	120049	39987	3	40025	480010	20	240000	240000	20	480000	720000	120198	120042	1	1	80021	10	9	10	10	80000	80000	10	240060	0	38	0	3	240002	1	0	5	240002	0	34	0	5020	7	17	8	8	120039	240000	240000	10	120043	120043	120133	120050	120043
480024	120042	930	0	0	0	0	0	0	132	0	0	0	0	2846	0	120027	16	16	0	25	488676	10	244763	240000	10	240000	240000	50	5519567	1951435	0	0	120021	120042	120049	39986	3	40024	480010	20	240000	240000	20	480240	720000	121087	120042	1	1	80021	10	9	10	10	80000	80000	10	240060	0	36	0	0	240002	0	0	2	240000	2	34	0	5033	9	17	6	8	120039	240000	240000	10	120043	120043	120049	120044	120043
480024	120043	931	0	0	0	0	0	0	0	3	0	0	0	8514	0	120033	16	16	0	25	485959	10	248581	240000	10	240117	240000	50	5519567	1945606	0	0	120021	120042	120043	39984	3	40025	480010	20	240000	240000	20	480000	720000	120043	120042	1	1	80021	10	9	10	10	80000	80000	10	240000	0	34	0	0	240000	0	0	5	240060	2	34	0	5031	8	17	7	8	120188	240000	240000	10	120044	120050	120043	120043	120050
480024	120042	930	0	0	0	0	0	0	498	5	0	0	0	4000	0	120027	16	16	0	25	485882	10	247173	240000	10	240000	240000	50	5519663	1936182	0	0	120483	120043	120042	39984	3	40024	480010	20	240000	240000	20	480000	720360	120042	120043	1	1	80021	10	9	10	10	80000	80000	10	240000	2	34	0	0	240002	1	0	2	240002	2	34	0	5020	8	17	9	9	120040	240000	240000	10	120050	120044	120200	120043	120044
480024	120042	930	0	0	0	0	0	0	12	2	0	0	0	5720	0	120028	16	0	0	25	487628	10	245027	240000	10	240000	240108	50	5519567	1941474	0	0	120021	120132	120042	39984	3	40024	480010	20	240000	240000	20	480000	720000	120043	120042	1	1	80021	10	9	10	10	80000	80000	10	240000	0	0	0	0	240002	1	0	8	240002	2	34	0	5020	10	17	6	11	120039	240000	240000	10	120044	120043	120043	120049	120143
480024	120042	931	0	0	0	0	0	0	0	91	1	0	0	3590	0	120179	16	16	0	25	486792	10	247141	240000	10	240000	240000	50	5519687	1957145	0	0	120021	120042	120049	39990	3	40025	480010	20	240000	240000	20	480000	720000	120042	120202	1	1	80021	10	9	10	10	80000	80000	10	240000	0	34	52	0	240002	0	0	11	240002	2	34	0	5019	8	17	8	8	120045	240000	240000	10	120044	120044	120043	120043	120050
480024	120049	931	0	0	0	0	0	0	6	3	1	0	0	6429	0	120027	16	16	0	25	485015	10	246663	240000	10	240117	240000	50	5519567	1955356	0	0	120021	120049	120042	39984	16	40030	480235	20	240000	240000	20	480000	720000	120043	120042	1	1	80021	10	9	10	10	80000	80000	10	240000	0	34	0	0	240002	0	0	870	240062	0	34	0	5251	9	44	6	9	120465	240000	240000	10	124487	123727	123266	146320	120512
480024	120349	933	0	0	0	1	3	1	132	176	0	0	0	6564	0	121711	16	16	178	94	486331	10	246058	240120	10	240234	240216	50	5537432	1935591	0	0	120164	120352	120197	40076	8	40275	480460	20	240240	240120	20	480480	720720	120195	120357	2	1	80021	10	9	10	10	80000	80000	10	240000	0	0	47	0	240064	1	0	2	240002	2	34	0	5020	10	17	7	7	120039	240000	240000	10	120043	120050	120044	120044	120043

ST3 (multiple, 8H)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations