Firestorm: ST3 (multiple, post-index, 16B) measurements

Code:

  st3 { v0.16b, v1.16b, v2.16b }, [x6], x8
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 0
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 6.000

Issues: 7.000

Integer unit issues: 1.000

Load/store unit issues: 3.000

SIMD/FP unit issues: 3.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	1f	24	37	3a	3f	46	49	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	5f	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd store (99)	inst ldst (9b)	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	cf	d0	d2	l1i cache miss demand (d3)	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
66008	28877	232	2	0	2	0	0	0	1	0	0	132	3	0	0	4688	28722	3	3	16785	7000	1000	3000	3000	1001	3000	3000	5000	33060	28806	16	24082	28571	28769	3	10	7000	3000	3000	7000	9000	28799	28759	1	1	61001	1000	1000	3000	2	0	0	3000	0	0	0	3000	3	7	0	0	13291	9455	6986	3133	0	35	19606	3234	3811	13	35	37	28307	1000	15615	12247	13667	3000	3000	1000	28801	28822	28769	28753	28680
66004	28733	230	0	1	0	1	1	1	1	0	0	0	4	0	0	4753	28747	3	3	16688	7000	1000	3000	3000	1000	3000	3000	5000	33011	24000	16	22715	28483	28614	3	10	7000	3000	3000	7000	9000	28760	28657	1	1	61001	1000	1000	3008	3	9	0	3003	0	2	3	3000	3	11	3	2	13048	9344	6921	3188	0	37	19651	3244	3807	16	37	38	28334	1000	15833	12101	13974	3000	3000	1000	28791	28712	28799	28851	28882
66004	28830	231	0	1	0	2	1	0	1	0	0	0	4	0	0	4734	28725	3	3	16693	7000	1000	3000	3000	1000	3000	3000	5000	33026	24000	11	22773	28627	28739	3	10	7000	3000	3000	7007	9000	28686	28761	1	1	61001	1000	1000	3000	0	6	0	3000	0	0	0	3000	0	6	0	0	13268	9359	6921	3151	0	38	19635	3267	3810	18	33	36	28430	1000	15944	12315	14048	3000	3000	1000	29134	29022	29099	29003	29028
66004	29009	233	1	0	0	0	0	1	0	0	0	0	2	0	0	4761	28542	0	2	16743	7000	1000	3000	3000	1000	3000	3000	5000	33040	24000	12	22701	28562	28717	3	10	7000	3000	3000	7000	9000	28720	28751	1	1	61001	1000	1000	3000	0	6	0	3000	0	0	1	3000	0	0	0	0	13102	9414	7027	3160	0	38	19499	3185	3820	14	31	32	28291	1000	15221	12230	13659	3000	3000	1000	28680	28819	28598	28689	28590
66004	28815	231	0	0	0	0	0	0	0	0	0	0	0	0	0	4732	28647	0	3	16614	7000	1000	3000	3000	1000	3000	3000	5000	33033	24000	17	22680	28460	28778	3	10	7000	3000	3000	7000	9000	28837	28906	1	1	61001	1000	1000	3000	0	6	0	3000	1	0	0	3000	0	6	0	0	13176	9608	6972	3205	0	42	19588	3207	3817	7	38	35	28189	1000	15453	12239	13601	3000	3000	1000	28844	28798	28838	28919	28584
66004	28879	230	0	0	1	0	0	0	0	0	0	0	1	0	0	4709	28537	0	3	17025	7000	1001	3003	3003	1000	3000	3000	5000	33042	24000	14	22694	28478	28696	3	10	7000	3000	3000	7000	9000	28691	28780	1	1	61001	1000	1000	3000	0	6	0	3000	0	0	0	3000	0	6	0	0	13060	9354	6972	3214	0	37	19315	3144	3813	13	39	39	28189	1000	15608	12174	13528	3000	3000	1000	28849	28929	28810	28880	28793
66004	28883	231	0	0	0	0	0	0	0	0	0	0	1	0	0	4716	28573	3	2	16655	7000	1000	3000	3000	1000	3000	3000	5000	33036	24000	13	22722	28613	28773	3	10	7000	3000	3000	7000	9000	28670	28817	1	1	61001	1000	1000	3000	0	6	0	3001	0	0	3	3001	1	6	0	0	13156	9426	6903	3146	0	37	19595	3249	3811	9	36	39	28343	1000	15640	12539	13969	3000	3000	1000	28909	28830	28750	28715	28937
66004	28797	231	0	0	0	0	0	0	0	0	0	12	2	0	0	4697	28727	0	3	16615	7000	1000	3000	3003	1000	3000	3000	5000	33000	24000	5	22619	28510	28771	3	10	7000	3000	3000	7000	9000	28891	28723	2	1	61001	1000	1000	3000	0	6	0	3000	0	0	1	3000	0	0	0	0	13083	9516	6951	3154	0	42	19697	3313	3814	22	35	36	28436	1000	15716	12577	14017	3000	3000	1000	28731	28827	28920	28732	29057
66004	28693	232	0	0	0	1	0	0	0	0	1	12	1	0	0	4731	29114	3	2	17152	7000	1000	3000	3000	1000	3000	3000	5000	33042	24000	10	22678	28397	28808	9	10	7000	3000	3000	7000	9000	28524	28523	1	1	61001	1000	1000	3000	0	6	0	3000	0	0	0	3000	0	0	0	0	13333	9727	6943	3207	0	39	19307	3173	3810	10	35	43	28169	1000	15036	12192	13765	3000	3000	1000	28518	28480	28665	28476	28585
66004	28520	221	0	0	0	0	1	0	0	0	0	0	1	0	0	4601	29738	2	3	16576	7000	1000	3000	3000	1000	3000	3000	5000	33025	24000	10	22793	28442	28617	3	24	7000	3000	3000	7000	9000	28560	28648	1	1	61001	1000	1000	3000	0	0	0	3000	0	0	3	3000	0	7	0	0	13370	9479	6911	3260	0	35	19364	3238	3817	12	34	34	28160	1000	15365	12055	13178	3000	3000	1000	28623	28459	28567	28780	28581

Count: 8

Code:

  st3 { v0.16b, v1.16b, v2.16b }, [x6], x8
  st3 { v0.16b, v1.16b, v2.16b }, [x6], x8
  st3 { v0.16b, v1.16b, v2.16b }, [x6], x8
  st3 { v0.16b, v1.16b, v2.16b }, [x6], x8
  st3 { v0.16b, v1.16b, v2.16b }, [x6], x8
  st3 { v0.16b, v1.16b, v2.16b }, [x6], x8
  st3 { v0.16b, v1.16b, v2.16b }, [x6], x8
  st3 { v0.16b, v1.16b, v2.16b }, [x6], x8

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.5005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	22	23	24	37	3a	3f	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd store (99)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d0	d2	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
480208	120043	930	0	0	0	0	0	0	0	0	0	0	0	6422	0	120650	16	0	0	92	567333	80100	252127	240000	80100	240000	240000	480499	5519567	1947134	0	120021	120042	120043	39984	3	40025	560100	200	240000	240000	200	560000	720000	120042	120043	1	1	80201	100	99	100	100	80000	80000	100	240000	0	42	0	0	240002	0	0	5	240002	2	42	0	0	0	0	0	5110	0	0	1	17	1	2	120040	80000	240000	240000	80100	120044	120044	122797	121262	120043
480204	120053	931	0	0	0	0	0	0	0	3	0	0	0	4287	0	120039	0	16	0	25	563435	80100	247800	240000	80100	240000	240000	480499	5519567	1933040	0	120021	120043	120043	40077	3	40025	560100	200	240000	240000	200	560000	720360	120043	120043	1	1	80201	100	99	100	100	80000	80000	100	240000	0	44	0	0	240002	0	0	2	240002	2	0	0	0	0	0	0	5110	0	0	2	17	1	2	120049	80000	240000	240000	80100	120053	120055	120208	120062	120055
480204	120052	931	1	0	0	1	0	0	0	20	0	0	0	3608	1	120040	16	16	0	25	561434	80100	246939	240000	80100	240000	240000	480496	5519860	1944125	0	120027	120052	120207	39991	3	40034	560100	200	240000	240000	200	560000	720000	120052	120061	1	1	80201	100	99	100	100	80000	80000	100	240077	15	44	0	0	240016	0	0	19	240002	16	44	14	0	1	0	0	5110	0	0	2	17	2	1	120059	80000	240000	240000	80100	120055	120208	120053	120055	120055
480204	120062	931	1	0	1	1	1	0	0	18	0	0	0	4536	1	120037	16	16	1	25	571016	80100	244546	240000	80100	240000	240000	480496	5519831	1945197	0	120028	120052	120054	39999	3	40033	560100	200	240120	240000	200	560000	720000	120054	120062	1	1	80201	100	99	100	100	80000	80000	100	240014	14	44	2	1	240016	0	0	21	240062	2	42	0	0	0	0	0	5110	0	0	2	17	1	2	120040	80000	240000	240000	80100	120043	120044	120044	120044	120044
480204	120042	932	0	0	0	0	0	0	0	3	0	0	0	5534	0	120040	16	16	0	25	565840	80100	245433	240000	80139	240000	240000	480499	5519567	1956560	0	120021	120043	120043	39984	3	40024	560100	200	240000	240000	200	560000	720000	120042	120043	1	1	80201	100	99	100	100	80000	80000	100	240000	0	42	0	0	240002	0	0	2	240002	2	42	0	0	0	0	0	5110	0	0	2	17	1	2	120040	80000	240000	240000	80100	120044	120044	120045	120044	120044
480204	120044	931	0	0	0	0	0	0	12	91	0	0	0	9997	0	120657	16	16	0	48	566537	80100	400735	240000	80100	240000	240000	480731	5519567	1944853	0	120021	120042	120043	39984	3	40025	560100	200	240000	240000	200	560000	720000	120043	120200	1	1	80201	100	99	100	100	80000	80000	100	240016	0	42	50	0	240002	0	0	0	240002	2	42	0	0	0	0	0	5110	0	0	2	25	2	1	120042	80000	240000	240000	80100	120044	120044	120044	120199	120045
480204	120043	931	0	0	1	0	0	0	0	3	0	0	0	9998	0	120045	16	16	0	25	566290	80100	245000	240000	80100	240000	240000	480499	5519567	1935817	0	120021	120196	120043	39984	3	40025	560100	200	241920	244800	208	562520	720000	120043	120043	1	1	80201	100	99	100	100	80000	80000	100	240000	0	42	0	0	240002	0	0	2	240002	0	42	0	0	0	0	0	5110	0	0	2	17	2	1	120040	80000	240000	240000	80100	120044	120201	120044	120044	120044
480204	120043	930	0	0	0	0	0	0	0	0	0	0	0	9965	0	120046	0	16	0	25	564388	80100	245715	240000	80100	240000	240000	480499	5519567	1947825	0	120021	120043	120043	39984	3	40025	560100	200	240120	240000	200	560000	720000	120043	120043	1	1	80201	100	99	100	100	80000	80000	100	240000	0	0	0	0	240002	0	0	2	240002	2	42	0	0	0	0	0	5122	0	0	2	17	2	1	120184	80000	240000	240000	80100	120043	120044	120045	120044	120044
480204	120043	930	0	0	0	0	0	0	12	3	0	0	0	8852	0	120038	0	0	0	25	562974	80100	243843	240000	80100	240000	240000	480499	5519567	1959395	0	120021	120043	120043	39984	3	40025	560100	200	240000	240000	200	560000	720000	120043	120043	2	1	80201	100	99	100	100	80000	80000	100	240000	0	42	0	2	240002	0	0	3	240002	2	42	0	0	0	0	0	5110	0	0	2	25	1	2	120039	80000	240000	240000	80100	120044	120043	120199	120044	120044
480204	120042	931	0	0	0	0	0	1	12	3	0	0	0	7132	0	120038	0	16	0	25	565103	80100	245255	240000	80100	240000	240000	480499	5519567	1954278	0	120021	120133	120042	39984	3	40025	560100	200	240000	240120	200	560000	720000	120042	120043	1	1	80201	100	99	100	100	80000	80000	100	240000	0	42	0	0	240002	1	0	5	240062	2	0	0	0	0	0	0	5110	0	0	1	17	1	1	120183	80000	240000	240000	80100	120043	120043	120044	120044	120043

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.5005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	22	23	24	37	3f	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd store (99)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	a4	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ld nt uop (e6)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
480028	120053	931	0	0	0	0	0	0	12	4	0	0	0	6856	120029	16	16	19187	25	566727	80010	243352	240000	80010	240000	240000	480049	5519567	1951537	0	120027	120044	120043	39984	3	40045	560010	20	240120	240000	20	560000	720000	120043	120043	1	1	80021	10	9	10	10	80000	80000	10	240000	0	42	0	240002	0	0	0	240062	16	42	0	5020	4	17	4	6	120040	0	80000	240000	240000	80010	120044	120044	120044	120044	120043
480024	120043	931	0	0	0	0	0	0	12	3	0	0	0	7137	120028	16	16	0	25	566437	80010	247281	240000	80010	240000	240000	480049	5519567	1960588	0	120021	120043	120042	39984	3	40035	560010	20	240000	240000	20	560000	720000	120043	120043	1	1	80021	10	9	10	10	80000	80000	10	240000	0	42	0	240002	4	0	2	240002	20	0	0	5020	6	17	3	3	120040	0	80000	240000	240000	80010	120044	120044	120044	120043	120044
480024	120043	930	0	0	0	0	0	0	0	0	0	0	0	5577	120028	0	16	0	25	567160	80010	249275	240000	80010	240000	240000	480049	5519567	1946830	0	120026	120135	120042	39984	3	40024	560010	20	240000	240000	20	560000	720000	120043	120043	1	1	80021	10	9	10	10	80000	80000	10	240000	0	46	0	240002	0	0	2	240002	16	42	0	5020	5	17	4	4	120040	0	80000	240000	240000	80010	120045	120044	120044	120044	120044
480024	120043	930	0	0	0	0	0	0	12	91	0	0	0	6430	120028	16	16	0	47	564771	80010	247144	240000	80010	240000	240000	480049	5519567	1954296	0	120021	120042	120043	39984	3	40025	560010	20	240000	240000	20	560000	720000	120043	120199	1	1	80021	10	9	10	10	80000	80000	10	240000	0	42	52	240002	0	0	6	240002	20	0	0	5020	5	17	6	4	120040	0	80000	240000	240000	80010	120044	120044	120044	120201	120044
480024	120042	931	0	0	1	0	0	0	0	3	0	0	0	9271	120027	0	16	0	25	569054	80010	244005	240000	80010	240000	240000	480049	5519567	1934303	0	120021	120198	120043	39984	3	40025	560010	20	240120	240000	20	560000	720000	120043	120044	1	1	80021	10	9	10	10	80000	80000	10	240000	0	42	0	240002	0	0	11	240002	20	0	0	5020	4	17	6	4	120184	0	80000	240000	240000	80010	120044	120044	120044	120044	120044
480024	120043	932	0	0	0	0	0	0	3	4	0	0	0	5956	120028	16	16	0	25	566441	80010	245721	240000	80049	240000	240000	480049	5519567	1957180	0	120021	120043	120043	39984	3	40025	560010	20	240000	240000	20	560000	720000	120043	120043	1	1	80021	10	9	10	10	80000	80000	10	240000	0	42	0	240002	0	4	2	240002	16	42	0	5020	5	17	5	6	120040	0	80000	240000	240000	80010	120044	120044	120044	120044	120044
480024	120043	931	0	0	0	0	0	0	0	3	0	0	0	9711	120028	16	16	93	25	564534	80010	245727	240000	80010	240000	240000	480049	5519567	1955151	0	120021	120043	120042	40076	3	40025	560010	20	240000	240000	20	560280	720000	120043	120043	1	1	80021	10	9	10	10	80000	80000	10	240000	0	42	0	240002	0	0	2	240002	20	42	0	5020	5	17	3	5	120040	0	80000	240000	240000	80010	120044	120044	120044	120199	120044
480024	120042	931	0	0	0	0	0	0	24	0	1	0	0	8721	120028	16	16	0	25	565723	80010	247881	240000	80010	240000	240000	480049	5519567	1959326	0	120021	120198	120043	39984	3	40025	560010	20	240000	240120	20	560000	720000	120043	120043	1	1	80021	10	9	10	10	80000	80000	10	240000	0	42	0	240002	1	0	2	240062	16	42	0	5020	5	17	4	6	120040	0	80000	240000	240000	80010	120044	120044	120044	120044	120044
480024	120043	931	0	0	0	0	0	0	21	3	0	0	0	9282	120028	16	16	0	25	569721	80010	246429	240000	80049	240000	240000	480049	5519567	1946220	0	120021	120043	120043	39984	3	40026	560010	20	240000	240000	20	560000	720000	120043	120043	1	1	80021	10	9	10	10	80000	80000	10	240000	0	0	0	240002	0	0	14	240002	16	42	0	5020	6	17	5	5	120040	0	80000	240000	240000	80010	120044	120044	120044	120044	120044
480024	120043	931	0	0	0	0	0	0	12	3	0	0	0	7138	120028	16	16	0	25	567157	80010	248572	240000	80010	240000	240000	480049	5519567	1945095	0	120021	120043	120043	39984	3	40025	560010	20	240000	240000	20	560000	720000	120043	120043	1	1	80021	10	9	10	10	80000	80000	10	240060	0	42	0	240000	0	0	5	240002	16	42	0	5020	5	17	4	5	120040	0	80000	240000	240000	80010	120045	120043	120044	120044	120044

ST3 (multiple, post-index, 16B)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations