Firestorm: ST3 (multiple, post-index, 2D) measurements

Code:

  st3 { v0.2d, v1.2d, v2.2d }, [x6], x8
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 0
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 6.000

Issues: 7.000

Integer unit issues: 1.000

Load/store unit issues: 3.000

SIMD/FP unit issues: 3.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	1f	22	23	3a	3f	46	49	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	5e	5f	60	61	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd store (99)	inst ldst (9b)	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	c9	cf	d0	d2	l1i cache miss demand (d3)	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
66008	28732	224	0	0	3	0	1	0	0	0	0	4	0	0	4731	28501	0	3	16435	7000	1000	3000	3000	1000	3000	3000	5000	33055	24000	0	12	1	8	22667	28366	28674	3	10	7000	3000	3000	7000	9000	28526	28576	1	1	61001	1000	1000	3004	4	0	2	3003	0	1	3	3000	3	9	3	1	0	13455	9648	7023	3222	0	51	19505	3201	3823	15	47	44	28169	1000	15120	12127	13331	3000	3000	1000	28541	28582	28559	28722	28639
66004	28655	221	1	1	0	1	1	0	0	0	12	4	0	0	4856	28464	3	3	16555	7000	1000	3000	3000	1000	3000	3000	5000	33034	24000	0	11	1	8	22762	28291	28687	3	10	7000	3000	3000	7000	9000	28486	28562	1	1	61001	1000	1000	3004	4	9	1	3003	1	1	6	3000	3	9	3	0	0	13238	9703	7034	3237	1	49	19383	3179	3814	18	47	50	28141	1000	14976	12163	13567	3000	3000	1000	28762	28666	28622	28573	28601
66004	28557	221	0	1	1	1	1	1	0	0	0	4	0	0	4762	28604	0	3	16615	7000	1000	3000	3000	1000	3000	3000	5000	33029	24000	0	15	1	0	22741	28484	28593	3	10	7000	3000	3000	7000	9000	28681	28625	1	1	61001	1000	1000	3004	3	9	1	3003	0	2	6	3000	3	9	3	1	0	13343	9391	7044	3225	0	50	19373	3246	3818	21	57	52	28176	1000	15588	12076	13413	3000	3000	1000	28600	28517	28736	28599	28632
66004	28656	221	0	1	1	1	1	0	0	0	0	4	0	0	4852	28551	2	3	16556	7000	1000	3000	3000	1000	3000	3000	5000	33034	24000	0	15	0	0	22727	28445	28654	3	10	7000	3000	3000	7000	9000	28541	28669	1	1	61001	1000	1000	3003	4	9	1	3003	0	1	3	3000	3	9	3	2	0	13148	9562	6939	3254	0	58	19411	3147	3814	17	54	54	28245	1000	15201	12216	13490	3000	3000	1000	28563	28662	28690	28588	28630
66004	28579	234	0	1	0	1	1	0	0	0	0	4	0	0	4753	28672	2	3	16846	7000	1000	3000	3000	1000	3000	3000	5000	33017	24000	0	14	0	0	22638	28419	28640	3	10	7000	3000	3000	7000	9000	28919	28763	1	1	61001	1000	1000	3004	3	9	1	3003	1	0	6	3000	4	9	3	0	0	12928	9514	6863	3091	0	43	19979	3190	3812	14	44	47	28625	1000	16452	13155	14455	3000	3000	1000	29135	29370	29175	29101	29348
66004	29255	227	3	0	0	0	5	0	0	0	0	1	0	0	4675	29149	3	3	17234	7000	1000	3000	3000	1000	3000	3000	5000	33040	24000	0	5	0	6	22704	28954	29254	3	10	7000	3000	3000	7000	9000	29162	29232	1	1	61001	1000	1000	3000	0	9	0	3000	0	0	0	3000	0	9	0	0	0	13061	9452	6961	3117	0	48	20144	3214	3829	13	44	49	28609	1000	16318	12846	14218	3000	3000	1000	29277	29193	29410	29322	29288
66004	29286	227	2	0	1	0	1	0	0	0	0	2	0	0	4647	29123	0	0	17175	7000	1000	3000	3000	1000	3000	3000	5000	33018	24000	0	6	0	0	22736	29033	29303	3	10	7000	3000	3000	7000	9000	29292	29312	1	1	61001	1000	1000	3000	0	6	0	3000	0	0	0	3000	0	6	0	0	0	13088	9284	7014	3174	0	55	20014	3133	3828	16	43	47	28601	1000	16203	12590	14206	3000	3000	1000	29264	29424	29286	29311	29379
66004	29367	228	2	0	1	0	1	0	0	0	0	1	0	0	4660	29130	0	0	17282	7000	1000	3000	3000	1000	3000	3000	5000	33027	24000	0	1	0	0	22737	28953	29466	3	10	7000	3000	3000	7000	9000	29412	29293	1	1	61001	1000	1000	3000	0	6	0	3000	0	0	0	3000	0	6	0	0	0	12994	9294	6935	3117	2	52	20047	3120	3827	11	49	48	28643	1000	16203	12812	14346	3000	3000	1000	29334	28867	29368	29304	29385
66004	29162	227	1	0	0	0	1	0	0	0	0	4	0	0	4755	29222	0	3	17210	7000	1000	3000	3000	1000	3000	3000	5000	33036	24000	0	1	1	0	22732	28888	29455	3	10	7000	3000	3000	7000	9000	29247	29335	1	1	61001	1000	1000	3004	3	6	2	3003	0	0	3	3000	3	6	3	1	0	13181	9292	6911	3153	0	46	20148	3139	3830	17	48	46	28730	1000	16176	12818	13749	3000	3000	1000	29367	29304	29290	29379	29292
66004	29342	227	0	1	0	1	0	1	0	0	0	4	0	0	4523	29211	3	0	17236	7000	1000	3000	3000	1000	3000	3000	5000	33040	24000	0	1	0	0	22794	28908	29285	3	10	7000	3000	3000	7000	9000	29335	29222	1	1	61001	1000	1000	3003	3	9	0	3003	0	1	3	3000	3	9	3	2	0	13125	9338	6953	3135	0	45	20102	3164	3823	17	46	50	28465	1000	15939	12766	14342	3000	3000	1000	29331	29242	29193	29317	29208

Count: 8

Code:

  st3 { v0.2d, v1.2d, v2.2d }, [x6], x8
  st3 { v0.2d, v1.2d, v2.2d }, [x6], x8
  st3 { v0.2d, v1.2d, v2.2d }, [x6], x8
  st3 { v0.2d, v1.2d, v2.2d }, [x6], x8
  st3 { v0.2d, v1.2d, v2.2d }, [x6], x8
  st3 { v0.2d, v1.2d, v2.2d }, [x6], x8
  st3 { v0.2d, v1.2d, v2.2d }, [x6], x8
  st3 { v0.2d, v1.2d, v2.2d }, [x6], x8

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.5005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	1f	22	23	37	3a	3f	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd store (99)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
480208	120042	931	0	0	0	0	0	0	0	0	21	1	0	4397	1	120035	16	16	6	25	567242	80100	243845	240000	80100	240000	240000	480495	5520240	1946004	0	120021	120042	120043	39984	3	40041	560100	200	240000	240000	200	560000	720000	120145	120043	1	1	80201	100	99	100	100	80000	80000	100	240000	0	36	0	0	240002	0	0	2	240002	16	34	0	5110	3	17	5	4	120040	80000	240000	240000	80100	120043	120043	120043	120043	120044
480204	120049	930	0	0	0	0	0	0	0	6	9	0	0	5227	0	120028	16	0	90	25	563763	80100	247606	240000	80100	240000	240000	480499	5519567	1957446	0	120681	120049	120042	39984	3	40065	560100	200	240000	240000	200	560000	720000	120043	120042	1	1	80201	100	99	100	100	80000	80000	100	240000	0	34	0	0	240002	1	0	5	240002	2	34	0	5110	3	17	4	3	120039	80000	240000	240000	80100	120049	120043	120044	120060	120050
480204	120043	931	0	0	0	0	0	0	0	0	3	0	0	4803	0	120027	16	16	0	25	562986	80100	242475	240000	80100	240000	240000	480499	5519567	1944360	1	120021	120042	120043	39984	3	40025	560100	200	240000	240000	200	560000	720000	120043	120049	2	1	80201	100	99	100	100	80000	80000	100	240000	0	34	0	0	240002	0	0	8	240002	2	34	0	5110	3	17	3	3	120046	80000	240000	240000	80100	120050	120043	120202	120043	120044
480204	120048	930	0	0	0	0	0	0	0	0	3	0	0	6460	0	120027	16	16	0	25	567931	80100	242883	240000	80100	240000	240000	480498	5519567	1941674	0	120021	120042	120048	39984	3	40025	560100	200	240000	240000	200	560000	720000	120049	120043	1	1	80201	100	99	100	100	80000	80000	100	240000	0	34	0	0	240000	0	0	11	240002	0	34	0	5110	4	17	3	4	120040	80000	240000	240000	80100	120043	120044	120043	120050	120050
480204	120042	931	0	0	0	0	0	0	0	0	9	0	0	6437	0	120028	16	16	0	25	562872	80100	244283	240000	80100	240000	240000	480499	5519567	1942105	0	120021	120043	120048	39984	3	40024	560100	200	240000	240000	200	560000	720000	120049	120043	1	1	80201	100	99	100	100	80000	80000	100	240000	0	34	0	0	240002	0	0	5	240002	2	34	0	5110	3	17	3	3	120040	80000	240000	240000	80100	120043	120043	120043	120043	120044
480204	120042	930	0	0	0	0	0	0	0	21	9	0	1	4303	0	120027	16	16	0	25	564389	80100	245874	240000	80100	240000	240000	480499	5519567	1939120	0	120021	120043	120042	39987	3	40024	560100	200	240000	240000	200	560000	720000	120042	120049	1	1	80201	100	99	100	100	80000	80000	100	240000	0	34	0	0	240002	0	0	5	240002	2	34	0	5109	2	17	3	3	120040	80000	240000	240000	80100	120043	120043	120043	120043	120044
480204	120042	930	0	0	0	0	0	0	0	0	3	0	0	5883	0	120027	16	16	365	25	567962	80100	246295	240000	80100	240000	240000	480498	5519567	1941740	0	120021	120043	120043	39984	3	40024	560100	200	240000	240000	200	560000	720000	120049	120042	1	1	80201	100	99	100	100	80000	80000	100	240000	0	34	0	0	240002	0	0	2	240002	2	34	0	5110	5	17	3	3	120039	80000	240000	240000	80100	120044	120053	120044	120044	120043
480204	120043	931	0	0	0	0	0	0	0	12	3	0	0	7454	0	120034	16	16	0	25	564094	80100	244668	240000	80100	240000	240000	480498	5519567	1954350	0	120021	120042	120049	39984	3	40025	560100	200	240000	240000	200	560000	720000	120043	120043	1	1	80201	100	99	100	100	80000	80000	100	240000	0	0	0	0	240002	0	0	2	240002	2	34	0	5110	4	17	4	3	120046	80000	240000	240000	80100	120050	120044	145546	120060	120043
480204	120049	930	0	0	0	0	0	0	0	21	3	0	0	4549	0	120028	16	16	0	25	566769	80100	246905	240000	80100	240000	240000	480499	5519567	1946869	0	120021	120043	120042	39984	3	40030	560100	200	240000	240000	200	560000	720000	120042	120043	1	1	80201	100	99	100	100	80000	80000	100	240000	0	34	0	0	240002	0	0	5	240002	2	34	0	5110	3	17	5	3	120040	80000	240000	240000	80100	120043	120049	120044	120050	120050
480204	120042	931	0	0	0	0	0	0	0	0	9	0	0	9261	1	120027	16	16	0	25	569752	80100	245711	240000	80100	240000	240108	480499	5519567	1938670	0	120021	120043	120043	39984	3	40024	560100	200	240000	240000	200	560000	720000	120204	120042	1	1	80201	100	99	100	100	80000	80000	100	240000	0	36	0	0	240002	0	0	2	240002	2	34	0	5110	3	17	3	5	120039	80000	240000	240000	80100	120044	120043	120358	144821	120044

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.5006

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	0f	18	19	1e	1f	22	23	24	37	3a	3f	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd store (99)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
480028	120050	930	1	1	0	0	0	0	0	21	0	0	0	7771	1	120033	16	16	0	25	567076	80010	247794	240000	80010	240000	240000	480049	5519567	1945903	1	120025	0	120042	120043	39984	3	40040	560010	20	240000	240000	20	560000	720000	120049	120042	1	1	80021	10	9	10	10	80000	80000	10	240000	0	0	0	1	240016	44	0	2	240002	16	34	0	0	5020	3	17	3	3	120040	80000	240000	240000	80010	120052	120061	120053	120054	120050
480024	120050	931	0	0	0	0	0	0	0	19	0	0	0	5012	0	120043	16	0	0	25	572040	80166	246425	240000	80010	240000	240000	480045	5519836	1950975	1	120021	0	120049	120202	39988	3	40024	560538	20	240000	240000	20	560000	720000	120047	120051	1	1	80021	10	9	10	10	80000	80000	10	240015	17	35	0	0	240002	44	0	18	240002	0	0	14	0	5020	3	16	3	3	120039	80000	240000	240000	80010	120043	120195	120043	120049	120061
480024	120042	931	1	2	0	0	0	1	15	19	0	0	0	3605	1	120034	16	0	0	25	563272	80010	248273	240000	80010	240000	240000	480049	5519567	1942192	1	120034	0	120042	120043	39984	3	40029	560010	20	240120	240000	20	560000	720000	120043	120042	1	1	80021	10	9	10	10	80000	80000	10	240000	0	34	0	1	240014	7	0	5	240002	16	34	0	0	5019	3	17	3	3	120040	80000	240000	240000	80010	120051	120058	120059	120053	120043
480024	120051	930	0	0	1	0	0	0	0	18	0	0	0	6564	0	120036	16	16	0	25	564543	80010	245362	240000	80010	240000	240108	480049	5519788	1943557	1	120021	0	120049	120050	39988	3	40024	560010	20	240000	240000	20	560000	720000	120057	120050	2	1	80021	10	9	10	10	80000	80000	10	240015	15	36	0	0	240002	57	0	21	240002	2	38	0	0	5020	3	17	4	3	144808	80000	240000	240000	80010	120043	120043	120049	120044	120198
480024	120042	931	1	0	0	0	0	0	0	14	0	0	0	2333	1	120027	0	16	0	25	566455	80010	244546	240000	80010	240000	240000	480049	5519687	1939305	1	120021	0	120043	120049	39986	3	40024	560010	20	240000	240000	20	560000	720000	120043	120195	1	1	80021	10	9	10	10	80000	80000	10	240000	0	0	0	0	240002	31	0	5	240002	16	0	0	0	5020	2	25	2	3	120039	80000	240000	240000	80010	120060	120051	120204	120061	120044
480024	120042	930	0	0	0	0	0	0	0	3	0	0	0	7128	0	120027	16	16	0	25	565369	80010	242160	240000	80010	240000	240000	480048	5519567	1943818	1	120024	0	120042	120194	39984	3	40024	560010	20	240000	240120	20	560000	720000	120042	120043	1	1	80021	10	9	10	10	80000	80000	10	240000	0	34	0	0	240002	37	0	3	240062	2	34	0	0	5020	3	17	2	3	120040	80000	240000	240000	80010	120043	120049	120043	120043	120044
480024	120195	930	0	0	0	0	0	0	0	0	0	0	0	7997	0	120028	16	16	0	25	566456	80166	243612	240060	80049	240000	240000	480049	5519567	1944916	1	120021	0	120207	120042	39984	3	40035	571098	20	240000	240000	20	560000	720000	120042	120043	1	1	80021	10	9	10	10	80000	80000	10	240000	0	34	16422	0	240002	12	0	0	240002	2	34	0	0	5020	3	17	3	3	120039	80000	240000	240000	80010	120043	120049	120043	120043	120043
480024	120043	931	0	0	0	0	0	0	0	0	0	0	0	7367	0	120027	0	16	0	33	566201	80010	245664	240000	80010	240000	240000	480049	5519567	1959722	1	120025	0	120042	120049	39990	6	40025	560010	20	240000	240000	20	560000	720000	120050	120049	1	1	80021	10	9	10	10	80000	80000	10	240015	14	36	0	0	240062	50	0	18	240002	2	36	14	0	5020	3	17	2	3	120039	80000	240000	240000	80010	120044	120049	120043	120043	120054
480024	120050	930	1	0	0	2	0	0	0	19	0	0	0	4335	1	120027	0	0	0	25	719948	80010	243428	240000	80010	240000	240000	480049	5519567	1943006	1	144582	0	120043	120042	39984	3	40029	560010	20	240000	240000	20	560000	720000	120042	120043	1	1	80021	10	9	10	10	80000	80000	10	240000	0	34	0	0	240016	55	0	0	240002	2	34	0	0	5020	3	17	3	3	120039	80000	240000	240000	80010	120050	120043	120043	120050	120044
480024	120058	930	0	0	1	0	0	0	0	21	0	0	0	6561	0	120043	16	0	0	25	562815	80010	245995	240000	80010	240000	240108	480049	5519567	1945080	1	120024	0	120042	120042	39984	3	40025	560010	20	240000	240000	20	560000	720000	120049	120043	1	1	80021	10	9	10	10	80000	80000	10	240000	0	34	0	0	240006	55	0	872	240002	2	0	0	0	5020	3	17	3	3	120040	80000	240000	240000	80010	120043	120043	120050	120044	120044

ST3 (multiple, post-index, 2D)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations