Firestorm: ST3 (multiple, post-index, 2S) measurements

Code:

  st3 { v0.2s, v1.2s, v2.2s }, [x6], x8
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 0
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 4.000

Issues: 5.000

Integer unit issues: 1.000

Load/store unit issues: 2.000

SIMD/FP unit issues: 2.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	1e	1f	22	3a	3f	46	49	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	5f	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd store (99)	inst ldst (9b)	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	cf	d0	d2	l1i cache miss demand (d3)	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
64007	29390	220	3	1	1	0	1	1	0	2	0	4621	29093	0	0	18168	5000	1000	2000	2000	1000	2000	2000	5000	21610	16000	8	21769	28981	29299	3	10	5000	2000	2000	5000	6000	29253	29215	1	1	61001	1000	1000	2004	2	6	0	2002	0	0	2	2000	2	6	2	3	12696	9036	6824	3041	0	47	20267	3076	3809	12	51	43	28440	1000	16470	13331	14606	2000	2000	1000	29242	29326	29323	29255	29289
64004	29316	219	0	1	3	0	1	0	0	3	0	4517	29048	0	0	18132	5000	1000	2000	2000	1000	2000	2000	5000	21616	16000	3	21768	28854	29235	3	10	5000	2000	2000	5000	6000	29247	29219	1	1	61001	1000	1000	2003	2	6	2	2002	0	1	2	2000	2	6	2	2	12831	9060	6862	3038	0	44	20251	3031	3806	11	43	46	28502	1000	16588	13516	14612	2000	2000	1000	29260	29253	29252	29287	29206
64004	29303	220	0	1	1	1	3	1	6	3	1	4573	29052	2	2	18169	5000	1000	2000	2000	1000	2000	2000	5000	21619	16000	1	21759	28948	29191	3	10	5000	2000	2000	5005	6006	29205	29335	1	1	61001	1000	1000	2003	2	6	0	2002	0	1	5	2000	2	6	2	0	12981	9161	6883	3020	0	44	20319	3045	3812	10	50	43	28434	1000	16455	13376	14630	2000	2000	1000	29198	29293	29225	29295	29265
64004	29230	227	0	1	1	1	1	1	0	3	1	4545	29023	0	1	18112	5000	1000	2000	2000	1000	2000	2000	5000	21616	16000	4	21788	28971	29141	3	10	5000	2000	2000	5000	6000	29141	29254	1	1	61001	1000	1000	2004	3	8	2	2003	0	1	2	2000	3	6	2	2	12814	8932	6843	3058	1	50	20263	3065	3811	9	51	45	28465	1000	16409	13512	14727	2000	2000	1000	29236	29333	29301	29299	29308
64004	29217	219	0	1	0	1	1	0	0	3	0	4535	29091	0	1	18177	5000	1000	2000	2000	1000	2000	2000	5000	21628	16000	1	21769	28997	29366	3	10	5000	2000	2000	5000	6000	29286	29172	1	1	61001	1000	1000	2002	2	4	0	2003	1	0	3	2001	3	6	2	2	12958	9124	6881	3071	0	48	20317	3059	3814	11	49	45	28503	1000	16519	13294	14728	2000	2000	1000	29284	29321	29261	29234	29256
64004	29269	219	0	1	1	0	2	1	0	3	0	4581	29032	0	0	18190	5000	1000	2000	2000	1000	2000	2000	5000	21620	16000	1	21775	28898	29391	3	10	5000	2000	2000	5000	6000	29211	29284	1	1	61001	1000	1000	2003	2	6	1	2003	0	3	6	2001	3	4	2	1	12888	9320	6820	3190	0	46	20234	3031	3813	7	46	47	28467	1000	16536	13320	14724	2000	2000	1000	29271	29285	29303	29279	29313
64004	29308	219	0	1	0	1	1	0	0	4	0	4526	29159	2	0	18157	5000	1000	2000	2000	1000	2000	2000	5000	21614	16000	1	21804	28990	29336	3	10	5000	2000	2000	5000	6000	29171	29172	1	1	61001	1000	1000	2002	2	4	2	2002	0	1	2	2000	2	6	2	0	12809	9158	6825	3073	1	41	20311	3051	3809	10	48	42	28541	1000	16370	13279	14631	2000	2000	1000	29260	29341	29225	29263	29229
64004	29273	219	0	1	2	1	0	0	0	4	1	4645	29130	2	1	18175	5000	1000	2000	2000	1000	2000	2000	5000	21616	16000	5	21824	28993	29198	3	10	5000	2000	2000	5000	6000	29209	29168	1	1	61001	1000	1000	2002	4	6	1	2003	0	1	2	2001	2	4	2	1	12774	9078	6863	3052	0	44	20330	3044	3817	4	46	46	28504	1000	16470	13289	14616	2000	2000	1000	29288	29319	29304	29273	29211
64004	29379	220	0	1	1	1	1	0	615	3	1	4565	29049	1	0	18148	5000	1000	2000	2000	1000	2000	2000	5000	21615	16000	3	21752	28954	29268	3	10	5000	2000	2000	5000	6000	29231	29230	1	1	61001	1000	1000	2003	3	6	1	2003	0	0	2	2000	2	4	2	1	12818	9190	6853	3029	1	41	20198	3044	3812	12	43	43	28430	1000	16547	13150	14242	2000	2000	1000	29288	29247	29241	29219	29203
64004	29277	219	0	1	1	1	1	0	546	3	1	4534	29123	1	1	18206	5000	1000	2000	2000	1000	2000	2000	5000	21620	16000	1	21731	28953	29273	3	10	5000	2000	2000	5000	6000	29231	29194	1	1	61001	1000	1000	2003	3	4	2	2002	1	0	2	2000	2	4	2	1	12854	9194	6859	3043	1	46	20251	3090	3809	6	44	44	28537	1000	16539	13319	14621	2000	2000	1000	29259	29258	29246	29324	29240

Count: 8

Code:

  st3 { v0.2s, v1.2s, v2.2s }, [x6], x8
  st3 { v0.2s, v1.2s, v2.2s }, [x6], x8
  st3 { v0.2s, v1.2s, v2.2s }, [x6], x8
  st3 { v0.2s, v1.2s, v2.2s }, [x6], x8
  st3 { v0.2s, v1.2s, v2.2s }, [x6], x8
  st3 { v0.2s, v1.2s, v2.2s }, [x6], x8
  st3 { v0.2s, v1.2s, v2.2s }, [x6], x8
  st3 { v0.2s, v1.2s, v2.2s }, [x6], x8

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0006

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	22	37	3f	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd store (99)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	c2	branch mispred nonspec (cb)	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
320207	80053	620	0	0	0	0	0	0	3	0	2718	80030	16	0	0	25	403670	80159	167194	160000	80100	160000	160000	480499	2079561	1295674	80023	80045	80045	0	3	35	400100	200	160000	160000	200	400000	480000	80044	80213	1	1	80201	100	99	100	100	80000	80000	100	160000	0	40	0	0	160000	0	0	2	160063	2	40	0	0	5109	0	1	17	1	1	80042	80000	0	160000	160000	80100	80046	80045	80045	80046	80047
320204	80046	621	0	0	0	1	1	0	3	0	5494	80364	16	16	90	72	402373	80218	164092	160000	80159	160118	160216	481203	2172330	1295165	80180	80213	80212	577	44	1684	400385	200	160120	160120	200	400300	480360	80214	80548	2	1	80201	100	99	100	100	80000	80000	100	160060	0	40	125	0	160120	0	0	2767	160122	0	40	0	0	5122	0	1	35	2	2	82665	80059	0	160000	160000	80100	80380	80218	80378	80213	80215
320204	80377	623	1	0	0	1	2	132	91	0	4815	80365	16	16	181	95	403193	80161	164370	160060	80218	160236	160108	481203	2198305	1295849	80023	80045	80044	0	3	28	400100	200	160000	160000	200	400000	480000	80044	80045	1	1	80201	100	99	100	100	80000	80000	100	160000	0	40	0	0	160002	0	0	0	160002	2	40	0	0	5109	0	1	17	1	1	80041	80000	0	160000	160000	80100	80055	80046	80045	80053	80047
320204	80045	620	0	0	0	0	0	0	3	0	2388	80037	16	16	0	25	403886	80100	163927	160000	80100	160000	160000	480499	2078751	1303060	80023	80044	80045	0	3	26	400100	200	160000	160000	200	400000	480000	80054	80045	1	1	80201	100	99	100	100	80000	80000	100	160000	0	40	0	0	160002	0	0	2	160002	2	40	0	0	5109	0	1	17	1	1	80042	80000	0	160000	160000	80100	80045	80045	80045	80046	80046
320204	80045	621	0	0	0	0	0	0	3	0	5149	80029	16	16	0	25	406036	80100	163583	160000	80100	160000	160000	480499	2079244	1294687	80023	80045	80044	0	3	26	400100	200	160000	160000	200	400000	480000	80044	80044	1	1	80201	100	99	100	100	80000	80000	100	160000	0	40	0	0	160002	0	0	5	160002	2	40	0	0	5109	0	1	17	1	1	80048	80000	0	160000	160000	80100	80045	80046	80046	80046	80045
320204	80045	620	1	0	0	0	0	0	3	0	4168	80029	16	16	0	25	403915	80100	163719	160000	80100	160000	160000	480499	2079393	1293745	80024	80044	80045	0	3	27	400100	200	160000	160000	200	400000	480000	80044	80045	1	1	80201	100	99	100	100	80000	80000	100	160000	0	40	0	0	160002	2	0	2	160002	2	40	0	0	5109	0	1	17	1	1	80041	80000	0	160000	160000	80100	80046	80045	80047	80045	80046
320204	80045	620	0	0	0	0	0	0	3	1	3979	80030	16	16	0	25	404685	80100	164329	160000	80100	160000	160000	480499	2236406	1293555	80024	80045	80045	0	3	26	400100	200	160000	160000	200	400000	480000	80045	80045	1	1	80201	100	99	100	100	80000	80000	100	160000	0	40	0	0	160002	0	0	2	160002	2	40	0	0	5109	0	1	17	1	1	80042	80000	0	160000	160000	80100	80046	80046	80045	80046	80046
320204	80045	620	0	0	0	0	0	0	3	0	5930	80030	16	16	0	25	406669	80100	163342	160000	80100	160000	160000	480499	2156417	1299546	80023	80046	80045	0	3	36	400100	200	160000	160000	200	400000	480000	80052	80045	1	1	80201	100	99	100	100	80000	80000	100	160000	0	40	0	0	160002	0	0	2	160002	2	40	0	0	5109	0	1	17	1	1	80041	80000	0	160000	160000	80100	80046	80046	80046	80046	80045
320204	80045	621	0	0	0	0	0	12	0	0	5444	80031	16	0	0	25	404248	80100	163834	160000	80100	160000	160000	480499	2078918	1299686	80025	80045	80044	0	3	36	400100	200	160000	160000	200	400000	480000	80044	80045	1	1	80201	100	99	100	100	80000	80000	100	160000	0	40	0	0	160002	0	0	2	160002	0	40	0	0	5109	0	1	17	1	1	80042	80000	0	160000	160000	80100	81260	80046	80049	80045	80046
320204	80045	621	0	0	0	0	0	0	3	0	6251	80107	16	16	0	25	404700	80100	162882	160000	80100	160000	160000	480499	2079252	1293947	80023	80044	80043	0	3	109	400100	200	160000	160000	200	400000	480000	80044	80044	1	1	80201	100	99	100	100	80000	80000	100	160000	0	40	0	0	160002	1	0	5	160002	2	40	0	0	5109	0	1	17	1	1	80042	80000	0	160000	160000	80100	80047	80045	80046	80046	80045

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0006

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	22	24	37	3a	3f	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	5f	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	91	inst branch cond (94)	inst int alu (97)	inst simd store (99)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
320027	80057	620	1	1	1	0	1	0	0	12	619	0	0	4584	3	80034	16	16	0	25	406513	80010	167048	160000	80010	160000	160000	480049	2162074	1298611	0	0	80024	80045	80044	0	3	36	400010	20	160000	160000	20	400000	480000	80224	80045	1	1	80021	10	9	0	10	10	80000	80000	10	160000	0	40	0	0	160002	0	0	2	160002	2	40	0	5021	7	17	10	10	80042	80000	0	160000	160000	80010	80045	80046	80046	80045	80045
320024	80044	620	0	0	0	0	0	0	0	6	3	0	0	3903	1	80030	16	16	0	25	405823	80010	164651	160000	80010	160000	160000	480049	2079022	1298254	0	0	80022	80044	80045	0	3	27	400010	20	160000	160000	20	400000	480000	80044	80054	1	1	80021	10	9	0	10	10	80000	80000	10	160000	0	40	0	0	160002	0	0	2	160002	2	40	0	5021	11	17	10	8	80041	80000	0	160000	160000	80010	80046	80046	80046	80045	80046
320024	80043	621	0	0	0	0	1	0	0	0	3	0	0	5080	1	80030	16	0	0	25	405062	80069	164759	160068	80010	160000	160000	480049	2158256	1293909	0	0	80024	80046	80045	0	3	27	400010	20	160000	160000	20	400000	480000	80045	80215	1	1	80021	10	9	0	10	10	80000	80000	10	160000	0	40	0	0	160000	0	0	2	160000	2	40	0	5021	10	17	11	9	80042	80000	0	160000	160000	80010	80046	80046	80047	80046	80046
320024	80046	621	0	0	0	0	0	0	0	0	3	0	0	3941	1	80030	0	16	0	25	405064	80010	165512	160000	80010	160000	160000	480049	2314599	1303565	0	0	80024	80046	80045	0	3	27	400010	20	160000	160000	20	400000	480000	80045	80044	1	1	80021	10	9	0	10	10	80000	80000	10	160000	0	40	0	0	160002	0	0	0	160002	2	40	0	5021	9	17	10	10	80383	80000	0	160000	160000	80010	80046	80046	80046	80046	80046
320024	80044	620	0	0	0	0	0	0	0	0	91	0	0	6478	1	80031	0	16	0	25	403986	80010	166102	160000	80010	160000	160000	480049	2233584	1302563	0	0	80023	80045	80045	0	3	27	400010	20	160120	160000	20	400000	480000	80045	80045	1	1	80021	10	9	0	10	10	80000	80000	10	160000	0	42	0	0	160002	0	0	2	160002	2	40	0	5021	10	17	8	10	80041	80000	0	160000	160000	80010	80211	80046	80046	80046	80045
320024	80045	620	0	0	0	0	0	0	0	0	3	0	0	4440	1	80199	16	0	0	25	406261	80010	163782	160000	80010	160118	160000	480049	2078410	1294846	0	0	80025	80043	82542	2386	3	26	400010	20	160000	160000	20	400000	480000	80044	80045	1	1	80021	10	9	0	10	10	80000	80000	10	160000	0	40	0	0	160002	0	0	2	160002	2	40	0	5021	7	17	10	10	80042	80000	0	160000	160000	80010	80049	80046	80046	80046	80045
320024	80044	621	0	0	0	0	0	0	0	0	3	0	0	3705	1	80030	16	16	0	25	406233	80010	165287	160000	80010	160000	160000	480049	1919779	1298809	0	0	80023	80045	80045	0	3	36	400010	20	160000	160000	20	400000	480000	80046	80046	1	1	80021	10	9	0	10	10	80000	80000	10	160000	0	40	0	0	160002	0	0	927	160002	0	40	0	5021	10	17	11	11	80042	80000	0	160000	160000	80010	80045	80046	80183	80046	80045
320024	80045	620	0	0	0	0	0	0	0	15	3	0	0	4209	1	80030	16	16	0	25	402555	80069	167194	160000	80010	160000	160000	480049	2156268	1296880	0	0	80024	80045	80044	0	3	30	400010	20	160000	160000	20	400000	480000	80213	80045	1	1	80021	10	9	0	10	10	80000	80000	10	160000	0	40	0	0	160002	0	0	5	160002	2	40	0	5021	11	17	10	8	80041	80000	0	160000	160000	80010	80045	80045	80045	80046	80046
320024	80046	620	0	0	0	0	0	0	0	0	3	0	0	4431	1	80029	16	16	0	25	403937	80010	164556	160000	80010	160000	160000	480049	2095389	1306533	0	0	80024	80045	80045	0	3	28	400010	20	160000	160000	20	400000	480000	80044	80044	1	1	80021	10	9	0	10	10	80000	80000	10	160000	0	40	0	0	160002	0	0	2	160002	2	40	0	5021	8	17	10	8	80041	80059	0	160000	160000	80010	80047	80046	80045	80045	80055
320024	80212	620	0	0	0	0	0	0	0	0	0	0	0	4044	1	80030	16	16	0	25	407049	80010	165179	160000	80010	160000	160000	480049	2078422	1294480	0	0	80024	80045	80045	0	3	26	400010	20	160000	160000	20	400000	480000	80044	80045	1	1	80021	10	9	0	10	10	80000	80000	10	160000	0	40	0	0	160000	0	0	2	160002	2	40	0	5021	10	17	7	11	80042	80000	0	160000	160000	80010	80046	80045	80047	80045	80045

ST3 (multiple, post-index, 2S)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations