Apple Microarchitecture Research by Dougall Johnson M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions M1/A14 E-core (Icestorm): Overview | Base Instructions | SIMD and FP Instructions
Code:
st3 { v0.4h, v1.4h, v2.4h }, [x6], x8 nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop
mov x0, 0 mov x8, 0
(no loop instructions)
Retires (minus 60 nops): 4.000
Issues: 5.000
Integer unit issues: 1.000
Load/store unit issues: 2.000
SIMD/FP unit issues: 2.000
retire uop (01) | cycle (02) | 03 | l1i tlb fill (04) | mmu table walk instruction (07) | mmu table walk data (08) | l2 tlb miss instruction (0a) | l2 tlb miss data (0b) | 18 | 19 | 1e | 1f | 22 | 24 | 3a | 3f | 46 | 49 | 50 | 51 | schedule uop (52) | schedule int uop (53) | schedule simd uop (54) | schedule ldst uop (55) | dispatch int uop (56) | dispatch simd uop (57) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | ldst uops in schedulers (5b) | 5f | 60 | 61 | 69 | 6d | 6e | map rewind (75) | map stall (76) | dispatch uop (78) | map ldst uop (7d) | map simd uop (7e) | map ldst uop inputs (80) | map simd uop inputs (81) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst simd store (99) | inst ldst (9b) | l1d tlb access (a0) | l1d tlb miss (a1) | l1d cache miss st (a2) | ld unit uop (a6) | st unit uop (a7) | l1d cache writeback (a8) | a9 | ac | af | bc | l1d cache miss st nonspec (c0) | c2 | c9 | cf | d0 | d2 | l1i cache miss demand (d3) | l1i tlb miss demand (d4) | d5 | map dispatch bubble (d6) | d9 | da | db | dd | fetch restart (de) | df | e0 | ? int output thing (e9) | ea | eb | ec | ? ldst retires (ed) | ? simd retires (ee) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
64007 | 28898 | 222 | 2 | 5 | 0 | 3 | 0 | 0 | 0 | 30 | 1 | 0 | 0 | 4575 | 28411 | 0 | 2 | 0 | 17628 | 5000 | 1000 | 2000 | 2000 | 1000 | 2000 | 2000 | 5000 | 21621 | 16000 | 6 | 0 | 0 | 21822 | 28498 | 28773 | 3 | 27 | 5000 | 2000 | 2000 | 5000 | 6000 | 28620 | 28560 | 1 | 1 | 61001 | 1000 | 1000 | 2000 | 0 | 6 | 0 | 2000 | 0 | 0 | 0 | 2002 | 0 | 6 | 0 | 0 | 13243 | 9775 | 7039 | 3248 | 1 | 64 | 19740 | 3278 | 3813 | 23 | 60 | 59 | 2 | 28244 | 1000 | 15361 | 12399 | 13769 | 2000 | 2000 | 1000 | 28738 | 28805 | 28680 | 28771 | 28766 |
64004 | 28705 | 222 | 0 | 3 | 0 | 4 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 4840 | 28572 | 2 | 2 | 0 | 17653 | 5000 | 1000 | 2000 | 2000 | 1000 | 2000 | 2000 | 5000 | 21618 | 16000 | 7 | 0 | 0 | 21866 | 28480 | 28676 | 3 | 10 | 5000 | 2000 | 2000 | 5000 | 6000 | 28703 | 28748 | 1 | 1 | 61001 | 1000 | 1000 | 2000 | 0 | 6 | 0 | 2000 | 0 | 0 | 0 | 2000 | 0 | 6 | 0 | 0 | 13129 | 9322 | 7016 | 3153 | 2 | 59 | 19813 | 3118 | 3814 | 15 | 56 | 61 | 2 | 28259 | 1000 | 15522 | 12443 | 13838 | 2000 | 2000 | 1000 | 28657 | 28655 | 28752 | 28651 | 28764 |
64004 | 28818 | 222 | 0 | 2 | 0 | 3 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 4598 | 28525 | 2 | 2 | 0 | 17470 | 5000 | 1000 | 2000 | 2000 | 1000 | 2000 | 2000 | 5000 | 21619 | 16000 | 4 | 0 | 0 | 21883 | 28353 | 28804 | 3 | 10 | 5000 | 2000 | 2000 | 5000 | 6000 | 28607 | 28626 | 1 | 1 | 61001 | 1000 | 1000 | 2000 | 0 | 6 | 0 | 2000 | 0 | 0 | 2 | 2000 | 0 | 0 | 0 | 0 | 13174 | 9493 | 7003 | 3155 | 2 | 60 | 19750 | 3174 | 3815 | 18 | 59 | 65 | 2 | 28196 | 1000 | 15167 | 12561 | 13568 | 2000 | 2000 | 1000 | 28660 | 28675 | 28591 | 28869 | 28694 |
64004 | 28736 | 222 | 0 | 1 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4907 | 28598 | 2 | 0 | 0 | 17879 | 5000 | 1000 | 2000 | 2000 | 1000 | 2000 | 2000 | 5000 | 21603 | 16000 | 7 | 0 | 0 | 21890 | 28465 | 28598 | 3 | 10 | 5000 | 2000 | 2000 | 5000 | 6000 | 28796 | 28714 | 1 | 1 | 61001 | 1000 | 1000 | 2004 | 0 | 0 | 0 | 2000 | 0 | 0 | 2 | 2000 | 0 | 6 | 0 | 0 | 13186 | 9182 | 7003 | 3192 | 2 | 59 | 19729 | 3210 | 3816 | 16 | 66 | 58 | 2 | 28261 | 1000 | 15108 | 12690 | 13456 | 2000 | 2000 | 1000 | 28628 | 28660 | 28794 | 28724 | 28583 |
64004 | 28650 | 223 | 0 | 2 | 0 | 2 | 0 | 1 | 1 | 3 | 1 | 0 | 0 | 4869 | 28609 | 2 | 0 | 0 | 17678 | 5000 | 1000 | 2000 | 2000 | 1000 | 2000 | 2000 | 5000 | 21624 | 16000 | 4 | 0 | 0 | 21799 | 28508 | 28648 | 7 | 10 | 5000 | 2000 | 2000 | 5000 | 6000 | 28617 | 28735 | 1 | 1 | 61001 | 1000 | 1000 | 2000 | 0 | 6 | 0 | 2002 | 0 | 0 | 0 | 2000 | 0 | 6 | 0 | 111 | 13282 | 9363 | 6963 | 3206 | 1 | 60 | 19638 | 3200 | 3815 | 16 | 63 | 63 | 2 | 28315 | 1000 | 15442 | 12570 | 13333 | 2000 | 2000 | 1000 | 28700 | 28681 | 28599 | 28763 | 28644 |
64004 | 28796 | 222 | 0 | 1 | 0 | 2 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 4645 | 28656 | 0 | 2 | 0 | 17653 | 5000 | 1000 | 2000 | 2000 | 1000 | 2000 | 2000 | 5000 | 21620 | 16000 | 6 | 0 | 0 | 21939 | 28396 | 28663 | 3 | 10 | 5000 | 2000 | 2000 | 5000 | 6000 | 28659 | 28661 | 1 | 1 | 61001 | 1000 | 1000 | 2000 | 0 | 6 | 0 | 2000 | 0 | 0 | 0 | 2000 | 0 | 6 | 0 | 0 | 13138 | 9615 | 7027 | 3215 | 2 | 59 | 19782 | 3088 | 3815 | 16 | 64 | 55 | 2 | 28184 | 1000 | 15708 | 12655 | 13673 | 2000 | 2000 | 1000 | 28666 | 28786 | 28681 | 28663 | 28629 |
64004 | 28736 | 223 | 0 | 2 | 0 | 3 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 4808 | 28511 | 2 | 0 | 0 | 17639 | 5000 | 1000 | 2000 | 2000 | 1000 | 2000 | 2000 | 5000 | 21623 | 16000 | 4 | 0 | 8 | 21928 | 28475 | 28693 | 3 | 10 | 5000 | 2000 | 2000 | 5000 | 6000 | 28676 | 28635 | 1 | 1 | 61001 | 1000 | 1000 | 2000 | 0 | 6 | 0 | 2002 | 0 | 0 | 0 | 2000 | 0 | 4 | 0 | 0 | 13321 | 9486 | 7006 | 3205 | 2 | 67 | 19721 | 3229 | 3819 | 15 | 64 | 64 | 2 | 28191 | 1000 | 15255 | 12544 | 14001 | 2000 | 2000 | 1000 | 28748 | 28813 | 28815 | 28796 | 28804 |
64004 | 28740 | 223 | 0 | 5 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 4773 | 28528 | 0 | 0 | 0 | 17644 | 5000 | 1000 | 2000 | 2000 | 1000 | 2000 | 2002 | 5000 | 21612 | 16000 | 2 | 0 | 0 | 21906 | 28558 | 28701 | 3 | 10 | 5000 | 2000 | 2000 | 5000 | 6000 | 28772 | 28634 | 1 | 1 | 61001 | 1000 | 1000 | 2000 | 0 | 4 | 0 | 2000 | 0 | 0 | 0 | 2000 | 0 | 6 | 0 | 0 | 13176 | 9583 | 7025 | 3172 | 2 | 64 | 19640 | 3314 | 3817 | 15 | 63 | 61 | 3 | 28228 | 1000 | 15329 | 12666 | 13437 | 2000 | 2000 | 1000 | 28556 | 28661 | 28630 | 28592 | 28782 |
64004 | 28763 | 223 | 0 | 3 | 0 | 5 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4779 | 28486 | 2 | 0 | 0 | 17595 | 5000 | 1000 | 2000 | 2000 | 1000 | 2000 | 2000 | 5000 | 21619 | 16000 | 3 | 0 | 0 | 21916 | 28589 | 28835 | 3 | 10 | 5000 | 2000 | 2000 | 5000 | 6000 | 28668 | 28747 | 1 | 1 | 61001 | 1000 | 1000 | 2000 | 0 | 0 | 0 | 2000 | 0 | 0 | 0 | 2000 | 0 | 4 | 0 | 0 | 13394 | 9581 | 7031 | 3222 | 3 | 64 | 19721 | 3221 | 3822 | 14 | 69 | 66 | 3 | 28242 | 1000 | 15559 | 12317 | 13574 | 2000 | 2000 | 1000 | 28830 | 28752 | 28818 | 28722 | 28650 |
64004 | 28694 | 223 | 0 | 2 | 0 | 4 | 0 | 4 | 0 | 24 | 1 | 0 | 0 | 4807 | 28603 | 2 | 2 | 0 | 17692 | 5000 | 1000 | 2000 | 2000 | 1000 | 2000 | 2000 | 5000 | 21623 | 16000 | 4 | 0 | 0 | 21782 | 28464 | 28798 | 3 | 10 | 5000 | 2000 | 2000 | 5000 | 6000 | 28649 | 28693 | 1 | 1 | 61001 | 1000 | 1000 | 2000 | 0 | 0 | 0 | 2000 | 0 | 0 | 0 | 2000 | 0 | 4 | 0 | 0 | 13172 | 9539 | 6995 | 3228 | 2 | 61 | 19825 | 3192 | 3812 | 23 | 65 | 60 | 2 | 28222 | 1000 | 15482 | 12670 | 13765 | 2000 | 2000 | 1000 | 28636 | 28762 | 28745 | 28664 | 28583 |
Count: 8
Code:
st3 { v0.4h, v1.4h, v2.4h }, [x6], x8 st3 { v0.4h, v1.4h, v2.4h }, [x6], x8 st3 { v0.4h, v1.4h, v2.4h }, [x6], x8 st3 { v0.4h, v1.4h, v2.4h }, [x6], x8 st3 { v0.4h, v1.4h, v2.4h }, [x6], x8 st3 { v0.4h, v1.4h, v2.4h }, [x6], x8 st3 { v0.4h, v1.4h, v2.4h }, [x6], x8 st3 { v0.4h, v1.4h, v2.4h }, [x6], x8
mov x7, x6 mov x8, x6 mov x9, x6 mov x10, x6 mov x11, x6 mov x12, x6 mov x13, x6 mov x8, 0
(fused SUBS/B.cc loop)
Result (median cycles for code divided by count): 1.0006
retire uop (01) | cycle (02) | 03 | mmu table walk data (08) | 09 | 18 | 19 | 1e | 1f | 22 | 23 | 37 | 3a | 3f | 46 | 49 | 4f | 51 | schedule uop (52) | schedule int uop (53) | schedule simd uop (54) | schedule ldst uop (55) | dispatch int uop (56) | dispatch simd uop (57) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | ldst uops in schedulers (5b) | 60 | 69 | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map simd uop (7e) | map int uop inputs (7f) | map ldst uop inputs (80) | map simd uop inputs (81) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int alu (97) | inst simd store (99) | inst ldst (9b) | 9f | l1d tlb access (a0) | l1d tlb miss (a1) | l1d cache miss st (a2) | a4 | st unit uop (a7) | l1d cache writeback (a8) | a9 | ac | af | bc | l1d cache miss st nonspec (c0) | branch cond mispred nonspec (c5) | cd | cf | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ? int output thing (e9) | ? ldst retires (ed) | ? simd retires (ee) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
320207 | 80058 | 621 | 0 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 2050 | 0 | 80030 | 16 | 16 | 0 | 25 | 405561 | 80100 | 166301 | 160000 | 80100 | 160000 | 160000 | 480499 | 2159008 | 1298085 | 0 | 80024 | 80045 | 80044 | 0 | 3 | 27 | 400100 | 200 | 160000 | 160000 | 200 | 400000 | 480000 | 80044 | 80045 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 160000 | 0 | 44 | 0 | 160002 | 0 | 0 | 2 | 160002 | 6 | 40 | 0 | 0 | 5109 | 1 | 17 | 1 | 1 | 80042 | 80000 | 160000 | 160000 | 80100 | 80046 | 80046 | 80046 | 80047 | 80046 |
320204 | 80045 | 620 | 0 | 0 | 0 | 0 | 21 | 3 | 0 | 0 | 7215 | 0 | 80033 | 0 | 0 | 0 | 25 | 405333 | 80100 | 165426 | 160000 | 80100 | 160000 | 160000 | 480499 | 2079751 | 1300749 | 0 | 80023 | 80044 | 80044 | 0 | 3 | 28 | 400100 | 200 | 160000 | 160000 | 200 | 400000 | 480000 | 80044 | 80044 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 160000 | 0 | 40 | 0 | 160002 | 0 | 0 | 2 | 160002 | 2 | 40 | 0 | 0 | 5109 | 1 | 17 | 1 | 1 | 80041 | 80000 | 160000 | 160000 | 80100 | 80046 | 80045 | 80046 | 80046 | 80046 |
320204 | 80118 | 621 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | 0 | 6272 | 0 | 80030 | 16 | 16 | 0 | 25 | 404507 | 80100 | 164856 | 160000 | 80100 | 160000 | 160000 | 480499 | 2078849 | 1296149 | 0 | 80024 | 80548 | 80045 | 0 | 3 | 27 | 400100 | 200 | 160000 | 160000 | 200 | 400000 | 480000 | 80046 | 80045 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 160000 | 0 | 40 | 0 | 160002 | 1 | 0 | 2 | 160002 | 2 | 40 | 0 | 0 | 5109 | 1 | 17 | 1 | 1 | 80042 | 80000 | 160000 | 160000 | 80100 | 80047 | 80046 | 80046 | 80046 | 80046 |
320204 | 80046 | 621 | 0 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 5772 | 0 | 80028 | 16 | 16 | 0 | 25 | 405665 | 80100 | 163734 | 160000 | 80100 | 160000 | 160000 | 480499 | 2157016 | 1306387 | 0 | 80023 | 80044 | 80045 | 0 | 3 | 25 | 400100 | 200 | 160000 | 160000 | 200 | 400000 | 480000 | 80044 | 80054 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 160000 | 0 | 40 | 0 | 160002 | 1 | 0 | 2 | 160002 | 2 | 42 | 0 | 0 | 5109 | 2 | 17 | 1 | 1 | 80045 | 80000 | 160000 | 160000 | 80100 | 80047 | 80046 | 80045 | 80046 | 80045 |
320204 | 80044 | 620 | 0 | 0 | 0 | 0 | 9 | 3 | 0 | 0 | 5416 | 0 | 80478 | 16 | 16 | 255 | 93 | 404854 | 80279 | 167933 | 160180 | 80277 | 160354 | 160324 | 481555 | 2797531 | 1305013 | 1 | 80476 | 80228 | 80047 | 0 | 3 | 26 | 400100 | 200 | 160000 | 160000 | 200 | 400000 | 480000 | 80044 | 80045 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 160000 | 0 | 44 | 0 | 160002 | 1 | 0 | 11 | 160004 | 14 | 40 | 0 | 0 | 5109 | 1 | 17 | 1 | 1 | 80041 | 80000 | 160000 | 160000 | 80100 | 80045 | 80046 | 80047 | 80045 | 80045 |
320204 | 80044 | 621 | 0 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 4068 | 0 | 80029 | 16 | 16 | 0 | 25 | 404970 | 80100 | 166865 | 160000 | 80100 | 160000 | 160000 | 480499 | 2306429 | 1287263 | 0 | 80024 | 80045 | 80045 | 0 | 3 | 27 | 400100 | 200 | 160000 | 160000 | 200 | 400000 | 480000 | 80044 | 80045 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 160000 | 0 | 40 | 0 | 160002 | 0 | 0 | 2 | 160002 | 2 | 0 | 0 | 0 | 5109 | 1 | 17 | 1 | 1 | 80042 | 80000 | 160000 | 160000 | 80100 | 80046 | 80055 | 80045 | 80046 | 80045 |
320204 | 80043 | 621 | 0 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 5503 | 0 | 80030 | 16 | 16 | 0 | 25 | 404180 | 80100 | 163568 | 160000 | 80100 | 160000 | 160000 | 480499 | 2079212 | 1290601 | 0 | 80024 | 80045 | 80045 | 0 | 3 | 27 | 400100 | 200 | 160000 | 160000 | 200 | 400000 | 480000 | 80044 | 80044 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 160000 | 0 | 0 | 0 | 160002 | 0 | 0 | 10 | 160002 | 2 | 40 | 0 | 0 | 5109 | 1 | 17 | 1 | 1 | 80043 | 80000 | 160000 | 160000 | 80100 | 80046 | 80045 | 80045 | 80046 | 80046 |
320204 | 80045 | 620 | 0 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 4358 | 0 | 80029 | 16 | 16 | 0 | 25 | 405757 | 80100 | 165121 | 160000 | 80100 | 160000 | 160000 | 480499 | 2079508 | 1297231 | 0 | 80024 | 80046 | 80045 | 0 | 3 | 27 | 400100 | 200 | 160000 | 160000 | 200 | 400000 | 480000 | 80044 | 80043 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 160000 | 0 | 40 | 0 | 160002 | 1 | 0 | 2 | 160000 | 2 | 40 | 0 | 0 | 5109 | 1 | 17 | 1 | 1 | 80043 | 80000 | 160000 | 160000 | 80100 | 80046 | 80045 | 80053 | 80045 | 80046 |
320204 | 80045 | 620 | 0 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 5813 | 0 | 80029 | 16 | 16 | 0 | 25 | 403939 | 80100 | 165862 | 160000 | 80100 | 160000 | 160000 | 480499 | 2079404 | 1293490 | 0 | 80025 | 80044 | 80044 | 0 | 3 | 26 | 400100 | 200 | 160000 | 160000 | 200 | 400000 | 480000 | 80045 | 80045 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 160000 | 0 | 40 | 0 | 160002 | 1 | 0 | 2 | 160000 | 2 | 40 | 0 | 0 | 5109 | 1 | 17 | 1 | 1 | 80042 | 80000 | 160000 | 160000 | 80100 | 80047 | 80046 | 80047 | 80045 | 80045 |
320204 | 80046 | 620 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4411 | 0 | 80029 | 16 | 16 | 0 | 25 | 404469 | 80100 | 165251 | 160000 | 80100 | 160000 | 160000 | 480499 | 2078945 | 1297987 | 0 | 80024 | 80045 | 80044 | 0 | 3 | 27 | 400100 | 200 | 160000 | 160000 | 200 | 400000 | 480000 | 80044 | 80045 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 160000 | 0 | 40 | 0 | 160000 | 0 | 0 | 2 | 160002 | 2 | 0 | 0 | 0 | 5109 | 1 | 17 | 1 | 1 | 80042 | 80000 | 160000 | 160000 | 80100 | 80046 | 80045 | 80045 | 80046 | 80046 |
Result (median cycles for code divided by count): 1.0007
retire uop (01) | cycle (02) | 03 | l1d tlb fill (05) | mmu table walk data (08) | 09 | l2 tlb miss data (0b) | 18 | 19 | 1e | 1f | 22 | 24 | 37 | 3a | 3f | 46 | 49 | 4f | 51 | schedule uop (52) | schedule int uop (53) | schedule simd uop (54) | schedule ldst uop (55) | dispatch int uop (56) | dispatch simd uop (57) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | ldst uops in schedulers (5b) | 60 | 69 | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map simd uop (7e) | map int uop inputs (7f) | map ldst uop inputs (80) | map simd uop inputs (81) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int alu (97) | inst simd store (99) | inst ldst (9b) | 9f | l1d tlb access (a0) | l1d tlb miss (a1) | l1d cache miss st (a2) | a4 | ld unit uop (a6) | st unit uop (a7) | l1d cache writeback (a8) | a9 | ac | af | bc | l1d cache miss st nonspec (c0) | l1d tlb miss nonspec (c1) | c2 | cf | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ? int output thing (e9) | ea | ? ldst retires (ed) | ? simd retires (ee) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
320027 | 80053 | 620 | 1 | 1 | 0 | 1 | 0 | 0 | 21 | 17 | 0 | 0 | 5823 | 2 | 80037 | 16 | 16 | 0 | 25 | 405959 | 80010 | 164762 | 160000 | 80010 | 160000 | 160000 | 480049 | 2799774 | 1304131 | 0 | 80027 | 80052 | 80051 | 0 | 3 | 35 | 400010 | 20 | 160000 | 160000 | 20 | 400000 | 480000 | 80053 | 80053 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 160012 | 12 | 46 | 0 | 0 | 160014 | 0 | 0 | 14 | 160002 | 14 | 46 | 12 | 0 | 5019 | 3 | 17 | 5 | 5 | 80050 | 80000 | 0 | 160000 | 160000 | 80010 | 80052 | 80050 | 80053 | 80052 | 80054 |
320024 | 80049 | 620 | 1 | 1 | 0 | 0 | 0 | 0 | 9 | 15 | 0 | 0 | 3137 | 2 | 80037 | 16 | 16 | 0 | 25 | 405253 | 80010 | 164233 | 160000 | 80069 | 160000 | 160000 | 480049 | 2639707 | 1304287 | 0 | 80023 | 80049 | 80049 | 0 | 3 | 33 | 400010 | 20 | 160000 | 160000 | 20 | 400000 | 480000 | 80051 | 80049 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 160013 | 12 | 46 | 0 | 0 | 160012 | 1 | 0 | 14 | 160002 | 14 | 46 | 12 | 1 | 5019 | 3 | 17 | 3 | 3 | 80049 | 80000 | 0 | 160000 | 160000 | 80010 | 80053 | 80053 | 80053 | 80054 | 80054 |
320024 | 80053 | 622 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 15 | 0 | 0 | 6015 | 2 | 80037 | 0 | 16 | 0 | 25 | 405696 | 80010 | 164705 | 160000 | 80010 | 160000 | 160000 | 480049 | 2479756 | 1296790 | 0 | 80027 | 80053 | 80053 | 0 | 3 | 34 | 400010 | 20 | 160000 | 160000 | 20 | 400000 | 480000 | 80053 | 80053 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 160012 | 12 | 46 | 0 | 2 | 160014 | 0 | 0 | 14 | 160002 | 14 | 46 | 12 | 0 | 5019 | 3 | 17 | 3 | 3 | 80050 | 80000 | 0 | 160000 | 160000 | 80010 | 80050 | 80050 | 80052 | 80051 | 80051 |
320024 | 80050 | 620 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 12 | 0 | 0 | 5681 | 2 | 80036 | 16 | 16 | 0 | 25 | 405171 | 80010 | 164699 | 160000 | 80010 | 160000 | 160000 | 480049 | 2559843 | 1305857 | 0 | 80028 | 80050 | 80137 | 0 | 3 | 35 | 400010 | 20 | 160000 | 160000 | 20 | 400000 | 480000 | 80052 | 80053 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 160012 | 13 | 46 | 0 | 0 | 160074 | 0 | 0 | 16 | 160002 | 14 | 44 | 12 | 0 | 5019 | 4 | 17 | 4 | 4 | 80049 | 80000 | 0 | 160000 | 160000 | 80010 | 80053 | 80053 | 80051 | 80052 | 80053 |
320024 | 80051 | 620 | 1 | 0 | 0 | 1 | 0 | 0 | 21 | 17 | 0 | 0 | 4699 | 2 | 80035 | 16 | 16 | 0 | 25 | 407399 | 80010 | 165976 | 160000 | 80010 | 160000 | 160000 | 480049 | 2559799 | 1295520 | 0 | 80025 | 80052 | 80053 | 0 | 3 | 34 | 400010 | 20 | 160000 | 160000 | 20 | 400000 | 480000 | 80050 | 80052 | 2 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 160012 | 12 | 44 | 0 | 0 | 160014 | 1 | 0 | 14 | 160000 | 14 | 44 | 12 | 1 | 5019 | 4 | 17 | 3 | 4 | 80049 | 80000 | 0 | 160000 | 160000 | 80010 | 80053 | 80054 | 80052 | 80051 | 80053 |
320024 | 80051 | 620 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 15 | 0 | 0 | 2353 | 2 | 80038 | 16 | 16 | 0 | 25 | 404809 | 80010 | 164374 | 160000 | 80010 | 160000 | 160000 | 480049 | 2799719 | 1296793 | 0 | 80027 | 80052 | 80052 | 0 | 3 | 35 | 400295 | 20 | 160000 | 160000 | 20 | 400000 | 480000 | 80053 | 80052 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 160012 | 12 | 46 | 0 | 0 | 160014 | 0 | 0 | 15 | 160002 | 14 | 0 | 12 | 1 | 5019 | 5 | 17 | 4 | 4 | 80046 | 80000 | 0 | 160000 | 160000 | 80010 | 80051 | 80054 | 80053 | 80053 | 80056 |
320024 | 80052 | 621 | 1 | 0 | 2 | 0 | 0 | 0 | 0 | 17 | 0 | 0 | 1621 | 2 | 80036 | 16 | 16 | 0 | 25 | 405458 | 80010 | 165542 | 160000 | 80010 | 160000 | 160000 | 480049 | 2559737 | 1294228 | 0 | 80027 | 80052 | 80053 | 0 | 3 | 35 | 400010 | 20 | 160000 | 160000 | 20 | 400000 | 480000 | 80222 | 80053 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 160012 | 13 | 46 | 0 | 0 | 160014 | 0 | 0 | 15 | 160002 | 14 | 46 | 12 | 0 | 5019 | 4 | 17 | 6 | 5 | 80049 | 80000 | 0 | 160000 | 160000 | 80010 | 80051 | 80053 | 80054 | 80054 | 80055 |
320024 | 80053 | 620 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 15 | 0 | 0 | 4848 | 2 | 80038 | 0 | 16 | 0 | 25 | 405494 | 80010 | 164986 | 160000 | 80010 | 160000 | 160000 | 480049 | 2559773 | 1317633 | 0 | 80037 | 80052 | 80053 | 0 | 3 | 32 | 400010 | 20 | 160000 | 160000 | 20 | 400000 | 480000 | 80053 | 80053 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 160012 | 12 | 44 | 0 | 0 | 160014 | 0 | 0 | 15 | 160000 | 12 | 0 | 12 | 0 | 5019 | 4 | 17 | 4 | 4 | 80049 | 80000 | 0 | 160000 | 160000 | 80010 | 80054 | 80053 | 80054 | 80053 | 80054 |
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