Apple Microarchitecture Research by Dougall Johnson M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions M1/A14 E-core (Icestorm): Overview | Base Instructions | SIMD and FP Instructions
Code:
st3 { v0.8b, v1.8b, v2.8b }, [x6], x8 nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop
mov x0, 0 mov x8, 0
(no loop instructions)
Retires (minus 60 nops): 4.000
Issues: 5.000
Integer unit issues: 1.000
Load/store unit issues: 2.000
SIMD/FP unit issues: 2.000
retire uop (01) | cycle (02) | 03 | mmu table walk instruction (07) | mmu table walk data (08) | 09 | l2 tlb miss instruction (0a) | l2 tlb miss data (0b) | 18 | 19 | 1e | 1f | 22 | 24 | 3a | 3f | 49 | 51 | schedule uop (52) | schedule int uop (53) | schedule simd uop (54) | schedule ldst uop (55) | dispatch int uop (56) | dispatch simd uop (57) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | ldst uops in schedulers (5b) | 5e | 5f | 69 | 6d | 6e | map rewind (75) | map stall (76) | dispatch uop (78) | map ldst uop (7d) | map simd uop (7e) | map ldst uop inputs (80) | map simd uop inputs (81) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst simd store (99) | inst ldst (9b) | l1d tlb access (a0) | l1d tlb miss (a1) | l1d cache miss st (a2) | ld unit uop (a6) | st unit uop (a7) | l1d cache writeback (a8) | a9 | ac | af | l1d cache miss st nonspec (c0) | c2 | c9 | cf | d0 | d2 | l1i cache miss demand (d3) | l1i tlb miss demand (d4) | d5 | map dispatch bubble (d6) | d9 | da | db | dd | fetch restart (de) | e0 | ? int output thing (e9) | ea | eb | ec | ? ldst retires (ed) | ? simd retires (ee) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
64007 | 29500 | 237 | 24 | 0 | 0 | 30 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | 4647 | 29334 | 0 | 18460 | 5000 | 1000 | 2000 | 2000 | 1000 | 2000 | 2000 | 5000 | 21622 | 16000 | 0 | 2 | 21835 | 29306 | 29533 | 3 | 10 | 5000 | 2000 | 2000 | 5000 | 6000 | 29530 | 29354 | 1 | 1 | 61001 | 1000 | 1000 | 2000 | 0 | 4 | 0 | 2000 | 0 | 0 | 0 | 2000 | 6 | 0 | 0 | 13153 | 9419 | 6915 | 3182 | 10 | 61 | 20439 | 3302 | 3814 | 20 | 64 | 68 | 28707 | 1000 | 16181 | 13113 | 14397 | 2000 | 2000 | 1000 | 29515 | 29495 | 29456 | 29430 | 29396 |
64004 | 29494 | 237 | 23 | 0 | 0 | 29 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 4721 | 29257 | 0 | 18349 | 5000 | 1000 | 2000 | 2000 | 1000 | 2000 | 2000 | 5000 | 21618 | 16000 | 0 | 2 | 21833 | 29023 | 29512 | 3 | 10 | 5000 | 2000 | 2000 | 5000 | 6000 | 29374 | 29297 | 1 | 1 | 61001 | 1000 | 1000 | 2000 | 0 | 4 | 0 | 2000 | 0 | 0 | 3 | 2000 | 4 | 0 | 0 | 13306 | 9391 | 6943 | 3170 | 16 | 61 | 20421 | 3269 | 3816 | 7 | 64 | 67 | 28737 | 1000 | 16382 | 13176 | 14483 | 2000 | 2000 | 1000 | 29465 | 29546 | 29514 | 29541 | 29396 |
64004 | 29435 | 237 | 20 | 0 | 0 | 33 | 0 | 0 | 0 | 18 | 0 | 1 | 0 | 4561 | 29249 | 0 | 18306 | 5000 | 1000 | 2000 | 2000 | 1000 | 2000 | 2000 | 5000 | 21602 | 16000 | 0 | 0 | 21870 | 29149 | 29531 | 3 | 10 | 5000 | 2000 | 2000 | 5000 | 6000 | 29391 | 29402 | 1 | 1 | 61001 | 1000 | 1000 | 2000 | 0 | 4 | 0 | 2000 | 0 | 0 | 0 | 2000 | 0 | 0 | 0 | 13273 | 9382 | 6973 | 3161 | 11 | 60 | 20550 | 3295 | 3819 | 14 | 65 | 64 | 28693 | 1000 | 16148 | 13155 | 14379 | 2000 | 2000 | 1000 | 29370 | 29360 | 29472 | 29475 | 29473 |
64004 | 29396 | 236 | 23 | 0 | 0 | 31 | 0 | 0 | 0 | 9 | 1 | 0 | 0 | 4666 | 29280 | 0 | 18315 | 5000 | 1000 | 2000 | 2000 | 1000 | 2000 | 2000 | 5000 | 21620 | 16000 | 0 | 3 | 21780 | 29176 | 29384 | 3 | 10 | 5000 | 2000 | 2000 | 5000 | 6000 | 29414 | 29475 | 1 | 1 | 61001 | 1000 | 1000 | 2000 | 0 | 4 | 0 | 2000 | 0 | 0 | 0 | 2000 | 4 | 0 | 0 | 13160 | 9438 | 6949 | 3138 | 13 | 63 | 20487 | 3255 | 3820 | 23 | 75 | 69 | 28814 | 1000 | 16103 | 13219 | 14382 | 2000 | 2000 | 1000 | 29537 | 29316 | 29541 | 29490 | 29563 |
64004 | 29435 | 236 | 26 | 0 | 0 | 24 | 0 | 0 | 0 | 9 | 0 | 0 | 0 | 4684 | 29253 | 0 | 18345 | 5000 | 1000 | 2000 | 2000 | 1000 | 2000 | 2000 | 5000 | 21616 | 16000 | 0 | 0 | 21816 | 29163 | 29424 | 3 | 10 | 5000 | 2000 | 2000 | 5000 | 6000 | 29345 | 29356 | 1 | 1 | 61001 | 1000 | 1000 | 2000 | 0 | 0 | 0 | 2000 | 0 | 0 | 0 | 2000 | 4 | 0 | 0 | 13305 | 9280 | 6908 | 3168 | 11 | 63 | 20410 | 3291 | 3819 | 21 | 67 | 60 | 28771 | 1000 | 16051 | 13069 | 14109 | 2000 | 2000 | 1000 | 29492 | 29515 | 29433 | 29483 | 29432 |
64004 | 29454 | 237 | 23 | 0 | 0 | 25 | 0 | 0 | 0 | 51 | 0 | 0 | 0 | 4755 | 29257 | 0 | 18389 | 5000 | 1000 | 2000 | 2000 | 1000 | 2000 | 2000 | 5000 | 21604 | 16000 | 0 | 0 | 21856 | 29114 | 29577 | 3 | 10 | 5000 | 2000 | 2000 | 5000 | 6000 | 29435 | 29397 | 1 | 1 | 61001 | 1000 | 1000 | 2000 | 0 | 0 | 0 | 2000 | 0 | 0 | 0 | 2000 | 6 | 0 | 0 | 13320 | 9422 | 6981 | 3138 | 7 | 64 | 20432 | 3280 | 3817 | 12 | 64 | 59 | 28823 | 1000 | 16328 | 13176 | 14345 | 2000 | 2000 | 1000 | 29494 | 29488 | 29577 | 29568 | 29341 |
64004 | 29472 | 237 | 24 | 0 | 0 | 23 | 0 | 0 | 0 | 15 | 0 | 0 | 0 | 4662 | 29200 | 0 | 18445 | 5000 | 1000 | 2000 | 2000 | 1000 | 2000 | 2000 | 5000 | 21610 | 16000 | 0 | 3 | 21849 | 29066 | 29537 | 3 | 10 | 5000 | 2000 | 2000 | 5000 | 6000 | 29392 | 29312 | 1 | 1 | 61001 | 1000 | 1000 | 2000 | 0 | 4 | 0 | 2000 | 0 | 0 | 0 | 2000 | 4 | 0 | 0 | 13201 | 9296 | 6950 | 3182 | 11 | 66 | 20364 | 3228 | 3820 | 16 | 59 | 62 | 28800 | 1000 | 16318 | 13225 | 14568 | 2000 | 2000 | 1000 | 29496 | 29482 | 29512 | 29541 | 29507 |
64004 | 29502 | 236 | 26 | 0 | 0 | 29 | 0 | 0 | 0 | 9 | 1 | 0 | 0 | 4618 | 29226 | 0 | 18235 | 5000 | 1000 | 2000 | 2000 | 1000 | 2000 | 2000 | 5000 | 21618 | 16000 | 0 | 3 | 21808 | 29190 | 29419 | 3 | 10 | 5000 | 2000 | 2000 | 5000 | 6000 | 29374 | 29297 | 1 | 1 | 61002 | 1000 | 1000 | 2000 | 0 | 4 | 0 | 2000 | 0 | 0 | 0 | 2000 | 4 | 0 | 0 | 13139 | 9510 | 6932 | 3196 | 6 | 63 | 20372 | 3266 | 3815 | 14 | 68 | 64 | 28796 | 1000 | 15958 | 13324 | 14540 | 2000 | 2000 | 1000 | 29527 | 29634 | 29524 | 29561 | 29405 |
64004 | 29501 | 237 | 23 | 0 | 0 | 32 | 0 | 0 | 0 | 9 | 2 | 0 | 0 | 4569 | 29275 | 0 | 18378 | 5000 | 1000 | 2000 | 2000 | 1000 | 2000 | 2000 | 5000 | 21610 | 16000 | 0 | 0 | 21858 | 29192 | 29445 | 3 | 10 | 5000 | 2000 | 2000 | 5000 | 6000 | 29339 | 29387 | 1 | 1 | 61001 | 1000 | 1000 | 2000 | 0 | 4 | 0 | 2000 | 0 | 0 | 0 | 2000 | 4 | 0 | 0 | 13091 | 9316 | 6938 | 3170 | 11 | 65 | 20535 | 3239 | 3819 | 23 | 66 | 60 | 28794 | 1000 | 15967 | 13153 | 14433 | 2000 | 2000 | 1000 | 29395 | 29509 | 29531 | 29520 | 29360 |
64004 | 29510 | 237 | 29 | 0 | 0 | 26 | 0 | 0 | 0 | 9 | 1 | 0 | 0 | 4801 | 29179 | 0 | 18394 | 5000 | 1000 | 2000 | 2000 | 1000 | 2000 | 2000 | 5000 | 21607 | 16000 | 0 | 0 | 21839 | 29244 | 29532 | 3 | 10 | 5000 | 2000 | 2000 | 5000 | 6000 | 29394 | 29373 | 1 | 1 | 61001 | 1000 | 1000 | 2000 | 0 | 0 | 0 | 2000 | 0 | 0 | 0 | 2000 | 4 | 0 | 0 | 12902 | 9500 | 6908 | 3124 | 17 | 68 | 20405 | 3270 | 3823 | 12 | 65 | 62 | 28770 | 1000 | 16332 | 13014 | 14604 | 2000 | 2000 | 1000 | 29429 | 29492 | 29423 | 29456 | 29482 |
Count: 8
Code:
st3 { v0.8b, v1.8b, v2.8b }, [x6], x8 st3 { v0.8b, v1.8b, v2.8b }, [x6], x8 st3 { v0.8b, v1.8b, v2.8b }, [x6], x8 st3 { v0.8b, v1.8b, v2.8b }, [x6], x8 st3 { v0.8b, v1.8b, v2.8b }, [x6], x8 st3 { v0.8b, v1.8b, v2.8b }, [x6], x8 st3 { v0.8b, v1.8b, v2.8b }, [x6], x8 st3 { v0.8b, v1.8b, v2.8b }, [x6], x8
mov x7, x6 mov x8, x6 mov x9, x6 mov x10, x6 mov x11, x6 mov x12, x6 mov x13, x6 mov x8, 0
(fused SUBS/B.cc loop)
Result (median cycles for code divided by count): 1.0006
retire uop (01) | cycle (02) | 03 | l1d tlb fill (05) | mmu table walk data (08) | 09 | l2 tlb miss instruction (0a) | l2 tlb miss data (0b) | 0e | 18 | 19 | 1e | 1f | 23 | 37 | 3a | 3f | 46 | 49 | 4f | 51 | schedule uop (52) | schedule int uop (53) | schedule simd uop (54) | schedule ldst uop (55) | dispatch int uop (56) | dispatch simd uop (57) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | ldst uops in schedulers (5b) | 60 | 69 | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map simd uop (7e) | map int uop inputs (7f) | map ldst uop inputs (80) | map simd uop inputs (81) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int alu (97) | inst simd store (99) | inst ldst (9b) | 9f | l1d tlb access (a0) | l1d tlb miss (a1) | l1d cache miss st (a2) | a4 | ld unit uop (a6) | st unit uop (a7) | l1d cache writeback (a8) | a9 | ac | af | bc | l1d cache miss st nonspec (c0) | l1d tlb miss nonspec (c1) | c2 | cf | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ? int output thing (e9) | eb | ? ldst retires (ed) | ? simd retires (ee) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
320207 | 80071 | 621 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 12 | 15 | 0 | 5981 | 2 | 80035 | 0 | 0 | 0 | 25 | 408329 | 80100 | 164393 | 160000 | 80100 | 160000 | 160000 | 481907 | 2319939 | 1301571 | 0 | 80025 | 80050 | 80050 | 0 | 7 | 31 | 400100 | 200 | 160000 | 160000 | 200 | 400000 | 480000 | 80241 | 80445 | 2 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 160012 | 12 | 38 | 0 | 0 | 161034 | 1 | 0 | 15 | 160002 | 14 | 38 | 0 | 1 | 5109 | 1 | 17 | 1 | 1 | 80047 | 80000 | 0 | 160000 | 160000 | 80100 | 80051 | 80052 | 80050 | 80059 | 80051 |
320204 | 80050 | 620 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 15 | 0 | 1943 | 2 | 80035 | 0 | 16 | 1 | 25 | 405235 | 80100 | 164007 | 160000 | 80100 | 160000 | 160000 | 480499 | 3679430 | 1289400 | 0 | 80025 | 80051 | 80050 | 0 | 3 | 31 | 400100 | 200 | 160000 | 160000 | 200 | 400000 | 480000 | 80216 | 80050 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 160012 | 12 | 38 | 0 | 1 | 160014 | 1 | 0 | 15 | 160002 | 14 | 38 | 12 | 0 | 5109 | 1 | 17 | 1 | 1 | 80048 | 80000 | 0 | 160000 | 160000 | 80100 | 80063 | 80050 | 80050 | 80062 | 80051 |
320204 | 80050 | 620 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 15 | 0 | 1218 | 2 | 80046 | 16 | 0 | 0 | 25 | 403435 | 80100 | 164735 | 160000 | 80100 | 160000 | 160000 | 480499 | 2279797 | 1295316 | 0 | 80023 | 80045 | 80050 | 0 | 3 | 32 | 400100 | 200 | 160000 | 160000 | 200 | 400000 | 480000 | 80051 | 80049 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 160013 | 0 | 38 | 0 | 1 | 160014 | 0 | 1 | 14 | 160000 | 12 | 38 | 12 | 0 | 5109 | 1 | 17 | 1 | 1 | 80045 | 80000 | 0 | 160000 | 160000 | 80100 | 80063 | 80052 | 80051 | 80060 | 80050 |
320204 | 80050 | 621 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 6 | 12 | 0 | 13 | 2 | 80032 | 16 | 15 | 2 | 25 | 400108 | 80100 | 160009 | 160000 | 80100 | 160000 | 160000 | 480499 | 2319939 | 1298756 | 0 | 80025 | 80050 | 80051 | 0 | 3 | 31 | 400100 | 200 | 160000 | 160000 | 200 | 400000 | 480000 | 80049 | 80049 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 160013 | 12 | 38 | 0 | 1 | 160012 | 0 | 1 | 279 | 160000 | 14 | 38 | 12 | 0 | 5109 | 1 | 17 | 1 | 1 | 80058 | 80000 | 0 | 160000 | 160000 | 80100 | 80051 | 80062 | 80051 | 80050 | 80051 |
320204 | 80061 | 620 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 18 | 0 | 4420 | 2 | 80047 | 16 | 16 | 0 | 25 | 402850 | 80100 | 164042 | 160000 | 80100 | 160000 | 160000 | 480499 | 2319939 | 1297912 | 0 | 80025 | 80051 | 80052 | 0 | 3 | 40 | 400100 | 200 | 160000 | 160000 | 200 | 400000 | 480000 | 80044 | 80058 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 160013 | 12 | 32 | 0 | 2 | 160014 | 0 | 0 | 185 | 160002 | 14 | 38 | 12 | 1 | 5109 | 1 | 17 | 1 | 1 | 80046 | 80000 | 0 | 160000 | 160000 | 80100 | 80051 | 80062 | 80050 | 80062 | 80052 |
320204 | 80702 | 634 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 13 | 0 | 4584 | 2 | 80042 | 16 | 16 | 0 | 25 | 404257 | 80100 | 166064 | 160000 | 80100 | 160000 | 160432 | 480499 | 3686258 | 1298223 | 0 | 80025 | 80051 | 80050 | 0 | 3 | 32 | 400100 | 200 | 160120 | 160000 | 200 | 400000 | 480000 | 80061 | 80062 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 160013 | 13 | 38 | 0 | 1 | 160014 | 1 | 1 | 306 | 160002 | 14 | 38 | 0 | 1 | 5109 | 1 | 17 | 1 | 1 | 80047 | 80000 | 0 | 160000 | 160000 | 80100 | 80051 | 80051 | 80062 | 80050 | 80050 |
320204 | 80050 | 620 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 12 | 15 | 0 | 1469 | 2 | 80035 | 16 | 16 | 0 | 25 | 406393 | 80100 | 163996 | 160000 | 80100 | 160000 | 160000 | 480499 | 2399916 | 1291360 | 0 | 80025 | 80049 | 80051 | 0 | 3 | 43 | 400100 | 200 | 160000 | 160000 | 200 | 400000 | 480000 | 80049 | 80062 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 160013 | 13 | 38 | 0 | 1 | 160014 | 0 | 2 | 15 | 160000 | 14 | 0 | 12 | 1 | 5109 | 1 | 17 | 1 | 1 | 80046 | 80000 | 0 | 160000 | 160000 | 80100 | 80050 | 80050 | 80049 | 80060 | 80060 |
320204 | 80049 | 620 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 13 | 0 | 2426 | 2 | 80035 | 16 | 16 | 0 | 25 | 404214 | 80100 | 160019 | 160000 | 80100 | 160000 | 160000 | 480498 | 3599288 | 1295271 | 0 | 80025 | 80049 | 80051 | 0 | 3 | 32 | 400100 | 200 | 160000 | 160000 | 200 | 400000 | 480000 | 80062 | 80057 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 160012 | 13 | 0 | 0 | 0 | 160014 | 0 | 1 | 188 | 160002 | 12 | 38 | 12 | 0 | 5109 | 1 | 17 | 1 | 1 | 80048 | 80000 | 0 | 160000 | 160000 | 80100 | 80050 | 80046 | 80051 | 80062 | 80050 |
320204 | 80050 | 621 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 16 | 0 | 2913 | 2 | 80035 | 16 | 0 | 0 | 25 | 406236 | 80100 | 165549 | 160000 | 80100 | 160000 | 160000 | 480499 | 3679406 | 1287342 | 1 | 80025 | 80057 | 80062 | 0 | 3 | 31 | 400100 | 200 | 160000 | 160000 | 200 | 400000 | 480000 | 80050 | 80048 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 160012 | 13 | 38 | 3 | 0 | 160014 | 1 | 1 | 300 | 160002 | 14 | 38 | 12 | 0 | 5109 | 1 | 17 | 1 | 1 | 80055 | 80000 | 0 | 160000 | 160000 | 80100 | 80050 | 80062 | 80051 | 80051 | 80052 |
320204 | 80059 | 620 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 16 | 0 | 11 | 2 | 80035 | 16 | 16 | 2 | 25 | 402529 | 80100 | 166166 | 160000 | 80100 | 160000 | 160000 | 480499 | 2235171 | 1289165 | 1 | 80024 | 80061 | 80059 | 0 | 3 | 32 | 400100 | 200 | 160000 | 160000 | 200 | 400000 | 480000 | 80051 | 80046 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 160013 | 13 | 38 | 0 | 1 | 160000 | 0 | 0 | 14 | 160002 | 14 | 0 | 12 | 0 | 5109 | 1 | 17 | 1 | 1 | 80047 | 80000 | 0 | 160000 | 160000 | 80100 | 80062 | 80051 | 80062 | 80051 | 80063 |
Result (median cycles for code divided by count): 1.0006
retire uop (01) | cycle (02) | 03 | l1d tlb fill (05) | mmu table walk data (08) | 09 | l2 tlb miss data (0b) | 18 | 19 | 1e | 1f | 22 | 23 | 24 | 37 | 3a | 3f | 46 | 49 | 4f | 51 | schedule uop (52) | schedule int uop (53) | schedule simd uop (54) | schedule ldst uop (55) | dispatch int uop (56) | dispatch simd uop (57) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | ldst uops in schedulers (5b) | 60 | 69 | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map simd uop (7e) | map int uop inputs (7f) | map ldst uop inputs (80) | map simd uop inputs (81) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int alu (97) | inst simd store (99) | inst ldst (9b) | 9f | l1d tlb access (a0) | l1d tlb miss (a1) | l1d cache miss st (a2) | a4 | ld unit uop (a6) | st unit uop (a7) | l1d cache writeback (a8) | a9 | ac | af | bc | l1d cache miss st nonspec (c0) | l1d tlb miss nonspec (c1) | c2 | cd | cf | d0 | l1i cache miss demand (d3) | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | e7 | ? int output thing (e9) | ? ldst retires (ed) | ? simd retires (ee) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
320027 | 80060 | 621 | 1 | 0 | 0 | 2 | 0 | 0 | 6 | 15 | 0 | 0 | 0 | 2447 | 2 | 80032 | 0 | 16 | 0 | 25 | 404915 | 80010 | 162665 | 160000 | 80010 | 160000 | 160000 | 480049 | 2159278 | 1294807 | 0 | 80024 | 80219 | 80049 | 0 | 3 | 32 | 400010 | 20 | 160000 | 160000 | 20 | 400000 | 480000 | 80050 | 80061 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 160000 | 0 | 0 | 0 | 1 | 160002 | 0 | 1 | 17 | 160000 | 2 | 38 | 12 | 0 | 0 | 5019 | 0 | 0 | 3 | 17 | 3 | 3 | 80042 | 0 | 80000 | 160000 | 160000 | 80010 | 80051 | 80046 | 80046 | 80046 | 80046 |
320024 | 80045 | 620 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | 4998 | 0 | 80036 | 0 | 0 | 0 | 25 | 400018 | 80010 | 160008 | 160000 | 80010 | 160000 | 160000 | 480049 | 2639885 | 1288746 | 0 | 80025 | 80045 | 80050 | 0 | 3 | 32 | 400010 | 20 | 160000 | 160000 | 20 | 400000 | 480000 | 80044 | 80050 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 160061 | 0 | 32 | 0 | 0 | 160002 | 0 | 0 | 11 | 160002 | 2 | 32 | 0 | 0 | 0 | 5019 | 0 | 0 | 3 | 17 | 3 | 3 | 80046 | 0 | 80000 | 160000 | 160000 | 80010 | 80046 | 80050 | 80046 | 80046 | 80047 |
320024 | 80049 | 620 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 15 | 1 | 0 | 0 | 5204 | 0 | 80029 | 16 | 16 | 0 | 25 | 403146 | 80010 | 164662 | 160000 | 80010 | 160000 | 160108 | 481105 | 3679391 | 1296050 | 0 | 80023 | 80050 | 80050 | 0 | 3 | 31 | 400010 | 20 | 160000 | 160000 | 20 | 400000 | 480000 | 80219 | 80050 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 160012 | 0 | 0 | 0 | 0 | 160012 | 0 | 0 | 14 | 160000 | 14 | 38 | 12 | 0 | 0 | 5019 | 0 | 0 | 3 | 17 | 3 | 3 | 80047 | 0 | 80000 | 160000 | 160000 | 80010 | 80046 | 80046 | 80051 | 80050 | 80046 |
320024 | 80050 | 620 | 0 | 0 | 0 | 0 | 0 | 0 | 12 | 16 | 0 | 0 | 0 | 5949 | 2 | 80037 | 16 | 0 | 2 | 25 | 406023 | 80010 | 166465 | 160000 | 80010 | 160000 | 160000 | 480049 | 2399913 | 1293377 | 0 | 80036 | 80049 | 80045 | 0 | 3 | 40 | 400010 | 20 | 160000 | 160000 | 20 | 400000 | 480000 | 80045 | 80044 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 160000 | 0 | 32 | 0 | 0 | 160002 | 0 | 0 | 2 | 160002 | 0 | 0 | 0 | 0 | 0 | 5019 | 0 | 0 | 3 | 17 | 3 | 3 | 80042 | 0 | 80000 | 160000 | 160000 | 80010 | 80050 | 80045 | 80046 | 80050 | 80052 |
320024 | 80045 | 620 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 16 | 0 | 0 | 0 | 1825 | 0 | 80036 | 0 | 0 | 0 | 25 | 404321 | 80010 | 160017 | 160000 | 80010 | 160000 | 160000 | 480049 | 2239894 | 1288411 | 0 | 80025 | 80049 | 80049 | 0 | 3 | 32 | 400010 | 20 | 160000 | 160000 | 20 | 400000 | 480000 | 80059 | 80061 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 160013 | 0 | 0 | 3 | 0 | 160012 | 0 | 0 | 8 | 160002 | 14 | 38 | 12 | 0 | 0 | 5019 | 0 | 0 | 3 | 17 | 3 | 3 | 80051 | 0 | 80000 | 160000 | 160000 | 80010 | 80045 | 80045 | 80045 | 80063 | 80049 |
320024 | 80061 | 621 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 15 | 1 | 0 | 0 | 4370 | 2 | 80034 | 16 | 16 | 0 | 49 | 403792 | 80010 | 165444 | 160000 | 80010 | 160000 | 160000 | 480049 | 2155261 | 1297159 | 0 | 80024 | 80045 | 80044 | 0 | 3 | 27 | 400010 | 20 | 160000 | 160000 | 20 | 400000 | 480000 | 80044 | 80044 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 160000 | 13 | 0 | 0 | 0 | 160012 | 1 | 0 | 2 | 160002 | 2 | 0 | 12 | 0 | 0 | 5019 | 0 | 0 | 3 | 17 | 3 | 3 | 80058 | 0 | 80000 | 160000 | 160000 | 80010 | 80220 | 80062 | 80051 | 80050 | 80062 |
320024 | 80044 | 621 | 1 | 0 | 0 | 0 | 0 | 0 | 12 | 15 | 0 | 0 | 0 | 5481 | 0 | 80046 | 16 | 16 | 0 | 25 | 405496 | 80010 | 164242 | 160000 | 80010 | 160000 | 160000 | 480049 | 2319939 | 1294988 | 0 | 80025 | 80217 | 80050 | 0 | 3 | 44 | 400010 | 20 | 160000 | 160000 | 20 | 400000 | 480000 | 80050 | 80050 | 2 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 160075 | 12 | 32 | 2 | 0 | 160014 | 0 | 0 | 15 | 160002 | 14 | 38 | 12 | 1 | 0 | 5019 | 0 | 0 | 3 | 17 | 3 | 3 | 80046 | 0 | 80000 | 160000 | 160000 | 80010 | 80049 | 80045 | 80045 | 80051 | 80051 |
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