Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

ST3 (multiple, post-index, 8H)

Test 1: uops

Code:

  st3 { v0.8h, v1.8h, v2.8h }, [x6], x8
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop
  mov x0, 0
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 6.000

Issues: 7.000

Integer unit issues: 1.000

Load/store unit issues: 3.000

SIMD/FP unit issues: 3.000

retire uop (01)cycle (02)03l1i tlb fill (04)mmu table walk instruction (07)mmu table walk data (08)09l2 tlb miss instruction (0a)l2 tlb miss data (0b)18191e1f233a3f464951schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)5f6061696d6emap rewind (75)map stall (76)dispatch uop (78)map ldst uop (7d)map simd uop (7e)map ldst uop inputs (80)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd store (99)inst ldst (9b)l1d tlb access (a0)l1d tlb miss (a1)l1d cache miss st (a2)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acafbcl1d cache miss st nonspec (c0)c2c9cfd0d2l1i cache miss demand (d3)l1i tlb miss demand (d4)d5map dispatch bubble (d6)d9dadbddfetch restart (de)e0? int output thing (e9)eaebec? ldst retires (ed)? simd retires (ee)? int retires (ef)f5f6f7f8fd
660082896623212400150000004659286103316697700010003000300010003000300050003302224000120022682286012872031070003000300070009000286552873411610011000100030002603000000300006001318197226923309493919646319638071246452848210001558112300139783000300010002876728819288052879828765
66004288122320180015001010464428592031674070001000300030001000300030005000330222400012002271428509288933107000300030007000900028686287861161001100010003000060300000455300006001313996036890306834119720326438011448462833110001571612266138243000300010002881328819287622875328680
6600428788231013009001010461928688331674870001001300030001000300030005000329852400030022643285052884031070003000300070009000288272875721610011000100030002603000000300006001315593866875311493719790326138081642502835710001542612294136103000300010002885828947289262901828929
6600428865232018111413126488047082885503167027000100030003006100130093003501033133240961500227142871529037182870003000300370219009288982887041610011000100030040623000140300006001296393336932311974419766324838151243462851510011616212492140363000300010002914728972291462898629060
660042915923401510161222641770463228967331699870001002300030061001300630035005331642402413002268528650289343107000300030007000900029114290092161001100010003000000300010400300000001298592896864307274420064328838091646412827210001550212355137783000300010002914829314289212895828893
66004287692330140016000000487728761321671070001000300030001001300030005000330192400081022684285892889131070003000300070009000286482867311610011000100030000603000123300006227911298693856972313074819673329438071844372837810001566612386135983000300010002880328813289262870328762
6600428979231016001600091047442871433165307000101230153041100730393012506033818242241300230652906529280100314705630393036708890812924029605171610011000100030242603034006141303200001279992996874310895019685319038131043452851010001554712243140583000300010002885028893288142887828647
6600428568221015001100000048542871233164007000100030003000100030003000500033039240009002276128438285733107000300030007000900028506285301161001100010003000060300000030000000133239404706131705381943431993809846532818810001536711723132453000300010002854428565286522851628441
6600428563223019002000001049322850500164577000100030003000100030003000500033056240007002276028356286393107000300030007000900028525285841161001100010003000060300050153000270013067954669073191115019466318838011448462829610001518212289138733000300010002858828912288412863228565
66004286392240200017000010468028777331675470001000300030001000300030005000330442400031022811284192867631070003000300070009000286262869111610011000100030000603000000300000001342894376986310254519595313538121142392821110001527912081133793000300010002854628635286812856228563

Test 2: throughput

Count: 8

Code:

  st3 { v0.8h, v1.8h, v2.8h }, [x6], x8
  st3 { v0.8h, v1.8h, v2.8h }, [x6], x8
  st3 { v0.8h, v1.8h, v2.8h }, [x6], x8
  st3 { v0.8h, v1.8h, v2.8h }, [x6], x8
  st3 { v0.8h, v1.8h, v2.8h }, [x6], x8
  st3 { v0.8h, v1.8h, v2.8h }, [x6], x8
  st3 { v0.8h, v1.8h, v2.8h }, [x6], x8
  st3 { v0.8h, v1.8h, v2.8h }, [x6], x8
  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.5006

retire uop (01)cycle (02)03l1d tlb fill (05)mmu table walk data (08)09l2 tlb miss data (0b)18191e1f2224373a3f46494f51schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)7amap int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd store (99)inst ldst (9b)9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache miss st (a2)a4ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acafbcl1d cache miss st nonspec (c0)l1d tlb miss nonspec (c1)c2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)f5f6f7f8fd
48020812005893111002701219102013112003516160255662828010024642624000080100240000240000480499551968719273460120021120042120043399903400245601000200240000240000200560000720000120042120043118020110099100100800008000010024001414360024001600222400021401405110117111200478000024000024000080100120051120206120062120060120052
4802041200509311000011219004534112003616160255714378010024566824000080100240000240000480499551983619327160120033120211120057399873400425601000200240000240120200560000720000120047120052118020110099100100800008000010024000003400240002208240002234005110117111200408000024000024000080100121119120043120050120044120043
4802041200439300000000000643001200281600255683018010024433624000080100240000240000480729551976419522920120027120051120058399973400335601000200240000240000200560000720000120058120060118020110099100100800008000010024001414360024001611142400021401405110117111200498000024000024000080100120061120059120052120060120059
4802041200589301101001218006659112004316160255679608010024620724000080100240000240000480499551968719317820120021120042120042399873400315601000200240000240000200560000720000120049120043118020110099100100800008000010024000003400240002001424000000005110117111200398003924000024000080100120053120062120059120053120051
480204120049930100200019005899112004516002556745380100249992240000801002400002400004804955520143194932701200341200511200583999934004256010002002400002400002025614007214401207061205834180201100991001008000080000100240060034002400021011240002234005110117111200398000024000024000080100120044120044120043144755120043
480204145268931000000120011601600120028161632556310380100249199240060801002400002400004804985519618193052501200331200591200603999834003156010002002400002400002005600007200001200601200521180201100991001008000080000100240000038002400021087324000220005110116111200468000024000024000080100144819120043120050120043120043
480204120043930000000123005255012002816160475640298010024573424000080100240000240000480499551956719499710120021120048120042399843400255601000200240000240000200560000720000120042120198118020110099100100800008000010024000000520240002002240002234005110126111200468000024000024000080100120043120043120196120043120043
4802041200439300000002400078450120027161602556796880100246284240000801002400002400004804995519567194768201200211200421200433998434002456010002002400002400002005600007200001200421200421180201100991001008000080000100240000000024000210524000200005109116111200408000024000024000080100120043120043120043120043120043
4802041200439310000000900740501200271616025563938801392437162400008010024000024000048049955195671958708012002112004912004339984340024560100020024000024000020056000072000012004212004311802011009910010080000800001002400000000240000005240000034005110117111200468000024000024000080100120043120043120043120197120043
4802041200439300000000300762401200270160255688848010024688824000080100240000240000480499551956719466530120021120042120048399843400255601000200240000240120200560000720000120043120042118020110099100100800008000010024000003400240000002240062234005121126111200408062624000024000080100120197120664120197120505120505

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.5005

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e1f22373f46494f51schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)5f6061696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd store (99)inst ldst (9b)9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache miss st (a2)a4ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acafbcl1d cache miss st nonspec (c0)c2branch mispred nonspec (cb)cfd0d2d5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)f5f6f7f8fd
48002812004393100009930160091200281616025569431800102433422400008001024000024000048004955195671934141000120021120042120197399843400255600102024000024012020560000720000120042120043118002110910108000080000102400000420024000200224006204200502000617881200408000024000024000080010120044120044120044120044120044
48002412004293100009333059491200291616025567158800102497112400008004924000024000048004955195671945889000120021120043120043399843401315600102024000024000020560000720000120043120043118002110910108000080000102400000420024006210224000224200502000617981200408003924000024000080010120043120044120138120044120044
48002412004393000009153521643712002716160255666708001024785524000080010240000240000480049551956719438260001200211200431200433998434002556001020240000240000205600007200001200431200431180021109101080000800001024000004200240002102240002242005020006179141200408000024000024000080010120044120044120043120043120044
480024120199930000057301168212002816160255671458001024927724000080010240000240108480049551956719438170001200211200431200433998434002556027420240000240000205600007200001200431200431180021109101080000800001024000004200240002022240000242005020007261281200408011724000024000080010120044120044120607120044120043
480024120043930010097230599812002816160255700068001024474124000080010240000240000480049551956719689490001200211200431200433998434002556001020240000240000205600007200001200431200431180021109101080000800001024000000002400020087724000224200502003717881200408000024000024000080010120043120043120043120043120044
480024120042931000098491064251200271616025565721800102450052400008001024000024000048004955195671937178000120021120043120043399843400255600102024000024000020560000720360120043120043118002110910108000080000102400002420024000220224000224200502000917871200398000024000024000080010120044120044120044120044120044
480024120043930000099600121391200281616025567872800102488542400008004924000024000048004955195671940005000120026120044120043399847400245600102024000024000020560000720000120043120043118002110910108000080000102400000420024000200924000224200502000817871200408000024000024000080010120044120043120195120044120044
4800241200439300001101735604770120028161693705692938001024656324000080049240117240000480281551956719394510001200211201971200433998491402375608022024024024024020560560720720120199120456318002110910108000080000102400602421562240182091715240122242005033009258101201848085824000024000080010120501120350120504120349120350
4800241203459340131139517905249120488161602556572080010249711240000800102400002400004800495519567194719200012002112004312004339984340025560010202400002400002056000072000012004312004311800211091010800008000010240000042002400020022400022000502000817781200408000024000024000080010120043120044120044120044120044
4800241200439300020747401669120028160025565020800102459972400008001024000024000048004955195671943133000120021120043120043399843400255600102024000024000020560000720000120043120042118002110910108000080000102400000420024000210324000224200502000617981200408000024000024000080010120044120044120045120044120044