Apple Microarchitecture Research by Dougall Johnson M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions M1/A14 E-core (Icestorm): Overview | Base Instructions | SIMD and FP Instructions
Code:
st3 { v0.b, v1.b, v2.b }[1], [x6] nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop
mov x0, 0
(no loop instructions)
Retires (minus 60 nops): 2.000
Issues: 2.000
Integer unit issues: 0.000
Load/store unit issues: 1.000
SIMD/FP unit issues: 1.000
retire uop (01) | cycle (02) | 03 | l1d tlb fill (05) | mmu table walk instruction (07) | mmu table walk data (08) | 09 | l2 tlb miss instruction (0a) | l2 tlb miss data (0b) | 18 | 19 | 1e | 1f | 3a | 3f | 49 | 51 | schedule uop (52) | schedule simd uop (54) | schedule ldst uop (55) | dispatch simd uop (57) | dispatch ldst uop (58) | simd uops in schedulers (5a) | ldst uops in schedulers (5b) | 5f | 69 | 6d | 6e | map rewind (75) | map stall (76) | dispatch uop (78) | map ldst uop (7d) | map simd uop (7e) | map ldst uop inputs (80) | map simd uop inputs (81) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst simd store (99) | inst ldst (9b) | l1d tlb access (a0) | l1d tlb miss (a1) | l1d cache miss st (a2) | ld unit uop (a6) | st unit uop (a7) | l1d cache writeback (a8) | a9 | ac | af | bc | l1d cache miss st nonspec (c0) | l1d tlb miss nonspec (c1) | c2 | c9 | cf | d0 | d2 | l1i cache miss demand (d3) | l1i tlb miss demand (d4) | d5 | map dispatch bubble (d6) | d9 | da | db | dd | fetch restart (de) | e0 | ea | eb | ec | ? ldst retires (ed) | ? simd retires (ee) | f5 | f6 | f7 | f8 | fd |
62006 | 29359 | 236 | 1 | 15 | 2 | 0 | 18 | 0 | 0 | 0 | 12 | 0 | 4643 | 29213 | 0 | 18467 | 2000 | 1000 | 1000 | 1000 | 1000 | 10905 | 8000 | 12 | 21749 | 28357 | 28568 | 3 | 10 | 2000 | 1000 | 1000 | 2000 | 3000 | 28715 | 28568 | 1 | 1 | 61001 | 1000 | 1000 | 1000 | 0 | 2 | 0 | 1000 | 0 | 0 | 246 | 1000 | 0 | 3 | 0 | 0 | 0 | 13346 | 10000 | 7019 | 3206 | 8 | 47 | 20053 | 3187 | 3819 | 11 | 45 | 38 | 28126 | 15161 | 12613 | 14211 | 1000 | 1000 | 28744 | 28598 | 28661 | 28665 | 28591 |
62004 | 28711 | 222 | 0 | 22 | 0 | 0 | 15 | 1 | 0 | 0 | 0 | 2 | 4922 | 28494 | 0 | 17665 | 2000 | 1000 | 1000 | 1000 | 1000 | 10908 | 8000 | 5 | 21707 | 28481 | 28597 | 3 | 10 | 2000 | 1000 | 1000 | 2000 | 3000 | 28572 | 28760 | 1 | 1 | 61001 | 1000 | 1000 | 1002 | 3 | 2 | 1 | 1001 | 0 | 1 | 1 | 1000 | 1 | 2 | 1 | 1 | 0 | 13460 | 9757 | 7017 | 3199 | 3 | 43 | 19957 | 3327 | 3815 | 19 | 41 | 41 | 28136 | 15334 | 12516 | 14069 | 1000 | 1000 | 28576 | 28617 | 28656 | 28642 | 28735 |
62004 | 28683 | 222 | 0 | 19 | 0 | 0 | 21 | 0 | 0 | 0 | 0 | 0 | 4768 | 28363 | 0 | 17633 | 2000 | 1000 | 1000 | 1000 | 1000 | 10905 | 8000 | 6 | 21732 | 28481 | 28593 | 3 | 10 | 2000 | 1000 | 1000 | 2000 | 3000 | 28573 | 28612 | 1 | 1 | 61001 | 1000 | 1000 | 1000 | 0 | 2 | 0 | 1000 | 0 | 0 | 70 | 1000 | 1 | 2 | 1 | 1 | 0 | 13207 | 9494 | 7037 | 3232 | 5 | 46 | 20125 | 3192 | 3812 | 17 | 48 | 46 | 28153 | 15059 | 12601 | 14125 | 1000 | 1000 | 28620 | 28706 | 28651 | 28720 | 28647 |
62004 | 28806 | 221 | 0 | 14 | 0 | 0 | 14 | 0 | 0 | 0 | 0 | 0 | 4774 | 28533 | 0 | 17613 | 2000 | 1001 | 1000 | 1000 | 1000 | 10902 | 8000 | 11 | 21751 | 28453 | 28604 | 3 | 10 | 2000 | 1000 | 1000 | 2000 | 3000 | 28555 | 28617 | 1 | 1 | 61001 | 1000 | 1000 | 1000 | 0 | 2 | 0 | 1000 | 0 | 0 | 0 | 1000 | 0 | 0 | 1 | 1 | 0 | 13276 | 9593 | 7003 | 3220 | 5 | 44 | 20011 | 3272 | 3821 | 13 | 43 | 45 | 28146 | 15055 | 12697 | 14262 | 1000 | 1000 | 28709 | 28627 | 28650 | 28607 | 28662 |
62004 | 28659 | 221 | 1 | 18 | 1 | 1 | 15 | 0 | 0 | 0 | 0 | 1 | 4872 | 28620 | 1 | 17618 | 2000 | 1000 | 1000 | 1000 | 1000 | 10898 | 8000 | 1 | 21703 | 28386 | 28734 | 3 | 10 | 2000 | 1000 | 1000 | 2000 | 3000 | 28608 | 28727 | 1 | 1 | 61001 | 1000 | 1000 | 1001 | 2 | 2 | 1 | 1001 | 0 | 1 | 391 | 1000 | 1 | 2 | 1 | 2 | 0 | 13319 | 9350 | 7031 | 3220 | 9 | 44 | 19987 | 3220 | 3808 | 10 | 43 | 41 | 28147 | 15603 | 12548 | 13980 | 1000 | 1000 | 28630 | 28659 | 28678 | 28621 | 28614 |
62004 | 28750 | 222 | 0 | 18 | 0 | 0 | 26 | 0 | 0 | 0 | 12 | 0 | 4909 | 28591 | 1 | 17765 | 2000 | 1000 | 1000 | 1000 | 1000 | 10908 | 8000 | 5 | 21752 | 28421 | 28629 | 3 | 10 | 2000 | 1000 | 1000 | 2000 | 3000 | 28653 | 28580 | 1 | 1 | 61001 | 1000 | 1000 | 1002 | 3 | 0 | 2 | 1001 | 0 | 1 | 1 | 1000 | 0 | 2 | 0 | 0 | 0 | 13164 | 9655 | 6978 | 3344 | 7 | 43 | 19953 | 3176 | 3816 | 10 | 42 | 41 | 28174 | 15564 | 12756 | 14225 | 1000 | 1000 | 28738 | 28582 | 28644 | 28621 | 28601 |
62004 | 28593 | 222 | 0 | 19 | 0 | 0 | 17 | 0 | 0 | 0 | 0 | 0 | 4858 | 28466 | 0 | 17627 | 2000 | 1000 | 1000 | 1000 | 1000 | 10906 | 8000 | 6 | 21743 | 28432 | 28695 | 3 | 10 | 2000 | 1000 | 1000 | 2000 | 3000 | 28573 | 28589 | 1 | 1 | 61001 | 1000 | 1000 | 1000 | 0 | 0 | 0 | 1000 | 0 | 0 | 0 | 1000 | 0 | 2 | 0 | 0 | 0 | 13137 | 9456 | 7058 | 3214 | 7 | 49 | 20046 | 3249 | 3808 | 13 | 34 | 42 | 28097 | 15155 | 12665 | 13986 | 1000 | 1000 | 28665 | 28671 | 28596 | 28653 | 28610 |
62004 | 28710 | 220 | 1 | 13 | 1 | 0 | 17 | 1 | 0 | 0 | 0 | 1 | 4807 | 28466 | 0 | 17623 | 2000 | 1000 | 1000 | 1000 | 1000 | 10909 | 8000 | 10 | 21697 | 28461 | 28697 | 3 | 10 | 2000 | 1000 | 1000 | 2000 | 3000 | 28543 | 28757 | 1 | 1 | 61001 | 1000 | 1000 | 1003 | 1 | 2 | 0 | 1001 | 0 | 1 | 1 | 1000 | 0 | 2 | 0 | 0 | 0 | 13304 | 9799 | 7077 | 3242 | 6 | 43 | 20059 | 3222 | 3809 | 13 | 38 | 47 | 28117 | 14891 | 12726 | 14023 | 1000 | 1000 | 28711 | 28540 | 28557 | 28467 | 28631 |
62004 | 28626 | 223 | 0 | 18 | 0 | 0 | 12 | 0 | 0 | 0 | 12 | 0 | 4723 | 28404 | 0 | 17551 | 2000 | 1000 | 1000 | 1000 | 1000 | 10910 | 8000 | 9 | 21726 | 28506 | 28677 | 3 | 10 | 2000 | 1000 | 1000 | 2000 | 3000 | 28718 | 28714 | 1 | 1 | 61001 | 1000 | 1000 | 1001 | 1 | 3 | 2 | 1001 | 0 | 2 | 1 | 1000 | 1 | 0 | 1 | 0 | 0 | 13649 | 9582 | 6989 | 3159 | 6 | 40 | 20084 | 3286 | 3813 | 8 | 46 | 43 | 28196 | 15361 | 12692 | 13998 | 1000 | 1000 | 28524 | 28712 | 28669 | 28713 | 28667 |
62004 | 28606 | 223 | 0 | 17 | 0 | 0 | 11 | 0 | 0 | 0 | 0 | 1 | 4836 | 28544 | 0 | 17620 | 2000 | 1000 | 1000 | 1000 | 1000 | 10903 | 8000 | 7 | 21753 | 28479 | 28753 | 3 | 10 | 2000 | 1000 | 1000 | 2000 | 3000 | 28603 | 28651 | 1 | 1 | 61001 | 1000 | 1000 | 1000 | 0 | 2 | 0 | 1000 | 0 | 0 | 0 | 1000 | 0 | 0 | 0 | 0 | 0 | 13423 | 9612 | 7097 | 3230 | 5 | 46 | 20013 | 3191 | 3808 | 11 | 45 | 41 | 28150 | 14815 | 12413 | 14013 | 1000 | 1000 | 28694 | 28782 | 28609 | 28666 | 28684 |
Count: 8
Code:
st3 { v0.b, v1.b, v2.b }[1], [x6] st3 { v0.b, v1.b, v2.b }[1], [x6] st3 { v0.b, v1.b, v2.b }[1], [x6] st3 { v0.b, v1.b, v2.b }[1], [x6] st3 { v0.b, v1.b, v2.b }[1], [x6] st3 { v0.b, v1.b, v2.b }[1], [x6] st3 { v0.b, v1.b, v2.b }[1], [x6] st3 { v0.b, v1.b, v2.b }[1], [x6]
mov x7, x6 mov x8, x6 mov x9, x6 mov x10, x6 mov x11, x6 mov x12, x6 mov x13, x6
(fused SUBS/B.cc loop)
Result (median cycles for code divided by count): 0.5007
retire uop (01) | cycle (02) | 03 | l1d tlb fill (05) | mmu table walk data (08) | 09 | l2 tlb miss data (0b) | 18 | 19 | 1e | 1f | 24 | 37 | 3a | 3f | 46 | 49 | 4f | 51 | schedule uop (52) | schedule int uop (53) | schedule simd uop (54) | schedule ldst uop (55) | dispatch int uop (56) | dispatch simd uop (57) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | ldst uops in schedulers (5b) | 60 | 69 | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map simd uop (7e) | map int uop inputs (7f) | map ldst uop inputs (80) | map simd uop inputs (81) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int alu (97) | inst simd store (99) | inst ldst (9b) | 9f | l1d tlb access (a0) | l1d tlb miss (a1) | l1d cache miss st (a2) | a4 | ld unit uop (a6) | st unit uop (a7) | l1d cache writeback (a8) | a9 | ac | af | bc | l1d cache miss st nonspec (c0) | l1d tlb miss nonspec (c1) | c2 | branch cond mispred nonspec (c5) | branch mispred nonspec (cb) | cd | cf | d0 | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ? int output thing (e9) | ? ldst retires (ed) | ? simd retires (ee) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
160206 | 40070 | 310 | 1 | 0 | 0 | 2 | 0 | 0 | 12 | 20 | 0 | 1461 | 1 | 40039 | 16 | 16 | 1 | 49 | 162476 | 100 | 82447 | 80000 | 100 | 80000 | 80000 | 500 | 1839976 | 647400 | 0 | 40029 | 40050 | 40050 | 19961 | 3 | 20020 | 160100 | 200 | 80000 | 80000 | 200 | 160000 | 240000 | 40052 | 40051 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 80014 | 15 | 44 | 0 | 1 | 80014 | 0 | 1 | 289 | 80000 | 16 | 43 | 14 | 2 | 0 | 0 | 0 | 5110 | 5 | 1 | 16 | 1 | 1 | 40051 | 0 | 80000 | 80000 | 100 | 40049 | 40049 | 40052 | 40054 | 40055 |
160204 | 40070 | 310 | 1 | 0 | 0 | 0 | 0 | 0 | 12 | 17 | 0 | 1827 | 1 | 40036 | 0 | 0 | 7 | 25 | 162756 | 100 | 82831 | 80000 | 100 | 80000 | 80000 | 500 | 1840072 | 643892 | 0 | 40027 | 40050 | 40052 | 19966 | 3 | 20005 | 160100 | 200 | 80000 | 80000 | 200 | 160000 | 240000 | 40050 | 40047 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 80015 | 14 | 44 | 0 | 1 | 80016 | 0 | 0 | 303 | 80002 | 16 | 44 | 14 | 0 | 0 | 0 | 0 | 5110 | 0 | 1 | 16 | 1 | 2 | 40051 | 0 | 80000 | 80000 | 100 | 40063 | 40051 | 40051 | 40064 | 40055 |
160204 | 40067 | 310 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 15 | 0 | 2439 | 1 | 40036 | 16 | 0 | 1 | 25 | 163825 | 100 | 82396 | 80000 | 100 | 80000 | 80000 | 500 | 1840048 | 649505 | 0 | 40025 | 40050 | 40054 | 19962 | 3 | 20012 | 160100 | 200 | 80000 | 80000 | 200 | 160000 | 240000 | 40050 | 40054 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 80014 | 14 | 44 | 0 | 0 | 80016 | 0 | 0 | 282 | 80002 | 16 | 44 | 14 | 1 | 0 | 0 | 0 | 5110 | 0 | 1 | 16 | 1 | 1 | 40047 | 0 | 80000 | 80000 | 100 | 40048 | 40052 | 40052 | 40052 | 40054 |
160204 | 40063 | 310 | 1 | 1 | 1 | 1 | 0 | 0 | 12 | 19 | 0 | 1213 | 1 | 40035 | 0 | 16 | 0 | 25 | 162170 | 100 | 83187 | 80000 | 100 | 80000 | 80000 | 500 | 1839904 | 649562 | 0 | 40029 | 40063 | 40050 | 19973 | 3 | 20012 | 160100 | 200 | 80000 | 80000 | 200 | 160000 | 240000 | 40052 | 40054 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 80015 | 15 | 44 | 0 | 1 | 80014 | 1 | 1 | 18 | 80002 | 14 | 44 | 14 | 0 | 0 | 0 | 0 | 5110 | 0 | 1 | 16 | 1 | 1 | 40048 | 0 | 80000 | 80000 | 100 | 40063 | 40052 | 40063 | 40063 | 40055 |
160204 | 40053 | 310 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 17 | 0 | 2293 | 1 | 40033 | 16 | 16 | 0 | 25 | 163785 | 100 | 81446 | 80000 | 100 | 80000 | 80000 | 500 | 1840072 | 642385 | 0 | 40025 | 40050 | 40054 | 19967 | 3 | 20012 | 160100 | 200 | 80000 | 80000 | 200 | 160000 | 240000 | 40062 | 40054 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 80015 | 14 | 44 | 0 | 1 | 80016 | 1 | 0 | 15 | 80002 | 14 | 44 | 14 | 0 | 0 | 0 | 0 | 5110 | 0 | 1 | 16 | 1 | 1 | 40051 | 0 | 80000 | 80000 | 100 | 40051 | 40063 | 40051 | 40051 | 40055 |
160204 | 40054 | 310 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 15 | 0 | 2882 | 1 | 40036 | 16 | 16 | 0 | 25 | 163732 | 100 | 83173 | 80000 | 100 | 80000 | 80000 | 500 | 1840456 | 647975 | 0 | 40022 | 40050 | 40051 | 19976 | 3 | 20005 | 160100 | 200 | 80000 | 80000 | 200 | 160000 | 240000 | 40050 | 40051 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 80014 | 14 | 44 | 0 | 0 | 80016 | 0 | 0 | 18 | 80002 | 16 | 44 | 14 | 0 | 0 | 0 | 0 | 5110 | 0 | 1 | 16 | 1 | 1 | 40048 | 0 | 80000 | 80000 | 100 | 40051 | 40051 | 40055 | 40055 | 40052 |
160204 | 40050 | 310 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 17 | 0 | 1989 | 1 | 40032 | 0 | 16 | 0 | 25 | 163062 | 100 | 82504 | 80000 | 100 | 80000 | 80000 | 500 | 1840144 | 647944 | 0 | 40025 | 40047 | 40053 | 19967 | 3 | 20020 | 160100 | 200 | 80000 | 80000 | 200 | 160000 | 240000 | 40052 | 40207 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 80014 | 14 | 44 | 0 | 2 | 80016 | 0 | 1 | 17 | 80002 | 16 | 44 | 14 | 1 | 0 | 0 | 0 | 5110 | 0 | 1 | 16 | 1 | 1 | 40050 | 0 | 80000 | 80000 | 100 | 40054 | 40055 | 40054 | 40053 | 40055 |
160204 | 40054 | 310 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 21 | 0 | 2648 | 1 | 40036 | 0 | 0 | 0 | 25 | 163681 | 100 | 83359 | 80000 | 100 | 80000 | 80000 | 500 | 1840024 | 643785 | 0 | 40025 | 40050 | 40050 | 19962 | 3 | 20012 | 160100 | 200 | 80000 | 80000 | 200 | 160000 | 240000 | 40063 | 40054 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 80015 | 14 | 44 | 0 | 0 | 80016 | 1 | 1 | 14 | 80002 | 16 | 44 | 14 | 0 | 0 | 0 | 0 | 5110 | 0 | 1 | 16 | 2 | 2 | 40051 | 0 | 80000 | 80000 | 100 | 40055 | 40055 | 40051 | 40051 | 40054 |
160204 | 40052 | 310 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 14 | 0 | 2021 | 1 | 40238 | 16 | 16 | 142 | 25 | 162657 | 100 | 82107 | 80000 | 100 | 80000 | 80000 | 500 | 1840168 | 646660 | 0 | 40024 | 40049 | 40252 | 19965 | 3 | 20173 | 160100 | 200 | 80000 | 80120 | 200 | 160000 | 240000 | 40054 | 40047 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 80015 | 15 | 0 | 0 | 1 | 80016 | 0 | 0 | 1069 | 80002 | 16 | 44 | 14 | 0 | 0 | 0 | 0 | 5110 | 0 | 1 | 16 | 1 | 1 | 40049 | 0 | 80000 | 80000 | 100 | 40055 | 40054 | 40259 | 40054 | 40052 |
160204 | 40052 | 310 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 14 | 0 | 3869 | 1 | 40035 | 16 | 16 | 1 | 47 | 162728 | 100 | 82781 | 80000 | 100 | 80000 | 80108 | 500 | 1840072 | 650569 | 0 | 40029 | 40063 | 40257 | 19967 | 11 | 20012 | 160100 | 200 | 80000 | 80000 | 200 | 160000 | 240000 | 40062 | 40050 | 2 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 80194 | 14 | 44 | 294 | 1 | 80016 | 0 | 1 | 14 | 80062 | 16 | 44 | 14 | 1 | 0 | 0 | 0 | 5110 | 0 | 1 | 16 | 1 | 1 | 40047 | 0 | 80000 | 80000 | 100 | 40063 | 40054 | 40051 | 40248 | 40055 |
Result (median cycles for code divided by count): 0.5005
retire uop (01) | cycle (02) | 03 | mmu table walk data (08) | l2 tlb miss data (0b) | 18 | 19 | 1e | 1f | 22 | 23 | 24 | 37 | 3a | 3f | 46 | 49 | 4f | 51 | schedule uop (52) | schedule int uop (53) | schedule simd uop (54) | schedule ldst uop (55) | dispatch int uop (56) | dispatch simd uop (57) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | ldst uops in schedulers (5b) | 69 | 6d | 6e | map stall dispatch (70) | rob full (74) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map simd uop (7e) | map int uop inputs (7f) | map ldst uop inputs (80) | map simd uop inputs (81) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | 91 | inst branch cond (94) | inst int alu (97) | inst simd store (99) | inst ldst (9b) | 9f | l1d tlb access (a0) | l1d tlb miss (a1) | l1d cache miss st (a2) | a4 | ld unit uop (a6) | st unit uop (a7) | l1d cache writeback (a8) | ac | af | bc | l1d cache miss st nonspec (c0) | c2 | cf | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ? ldst retires (ed) | ? simd retires (ee) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
160026 | 40042 | 310 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | 0 | 0 | 4695 | 0 | 40027 | 16 | 16 | 0 | 25 | 160039 | 10 | 80031 | 80000 | 10 | 80000 | 80000 | 50 | 1839712 | 640084 | 40023 | 40043 | 40042 | 19982 | 0 | 3 | 20023 | 160010 | 20 | 80000 | 80000 | 20 | 160000 | 240000 | 40042 | 40043 | 1 | 1 | 80021 | 10 | 9 | 0 | 10 | 10 | 80000 | 80000 | 10 | 80000 | 0 | 34 | 0 | 0 | 80002 | 0 | 5 | 80002 | 2 | 34 | 0 | 5020 | 5 | 16 | 4 | 3 | 40040 | 80000 | 80000 | 10 | 40044 | 40043 | 40044 | 40043 | 40049 |
160024 | 40042 | 311 | 0 | 0 | 0 | 0 | 0 | 9 | 1 | 0 | 0 | 56 | 0 | 40028 | 16 | 16 | 0 | 25 | 163796 | 10 | 81933 | 80000 | 10 | 80000 | 80000 | 50 | 1839712 | 640094 | 40021 | 40043 | 40048 | 19988 | 0 | 3 | 20022 | 160010 | 20 | 80000 | 80000 | 20 | 160000 | 240000 | 40043 | 40048 | 1 | 1 | 80021 | 10 | 9 | 0 | 10 | 10 | 80000 | 80000 | 10 | 80000 | 0 | 34 | 0 | 0 | 80002 | 1 | 5 | 80002 | 2 | 34 | 0 | 5020 | 3 | 16 | 4 | 3 | 41127 | 80000 | 80000 | 10 | 40043 | 40044 | 40043 | 40044 | 40044 |
160024 | 40048 | 317 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | 0 | 0 | 4035 | 0 | 40029 | 16 | 16 | 0 | 25 | 161980 | 10 | 82876 | 80000 | 10 | 80000 | 80000 | 50 | 1839712 | 646164 | 40024 | 40042 | 40049 | 19982 | 0 | 3 | 20022 | 160010 | 20 | 80000 | 80000 | 20 | 160000 | 240000 | 40043 | 40042 | 1 | 1 | 80021 | 10 | 9 | 0 | 10 | 10 | 80000 | 80000 | 10 | 80000 | 0 | 34 | 0 | 0 | 80002 | 0 | 2 | 80002 | 2 | 34 | 0 | 5020 | 3 | 16 | 4 | 3 | 40040 | 80000 | 80000 | 10 | 40050 | 40050 | 40725 | 40049 | 40044 |
160024 | 40042 | 311 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | 0 | 0 | 3425 | 0 | 40034 | 16 | 16 | 1 | 25 | 162290 | 10 | 80870 | 80000 | 10 | 80000 | 80000 | 50 | 1839832 | 644428 | 40021 | 40042 | 40043 | 19982 | 0 | 3 | 20023 | 160010 | 20 | 80000 | 80000 | 20 | 160000 | 240000 | 40042 | 40043 | 1 | 1 | 80021 | 10 | 9 | 0 | 10 | 10 | 80000 | 80000 | 10 | 80000 | 0 | 34 | 0 | 0 | 80002 | 1 | 5 | 80002 | 2 | 34 | 0 | 5020 | 3 | 16 | 4 | 3 | 40039 | 80000 | 80000 | 10 | 40044 | 40043 | 40044 | 40043 | 40043 |
160024 | 40049 | 311 | 0 | 0 | 0 | 0 | 0 | 6 | 1 | 0 | 0 | 286 | 0 | 40028 | 16 | 16 | 0 | 25 | 160048 | 10 | 81427 | 80000 | 10 | 80000 | 80000 | 50 | 1839808 | 649310 | 40023 | 40043 | 40048 | 19982 | 0 | 3 | 20022 | 160010 | 20 | 80000 | 80000 | 20 | 160000 | 240000 | 40043 | 40042 | 1 | 1 | 80021 | 10 | 9 | 0 | 10 | 10 | 80000 | 80000 | 10 | 80000 | 0 | 0 | 0 | 0 | 80002 | 0 | 5 | 80002 | 2 | 34 | 0 | 5020 | 3 | 16 | 3 | 5 | 40045 | 80000 | 80000 | 10 | 40044 | 40043 | 40044 | 40043 | 40043 |
160024 | 40049 | 310 | 0 | 0 | 1 | 1 | 0 | 3 | 1 | 0 | 0 | 43 | 0 | 40033 | 16 | 16 | 0 | 25 | 161494 | 10 | 80036 | 80000 | 10 | 80000 | 80000 | 50 | 1839712 | 645052 | 40024 | 40042 | 40049 | 19982 | 0 | 3 | 20023 | 160010 | 20 | 80000 | 80000 | 20 | 160000 | 240000 | 40042 | 40049 | 1 | 1 | 80021 | 10 | 9 | 0 | 10 | 10 | 80000 | 80000 | 10 | 80000 | 0 | 34 | 0 | 0 | 80002 | 0 | 0 | 80002 | 2 | 34 | 0 | 5020 | 4 | 16 | 6 | 5 | 40046 | 80000 | 80000 | 10 | 40043 | 40044 | 40043 | 40044 | 40044 |
160024 | 40043 | 311 | 0 | 0 | 0 | 0 | 12 | 3 | 1 | 0 | 0 | 3911 | 0 | 40033 | 16 | 16 | 0 | 25 | 164549 | 10 | 85141 | 80000 | 10 | 80000 | 80000 | 50 | 1839712 | 640111 | 40021 | 40042 | 40042 | 19982 | 0 | 3 | 20028 | 160010 | 20 | 80000 | 80000 | 20 | 160000 | 240000 | 40049 | 40042 | 1 | 1 | 80021 | 10 | 9 | 0 | 10 | 10 | 80000 | 80000 | 10 | 80000 | 0 | 34 | 2 | 0 | 80002 | 0 | 5 | 80000 | 2 | 34 | 0 | 5020 | 3 | 16 | 4 | 3 | 40040 | 80000 | 80000 | 10 | 40044 | 40043 | 40043 | 40043 | 40050 |
160024 | 40042 | 311 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | 0 | 0 | 22 | 0 | 40922 | 16 | 16 | 0 | 25 | 160096 | 10 | 81562 | 80000 | 10 | 80000 | 80000 | 50 | 1839712 | 640093 | 40021 | 40043 | 40048 | 19982 | 0 | 3 | 20023 | 160010 | 20 | 80000 | 80000 | 20 | 160000 | 240000 | 40049 | 40043 | 1 | 1 | 80021 | 10 | 9 | 0 | 10 | 10 | 80000 | 80000 | 10 | 80000 | 0 | 34 | 0 | 0 | 80002 | 0 | 2 | 80002 | 2 | 34 | 0 | 5020 | 3 | 16 | 6 | 5 | 40039 | 80000 | 80000 | 10 | 40050 | 40050 | 40043 | 40050 | 40043 |
160024 | 40043 | 310 | 0 | 0 | 0 | 0 | 12 | 6 | 1 | 0 | 0 | 4113 | 0 | 40028 | 16 | 16 | 0 | 25 | 164520 | 10 | 81771 | 80000 | 10 | 80000 | 80000 | 50 | 1839712 | 654106 | 40021 | 40043 | 40042 | 19984 | 0 | 3 | 20022 | 160010 | 20 | 80000 | 80000 | 20 | 160000 | 240000 | 40043 | 40042 | 1 | 1 | 80021 | 10 | 9 | 0 | 10 | 10 | 80000 | 80000 | 10 | 80000 | 0 | 34 | 0 | 0 | 80002 | 0 | 2 | 80002 | 2 | 34 | 0 | 5020 | 4 | 16 | 3 | 6 | 40040 | 80000 | 80000 | 10 | 40050 | 40050 | 40049 | 40049 | 40044 |
160024 | 40042 | 313 | 0 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 1 | 3105 | 0 | 40027 | 16 | 16 | 0 | 25 | 161572 | 10 | 83874 | 80000 | 10 | 80000 | 80000 | 50 | 1839712 | 645874 | 40024 | 40042 | 40049 | 19985 | 0 | 3 | 20023 | 160010 | 20 | 80000 | 80000 | 20 | 160000 | 240000 | 40042 | 40049 | 1 | 1 | 80021 | 10 | 9 | 0 | 10 | 10 | 80000 | 80000 | 10 | 80000 | 0 | 34 | 0 | 0 | 80002 | 0 | 2 | 80002 | 2 | 34 | 0 | 5020 | 2 | 16 | 4 | 4 | 40039 | 80000 | 80000 | 10 | 40044 | 40043 | 40044 | 40043 | 40043 |