Apple Microarchitecture Research by Dougall Johnson M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions M1/A14 E-core (Icestorm): Overview | Base Instructions | SIMD and FP Instructions
Code:
st3 { v0.d, v1.d, v2.d }[1], [x6] nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop
mov x0, 0
(no loop instructions)
Retires (minus 60 nops): 4.000
Issues: 4.000
Integer unit issues: 0.000
Load/store unit issues: 2.000
SIMD/FP unit issues: 2.000
retire uop (01) | cycle (02) | 03 | l1d tlb fill (05) | mmu table walk instruction (07) | mmu table walk data (08) | 09 | l2 tlb miss instruction (0a) | l2 tlb miss data (0b) | 18 | 19 | 1e | 1f | 24 | 3a | 3f | 46 | 49 | 51 | schedule uop (52) | schedule simd uop (54) | schedule ldst uop (55) | dispatch simd uop (57) | dispatch ldst uop (58) | simd uops in schedulers (5a) | ldst uops in schedulers (5b) | 5e | 5f | 69 | 6d | 6e | map rewind (75) | map stall (76) | dispatch uop (78) | map ldst uop (7d) | map simd uop (7e) | map ldst uop inputs (80) | map simd uop inputs (81) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst simd store (99) | inst ldst (9b) | l1d tlb access (a0) | l1d tlb miss (a1) | l1d cache miss st (a2) | ld unit uop (a6) | st unit uop (a7) | l1d cache writeback (a8) | a9 | ac | af | bc | l1d cache miss st nonspec (c0) | l1d tlb miss nonspec (c1) | c2 | c9 | cf | d0 | d2 | l1i cache miss demand (d3) | l1i tlb miss demand (d4) | d5 | map dispatch bubble (d6) | d9 | da | db | dd | fetch restart (de) | e0 | ea | eb | ec | ? ldst retires (ed) | ? simd retires (ee) | f5 | f6 | f7 | f8 | fd |
64007 | 29381 | 237 | 0 | 19 | 0 | 0 | 18 | 0 | 0 | 0 | 0 | 0 | 0 | 4661 | 29245 | 0 | 0 | 18181 | 4000 | 2000 | 2000 | 2000 | 2000 | 21595 | 16000 | 0 | 9 | 21817 | 29085 | 29297 | 3 | 10 | 4000 | 2000 | 2000 | 4000 | 6006 | 29356 | 29362 | 1 | 1 | 61001 | 1000 | 1000 | 2003 | 4 | 4 | 1 | 2002 | 0 | 2 | 2 | 2000 | 0 | 4 | 2 | 6 | 0 | 13140 | 9436 | 6918 | 3151 | 7 | 45 | 20419 | 3259 | 3810 | 18 | 52 | 51 | 28636 | 16213 | 13151 | 14554 | 2000 | 2000 | 29329 | 29297 | 29287 | 29414 | 29227 |
64004 | 29384 | 234 | 1 | 16 | 0 | 0 | 19 | 1 | 0 | 0 | 9 | 1 | 0 | 4759 | 29093 | 0 | 0 | 18195 | 4000 | 2002 | 2000 | 2000 | 2000 | 21610 | 16000 | 0 | 6 | 21838 | 29138 | 29350 | 3 | 10 | 4000 | 2000 | 2000 | 4000 | 6000 | 29309 | 29277 | 1 | 1 | 61001 | 1000 | 1000 | 2005 | 3 | 4 | 3 | 2002 | 0 | 1 | 2 | 2000 | 2 | 6 | 2 | 0 | 0 | 13263 | 9590 | 6903 | 3153 | 8 | 47 | 20330 | 3260 | 3814 | 18 | 44 | 49 | 28656 | 15969 | 13280 | 14910 | 2000 | 2000 | 29413 | 29285 | 29328 | 29309 | 29320 |
64004 | 29231 | 235 | 0 | 17 | 0 | 0 | 15 | 0 | 0 | 0 | 177 | 3 | 0 | 4630 | 29113 | 2 | 2 | 18224 | 4004 | 2000 | 2000 | 2000 | 2000 | 21625 | 16000 | 0 | 3 | 21852 | 29173 | 29354 | 3 | 28 | 4000 | 2000 | 2000 | 4000 | 6000 | 29355 | 29429 | 1 | 1 | 61001 | 1000 | 1000 | 2000 | 0 | 4 | 2 | 2000 | 0 | 0 | 0 | 2002 | 0 | 4 | 2 | 1 | 0 | 12994 | 9422 | 6964 | 3138 | 6 | 46 | 20353 | 3234 | 3817 | 13 | 49 | 48 | 28667 | 16088 | 13008 | 14647 | 2000 | 2000 | 29306 | 29354 | 29356 | 29340 | 29163 |
64004 | 29325 | 235 | 1 | 21 | 1 | 0 | 18 | 1 | 0 | 0 | 21 | 0 | 0 | 4560 | 29157 | 0 | 0 | 18094 | 4000 | 2000 | 2000 | 2000 | 2000 | 21616 | 16000 | 0 | 0 | 21797 | 29086 | 29469 | 3 | 10 | 4000 | 2000 | 2000 | 4004 | 6000 | 29273 | 29189 | 1 | 1 | 61001 | 1000 | 1000 | 2004 | 2 | 6 | 0 | 2002 | 0 | 1 | 387 | 2000 | 2 | 4 | 2 | 0 | 0 | 13040 | 9535 | 6907 | 3153 | 6 | 45 | 20214 | 3205 | 3809 | 9 | 47 | 48 | 28703 | 16356 | 13176 | 14399 | 2000 | 2000 | 29251 | 29312 | 29296 | 29305 | 29285 |
64004 | 29285 | 237 | 0 | 21 | 1 | 0 | 19 | 0 | 0 | 0 | 0 | 3 | 0 | 4713 | 29185 | 2 | 2 | 18179 | 4000 | 2000 | 2000 | 2000 | 2000 | 21613 | 16000 | 0 | 4 | 21842 | 29080 | 29368 | 3 | 10 | 4000 | 2002 | 2000 | 4000 | 6000 | 29270 | 29131 | 1 | 1 | 61001 | 1000 | 1000 | 2000 | 2 | 4 | 0 | 2000 | 0 | 0 | 0 | 2000 | 0 | 6 | 2 | 0 | 0 | 13041 | 9508 | 6943 | 3125 | 8 | 51 | 20310 | 3205 | 3818 | 10 | 47 | 53 | 28658 | 15988 | 13441 | 14728 | 2000 | 2000 | 29358 | 29321 | 29232 | 29457 | 29372 |
64004 | 29327 | 236 | 1 | 17 | 1 | 1 | 22 | 1 | 0 | 0 | 219 | 133 | 0 | 4636 | 29263 | 2 | 0 | 18298 | 4000 | 2000 | 2000 | 2000 | 2000 | 21631 | 16000 | 0 | 9 | 21778 | 28992 | 29296 | 3 | 10 | 4000 | 2000 | 2000 | 4000 | 6000 | 29282 | 29349 | 1 | 1 | 61001 | 1000 | 1000 | 2004 | 3 | 6 | 3 | 2002 | 0 | 0 | 2 | 2002 | 2 | 8 | 2 | 0 | 0 | 13160 | 9458 | 6990 | 3144 | 4 | 43 | 20286 | 3231 | 3813 | 13 | 48 | 46 | 28623 | 16030 | 13276 | 14655 | 2000 | 2000 | 29219 | 29243 | 29405 | 29348 | 29326 |
64004 | 29267 | 236 | 0 | 18 | 0 | 0 | 19 | 0 | 0 | 0 | 27 | 3 | 0 | 4603 | 29185 | 0 | 2 | 18172 | 4004 | 2000 | 2000 | 2000 | 2000 | 21614 | 16000 | 0 | 3 | 21828 | 29151 | 29230 | 3 | 27 | 4000 | 2000 | 2000 | 4000 | 6000 | 29243 | 29209 | 1 | 1 | 61001 | 1000 | 1000 | 2000 | 0 | 6 | 0 | 2000 | 0 | 0 | 425 | 2000 | 0 | 4 | 2 | 2 | 0 | 13009 | 9579 | 6912 | 3128 | 9 | 38 | 20353 | 3239 | 3808 | 12 | 46 | 45 | 28608 | 15951 | 13240 | 14776 | 2000 | 2000 | 29213 | 29279 | 29311 | 29349 | 29387 |
64004 | 29288 | 236 | 1 | 17 | 1 | 1 | 17 | 2 | 1 | 0 | 33 | 1 | 0 | 4603 | 29114 | 0 | 0 | 18136 | 4000 | 2000 | 2000 | 2002 | 2000 | 21610 | 16000 | 0 | 5 | 21795 | 29010 | 29320 | 3 | 10 | 4000 | 2000 | 2000 | 4000 | 6000 | 29230 | 29270 | 1 | 1 | 61001 | 1000 | 1000 | 2003 | 2 | 4 | 1 | 2004 | 0 | 1 | 2 | 2000 | 2 | 8 | 2 | 0 | 0 | 13365 | 9294 | 6954 | 3184 | 7 | 49 | 20376 | 3234 | 3812 | 11 | 44 | 40 | 28489 | 16006 | 13370 | 14979 | 2000 | 2000 | 29501 | 29540 | 29334 | 29302 | 29349 |
64004 | 29278 | 236 | 0 | 18 | 0 | 0 | 21 | 0 | 0 | 0 | 24 | 3 | 0 | 4633 | 29099 | 2 | 0 | 18387 | 4000 | 2000 | 2000 | 2000 | 2000 | 21618 | 16000 | 0 | 1 | 21757 | 29012 | 29317 | 3 | 10 | 4000 | 2000 | 2000 | 4000 | 6000 | 29260 | 29283 | 1 | 1 | 61001 | 1000 | 1000 | 2000 | 0 | 4 | 0 | 2000 | 0 | 0 | 0 | 2000 | 0 | 6 | 2 | 0 | 0 | 13172 | 9463 | 6931 | 3046 | 8 | 44 | 20315 | 3262 | 3813 | 25 | 49 | 44 | 28672 | 16137 | 13121 | 14917 | 2000 | 2000 | 29472 | 29474 | 29327 | 29374 | 29387 |
64004 | 29395 | 235 | 1 | 20 | 1 | 1 | 20 | 1 | 0 | 0 | 33 | 0 | 0 | 4662 | 29221 | 0 | 0 | 18279 | 4000 | 2000 | 2000 | 2000 | 2000 | 21616 | 16000 | 0 | 0 | 21830 | 29165 | 29362 | 3 | 10 | 4000 | 2000 | 2000 | 4000 | 6000 | 29297 | 29314 | 1 | 1 | 61001 | 1000 | 1000 | 2003 | 3 | 6 | 1 | 2002 | 0 | 1 | 2 | 2000 | 2 | 4 | 2 | 0 | 0 | 13024 | 9482 | 6948 | 3133 | 4 | 42 | 20479 | 3287 | 3815 | 13 | 48 | 44 | 28657 | 16301 | 13086 | 14737 | 2000 | 2000 | 29427 | 29512 | 29338 | 29330 | 29086 |
Count: 8
Code:
st3 { v0.d, v1.d, v2.d }[1], [x6] st3 { v0.d, v1.d, v2.d }[1], [x6] st3 { v0.d, v1.d, v2.d }[1], [x6] st3 { v0.d, v1.d, v2.d }[1], [x6] st3 { v0.d, v1.d, v2.d }[1], [x6] st3 { v0.d, v1.d, v2.d }[1], [x6] st3 { v0.d, v1.d, v2.d }[1], [x6] st3 { v0.d, v1.d, v2.d }[1], [x6]
mov x7, x6 mov x8, x6 mov x9, x6 mov x10, x6 mov x11, x6 mov x12, x6 mov x13, x6
(fused SUBS/B.cc loop)
Result (median cycles for code divided by count): 1.0006
retire uop (01) | cycle (02) | 03 | l1d tlb fill (05) | mmu table walk instruction (07) | mmu table walk data (08) | l2 tlb miss instruction (0a) | l2 tlb miss data (0b) | 18 | 19 | 1e | 1f | 23 | 37 | 3a | 3f | 46 | 49 | 4f | 51 | schedule uop (52) | schedule int uop (53) | schedule simd uop (54) | schedule ldst uop (55) | dispatch int uop (56) | dispatch simd uop (57) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | ldst uops in schedulers (5b) | 69 | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map simd uop (7e) | map int uop inputs (7f) | map ldst uop inputs (80) | map simd uop inputs (81) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int alu (97) | inst simd store (99) | inst ldst (9b) | 9f | l1d tlb access (a0) | l1d tlb miss (a1) | l1d cache miss st (a2) | a4 | ld unit uop (a6) | st unit uop (a7) | l1d cache writeback (a8) | a9 | ac | af | bc | l1d cache miss st nonspec (c0) | l1d tlb miss nonspec (c1) | c2 | cd | cf | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ? ldst retires (ed) | ? simd retires (ee) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
320207 | 80058 | 620 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 21 | 3 | 0 | 5858 | 0 | 80037 | 16 | 0 | 0 | 25 | 326323 | 100 | 165704 | 160000 | 100 | 160000 | 160000 | 500 | 2158234 | 1299350 | 80023 | 80045 | 80045 | 0 | 3 | 26 | 320100 | 200 | 160000 | 160000 | 200 | 320000 | 480000 | 80045 | 80045 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 160000 | 0 | 0 | 406 | 0 | 160002 | 0 | 0 | 2 | 160002 | 2 | 34 | 0 | 0 | 0 | 5109 | 8 | 17 | 8 | 4 | 80042 | 160000 | 160000 | 100 | 80046 | 80046 | 80050 | 80047 | 80048 |
320204 | 80049 | 621 | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 9 | 0 | 5864 | 0 | 80029 | 0 | 16 | 0 | 25 | 325440 | 100 | 165322 | 160000 | 100 | 160000 | 160000 | 500 | 2290786 | 1302070 | 80022 | 80045 | 80044 | 0 | 3 | 27 | 320100 | 200 | 160000 | 160000 | 200 | 320000 | 480000 | 80046 | 80048 | 2 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 160014 | 14 | 36 | 0 | 0 | 160016 | 0 | 0 | 19 | 160002 | 16 | 36 | 14 | 1 | 0 | 5109 | 11 | 17 | 9 | 10 | 80047 | 160000 | 160000 | 100 | 80051 | 80051 | 80051 | 80052 | 80051 |
320204 | 80052 | 621 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 96 | 18 | 0 | 1625 | 1 | 80035 | 16 | 0 | 0 | 25 | 326865 | 100 | 166823 | 160000 | 100 | 160000 | 160000 | 500 | 3565532 | 1297271 | 80025 | 80051 | 80050 | 0 | 3 | 40 | 320100 | 200 | 160000 | 160000 | 200 | 320000 | 480000 | 80058 | 80059 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 160015 | 14 | 36 | 0 | 0 | 160016 | 0 | 0 | 16 | 160002 | 16 | 36 | 14 | 0 | 0 | 5109 | 8 | 17 | 8 | 8 | 80049 | 160000 | 160000 | 100 | 80059 | 80050 | 80051 | 80059 | 80059 |
320204 | 80050 | 620 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 15 | 18 | 0 | 6111 | 1 | 80043 | 16 | 14 | 0 | 25 | 324801 | 100 | 161224 | 160000 | 100 | 160000 | 160000 | 500 | 2559886 | 1300924 | 80025 | 80060 | 80058 | 0 | 3 | 42 | 320100 | 200 | 160000 | 160000 | 200 | 320000 | 480000 | 80051 | 80051 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 160014 | 15 | 36 | 0 | 0 | 160016 | 1 | 1 | 19 | 160000 | 16 | 36 | 14 | 0 | 0 | 5109 | 4 | 17 | 9 | 4 | 80057 | 160000 | 160000 | 100 | 80061 | 80052 | 80060 | 80060 | 80060 |
320204 | 80050 | 620 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 19 | 0 | 5154 | 1 | 80037 | 16 | 16 | 0 | 25 | 325778 | 100 | 165272 | 160000 | 100 | 160000 | 160000 | 500 | 3679133 | 1297190 | 80036 | 80050 | 80058 | 0 | 3 | 40 | 320100 | 200 | 160000 | 160000 | 200 | 320000 | 480000 | 80058 | 80057 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 160014 | 14 | 36 | 9 | 0 | 160016 | 0 | 0 | 18 | 160002 | 14 | 0 | 14 | 1 | 0 | 5109 | 7 | 17 | 4 | 7 | 80056 | 160000 | 160000 | 100 | 80061 | 80052 | 80059 | 80050 | 80051 |
320204 | 80050 | 621 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 21 | 21 | 0 | 5891 | 1 | 80044 | 16 | 16 | 16 | 25 | 325296 | 100 | 164708 | 160000 | 100 | 160000 | 160000 | 500 | 3679304 | 1300983 | 80033 | 80050 | 80050 | 0 | 3 | 32 | 320100 | 200 | 160000 | 160000 | 200 | 320000 | 480000 | 80058 | 80226 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 160014 | 14 | 36 | 0 | 1 | 160016 | 0 | 0 | 24 | 160002 | 16 | 36 | 14 | 0 | 0 | 5109 | 8 | 17 | 10 | 9 | 80047 | 160000 | 160000 | 100 | 80052 | 80058 | 80050 | 80060 | 80051 |
320204 | 80060 | 643 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 18 | 0 | 5872 | 1 | 80044 | 16 | 16 | 0 | 46 | 325392 | 100 | 164785 | 160000 | 100 | 160000 | 160000 | 500 | 2399920 | 1297347 | 80195 | 80050 | 80049 | 0 | 3 | 32 | 320100 | 200 | 160000 | 160000 | 200 | 320000 | 480000 | 80220 | 80050 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 160015 | 14 | 0 | 0 | 0 | 160000 | 11 | 0 | 2 | 160002 | 2 | 34 | 0 | 0 | 0 | 5109 | 8 | 17 | 7 | 8 | 80045 | 160000 | 160000 | 100 | 80049 | 80046 | 80046 | 80050 | 80045 |
320204 | 80044 | 621 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 9 | 0 | 7265 | 0 | 80034 | 16 | 16 | 0 | 25 | 325119 | 100 | 164194 | 160000 | 100 | 160000 | 160000 | 500 | 2077914 | 1302701 | 80023 | 80049 | 80049 | 0 | 3 | 26 | 320100 | 200 | 160000 | 160000 | 200 | 320000 | 480000 | 80044 | 80044 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 160000 | 0 | 34 | 0 | 0 | 160000 | 3 | 0 | 925 | 160002 | 2 | 34 | 0 | 0 | 0 | 5109 | 8 | 17 | 8 | 9 | 80042 | 160000 | 160000 | 100 | 80045 | 80218 | 80046 | 80045 | 80045 |
320204 | 80044 | 620 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0 | 6520 | 0 | 80029 | 16 | 16 | 0 | 25 | 325943 | 100 | 164392 | 160000 | 100 | 160000 | 160108 | 500 | 2158255 | 1295615 | 80024 | 80049 | 80045 | 82 | 3 | 26 | 320100 | 200 | 160000 | 160000 | 200 | 320000 | 480000 | 80045 | 80045 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 160000 | 0 | 34 | 0 | 0 | 160002 | 0 | 0 | 8 | 160002 | 2 | 34 | 0 | 0 | 0 | 5109 | 8 | 17 | 8 | 8 | 80042 | 160000 | 160000 | 100 | 80046 | 80046 | 80050 | 80045 | 80046 |
320204 | 80044 | 621 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0 | 5331 | 0 | 80029 | 16 | 16 | 0 | 25 | 326936 | 100 | 167215 | 160000 | 100 | 160000 | 160000 | 500 | 2159396 | 1295139 | 80023 | 80049 | 80044 | 0 | 3 | 27 | 320100 | 200 | 160000 | 160000 | 200 | 320000 | 480000 | 80045 | 80044 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 160000 | 0 | 34 | 0 | 0 | 160002 | 0 | 0 | 922 | 160002 | 2 | 0 | 0 | 0 | 0 | 5109 | 9 | 17 | 10 | 4 | 80129 | 160000 | 160000 | 100 | 80050 | 80045 | 80045 | 80050 | 80050 |
Result (median cycles for code divided by count): 1.0006
retire uop (01) | cycle (02) | 03 | l1i tlb fill (04) | mmu table walk data (08) | 09 | l2 tlb miss data (0b) | 18 | 19 | 1e | 1f | 24 | 37 | 3a | 3f | 46 | 49 | 4f | 51 | schedule uop (52) | schedule int uop (53) | schedule simd uop (54) | schedule ldst uop (55) | dispatch int uop (56) | dispatch simd uop (57) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | ldst uops in schedulers (5b) | 60 | 69 | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map simd uop (7e) | map int uop inputs (7f) | map ldst uop inputs (80) | map simd uop inputs (81) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int alu (97) | inst simd store (99) | inst ldst (9b) | 9f | l1d tlb access (a0) | l1d tlb miss (a1) | l1d cache miss st (a2) | a4 | ld unit uop (a6) | st unit uop (a7) | l1d cache writeback (a8) | a9 | ac | af | bc | l1d cache miss st nonspec (c0) | c2 | cd | cf | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ? ldst retires (ed) | ? simd retires (ee) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
320027 | 80058 | 621 | 1 | 0 | 0 | 0 | 0 | 0 | 12 | 9 | 0 | 6102 | 0 | 80030 | 16 | 16 | 0 | 25 | 324025 | 10 | 165704 | 160000 | 10 | 160000 | 160000 | 50 | 2319283 | 1294633 | 0 | 80024 | 80044 | 80045 | 0 | 3 | 33 | 320010 | 20 | 160000 | 160000 | 20 | 320000 | 480000 | 80048 | 80049 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 160000 | 0 | 38 | 0 | 0 | 160000 | 0 | 0 | 8 | 160002 | 2 | 34 | 0 | 0 | 5022 | 13 | 17 | 15 | 7 | 80047 | 160000 | 160000 | 10 | 80051 | 80060 | 80051 | 80045 | 80045 |
320024 | 80045 | 620 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0 | 4566 | 0 | 80029 | 0 | 16 | 0 | 25 | 323898 | 10 | 163582 | 160000 | 10 | 160000 | 160000 | 50 | 2239239 | 1295839 | 0 | 80023 | 80044 | 80045 | 0 | 3 | 26 | 320010 | 20 | 160000 | 160120 | 20 | 320000 | 480360 | 83101 | 81200 | 2 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 160000 | 4 | 34 | 63 | 0 | 160060 | 0 | 2 | 917 | 160122 | 0 | 34 | 0 | 0 | 5019 | 21 | 179 | 7 | 10 | 80357 | 160000 | 160000 | 10 | 80220 | 80210 | 80377 | 80212 | 80209 |
320024 | 80210 | 622 | 0 | 0 | 0 | 0 | 1 | 1 | 132 | 185 | 0 | 4407 | 0 | 80355 | 16 | 0 | 89 | 49 | 322391 | 10 | 166103 | 160120 | 10 | 160118 | 160108 | 50 | 2147975 | 1295919 | 0 | 80327 | 80209 | 80209 | 81 | 6 | 224 | 320462 | 20 | 160120 | 160120 | 20 | 320480 | 480360 | 80044 | 80216 | 2 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 160060 | 2 | 34 | 62 | 0 | 160002 | 0 | 0 | 928 | 160062 | 2 | 34 | 0 | 0 | 5019 | 12 | 17 | 12 | 6 | 80049 | 160000 | 160000 | 10 | 80051 | 80059 | 80062 | 80046 | 80045 |
320024 | 80046 | 620 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 6874 | 0 | 80029 | 16 | 16 | 0 | 25 | 324221 | 10 | 167451 | 160000 | 10 | 160000 | 160000 | 50 | 2157445 | 1297117 | 0 | 80022 | 80048 | 80049 | 0 | 3 | 27 | 320010 | 20 | 160000 | 160000 | 20 | 320000 | 480000 | 80045 | 80045 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 160000 | 0 | 34 | 0 | 0 | 160002 | 0 | 0 | 2 | 160002 | 2 | 0 | 0 | 0 | 5019 | 11 | 17 | 7 | 12 | 80044 | 160000 | 160000 | 10 | 80052 | 80051 | 80045 | 80044 | 80045 |
320024 | 80044 | 621 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0 | 5911 | 0 | 80030 | 16 | 16 | 0 | 25 | 323976 | 10 | 164796 | 160000 | 10 | 160000 | 160000 | 50 | 2228137 | 1300903 | 0 | 80023 | 80048 | 80049 | 0 | 3 | 26 | 320010 | 20 | 160000 | 160000 | 20 | 320000 | 480000 | 80044 | 80045 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 160000 | 0 | 34 | 0 | 0 | 160002 | 0 | 0 | 2 | 160002 | 2 | 34 | 0 | 0 | 5019 | 5 | 17 | 12 | 12 | 80056 | 160000 | 160000 | 10 | 80059 | 80061 | 80052 | 80046 | 80046 |
320024 | 80044 | 620 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 9 | 0 | 6496 | 0 | 80030 | 16 | 16 | 0 | 25 | 325991 | 10 | 164046 | 160000 | 10 | 160000 | 160000 | 50 | 2159548 | 1300476 | 0 | 80023 | 80044 | 80044 | 0 | 3 | 27 | 320010 | 20 | 160000 | 160000 | 20 | 320000 | 480000 | 80046 | 80044 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 160000 | 0 | 34 | 0 | 0 | 160002 | 0 | 0 | 5 | 160000 | 2 | 34 | 0 | 0 | 5021 | 11 | 17 | 12 | 6 | 80047 | 160000 | 160000 | 10 | 80052 | 80052 | 80050 | 80045 | 80047 |
320024 | 80044 | 620 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0 | 6166 | 0 | 80030 | 16 | 16 | 0 | 25 | 324420 | 10 | 164299 | 160000 | 10 | 160000 | 160000 | 50 | 2398907 | 1781398 | 0 | 80024 | 80045 | 80045 | 0 | 3 | 26 | 320010 | 20 | 160000 | 160000 | 20 | 320000 | 480000 | 80044 | 80044 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 160000 | 0 | 34 | 0 | 0 | 160002 | 0 | 0 | 2 | 160002 | 2 | 34 | 0 | 0 | 5019 | 6 | 17 | 8 | 12 | 80047 | 160000 | 160000 | 10 | 80060 | 80060 | 80051 | 80046 | 80045 |
320024 | 80044 | 620 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 9 | 0 | 4499 | 0 | 80029 | 16 | 0 | 0 | 25 | 325921 | 10 | 164069 | 160000 | 10 | 160000 | 160000 | 50 | 2383768 | 1294864 | 0 | 80024 | 80044 | 80045 | 0 | 3 | 30 | 320010 | 20 | 160000 | 160000 | 20 | 320000 | 480000 | 80049 | 80049 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 160000 | 0 | 34 | 0 | 0 | 160002 | 0 | 0 | 2 | 160002 | 2 | 34 | 0 | 0 | 5019 | 6 | 17 | 13 | 13 | 80047 | 160000 | 160000 | 10 | 80228 | 80045 | 80049 | 80046 | 80045 |
320024 | 80045 | 620 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0 | 4130 | 0 | 80030 | 0 | 16 | 0 | 33 | 326302 | 10 | 166611 | 160060 | 10 | 160000 | 160000 | 50 | 2079380 | 1294133 | 0 | 80025 | 80045 | 80045 | 0 | 3 | 26 | 320010 | 20 | 160000 | 160000 | 20 | 320000 | 480000 | 80044 | 80045 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 160000 | 0 | 34 | 0 | 0 | 160002 | 0 | 0 | 0 | 160002 | 2 | 34 | 0 | 0 | 5019 | 12 | 17 | 10 | 12 | 80056 | 160000 | 160000 | 10 | 80059 | 80059 | 80131 | 80046 | 80049 |
320024 | 80049 | 620 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0 | 3821 | 0 | 80034 | 16 | 16 | 0 | 25 | 323385 | 10 | 164419 | 160000 | 10 | 160000 | 160000 | 50 | 2319107 | 1294694 | 0 | 80025 | 80044 | 80044 | 0 | 3 | 27 | 320010 | 20 | 160000 | 160000 | 20 | 320000 | 480000 | 80044 | 80045 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 160000 | 0 | 34 | 0 | 0 | 160002 | 0 | 0 | 7 | 160002 | 2 | 34 | 0 | 0 | 5019 | 12 | 17 | 13 | 13 | 80056 | 160000 | 160000 | 10 | 81220 | 80045 | 80046 | 80045 | 80046 |