Apple Microarchitecture Research by Dougall Johnson M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions M1/A14 E-core (Icestorm): Overview | Base Instructions | SIMD and FP Instructions
Code:
st3 { v0.s, v1.s, v2.s }[1], [x6] nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop
mov x0, 0
(no loop instructions)
Retires (minus 60 nops): 2.000
Issues: 2.000
Integer unit issues: 0.000
Load/store unit issues: 1.000
SIMD/FP unit issues: 1.000
retire uop (01) | cycle (02) | 03 | l1i tlb fill (04) | mmu table walk instruction (07) | mmu table walk data (08) | 09 | l2 tlb miss instruction (0a) | l2 tlb miss data (0b) | 18 | 19 | 1e | 1f | 22 | 24 | 3a | 3f | 46 | 49 | 51 | schedule uop (52) | schedule simd uop (54) | schedule ldst uop (55) | dispatch simd uop (57) | dispatch ldst uop (58) | simd uops in schedulers (5a) | ldst uops in schedulers (5b) | 5f | 60 | 61 | 69 | 6d | 6e | map rewind (75) | map stall (76) | dispatch uop (78) | map ldst uop (7d) | map simd uop (7e) | map ldst uop inputs (80) | map simd uop inputs (81) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst simd store (99) | inst ldst (9b) | l1d tlb access (a0) | l1d tlb miss (a1) | l1d cache miss st (a2) | ld unit uop (a6) | st unit uop (a7) | l1d cache writeback (a8) | a9 | ac | af | l1d cache miss st nonspec (c0) | c2 | c9 | cf | d0 | d2 | l1i cache miss demand (d3) | l1i tlb miss demand (d4) | d5 | map dispatch bubble (d6) | d9 | da | db | dd | fetch restart (de) | e0 | ea | eb | ec | ? ldst retires (ed) | ? simd retires (ee) | f5 | f6 | f7 | f8 | fd |
62006 | 29007 | 233 | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | 3 | 2 | 0 | 0 | 4642 | 29184 | 0 | 0 | 18210 | 2000 | 1000 | 1000 | 1000 | 1000 | 10904 | 8000 | 14 | 0 | 0 | 21709 | 28746 | 29039 | 3 | 10 | 2000 | 1000 | 1000 | 2000 | 3000 | 28813 | 28871 | 1 | 1 | 61001 | 1000 | 1000 | 1000 | 0 | 3 | 0 | 1000 | 2 | 0 | 0 | 1000 | 0 | 0 | 0 | 13081 | 9169 | 7016 | 3133 | 0 | 66 | 20353 | 3219 | 3818 | 28 | 70 | 72 | 28341 | 16483 | 12991 | 14836 | 1000 | 1000 | 29459 | 29541 | 29540 | 29578 | 29307 |
62004 | 29140 | 232 | 0 | 3 | 0 | 0 | 3 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 4705 | 28972 | 0 | 1 | 18097 | 2000 | 1000 | 1000 | 1000 | 1000 | 10910 | 8000 | 5 | 0 | 0 | 21716 | 28669 | 28865 | 3 | 10 | 2000 | 1000 | 1000 | 2000 | 3000 | 28970 | 29046 | 1 | 1 | 61001 | 1000 | 1000 | 1000 | 0 | 0 | 0 | 1000 | 0 | 0 | 0 | 1000 | 2 | 0 | 0 | 13209 | 9098 | 6963 | 3140 | 1 | 68 | 20236 | 3220 | 3825 | 15 | 80 | 70 | 28374 | 15719 | 13076 | 14306 | 1000 | 1000 | 29241 | 29371 | 29158 | 29298 | 29009 |
62004 | 29183 | 234 | 0 | 2 | 0 | 0 | 2 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 4752 | 28805 | 0 | 1 | 17993 | 2000 | 1000 | 1000 | 1000 | 1000 | 10908 | 8000 | 1 | 0 | 0 | 21719 | 28778 | 28932 | 3 | 10 | 2000 | 1000 | 1000 | 2000 | 3000 | 29042 | 28879 | 1 | 1 | 61001 | 1000 | 1000 | 1000 | 0 | 2 | 0 | 1000 | 0 | 0 | 0 | 1000 | 2 | 0 | 0 | 13259 | 9308 | 6890 | 3157 | 1 | 73 | 20322 | 3259 | 3831 | 16 | 76 | 76 | 28589 | 15817 | 12958 | 14056 | 1000 | 1000 | 29035 | 28988 | 29025 | 28950 | 28949 |
62004 | 29243 | 233 | 0 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 4751 | 29104 | 0 | 0 | 18193 | 2000 | 1000 | 1000 | 1000 | 1000 | 10902 | 8000 | 3 | 0 | 0 | 21698 | 28893 | 29150 | 3 | 10 | 2000 | 1000 | 1000 | 2000 | 3000 | 29110 | 29147 | 1 | 1 | 61001 | 1000 | 1000 | 1007 | 7 | 3 | 0 | 1000 | 0 | 0 | 0 | 1000 | 2 | 0 | 0 | 13138 | 9427 | 6921 | 3099 | 0 | 62 | 20474 | 3201 | 3823 | 25 | 73 | 67 | 28595 | 15889 | 13108 | 14684 | 1000 | 1000 | 29190 | 29226 | 29133 | 29140 | 29253 |
62004 | 29240 | 236 | 0 | 4 | 0 | 0 | 3 | 0 | 0 | 0 | 15 | 0 | 0 | 0 | 4586 | 29008 | 0 | 0 | 18251 | 2000 | 1000 | 1001 | 1002 | 1000 | 10921 | 8008 | 5 | 0 | 0 | 21698 | 28897 | 29333 | 8 | 29 | 2002 | 1001 | 1000 | 2000 | 3003 | 29138 | 29053 | 2 | 1 | 61001 | 1000 | 1000 | 1003 | 2 | 3 | 0 | 1001 | 0 | 2 | 425 | 1000 | 2 | 2 | 327 | 13073 | 9207 | 6898 | 3123 | 2 | 65 | 20598 | 3249 | 3827 | 21 | 73 | 76 | 28668 | 15946 | 13032 | 14864 | 1000 | 1000 | 29198 | 29215 | 29207 | 29077 | 29238 |
62004 | 29215 | 236 | 0 | 1 | 0 | 1 | 2 | 0 | 1 | 1 | 279 | 177 | 0 | 0 | 4588 | 29059 | 0 | 1 | 18097 | 2002 | 1001 | 1000 | 1001 | 1002 | 10911 | 8008 | 3 | 0 | 0 | 21731 | 28979 | 29110 | 9 | 46 | 2002 | 1001 | 1000 | 2002 | 3003 | 29081 | 29243 | 2 | 1 | 61001 | 1000 | 1000 | 1002 | 0 | 2 | 2 | 1001 | 0 | 4 | 470 | 1001 | 3 | 2 | 0 | 13047 | 9333 | 6900 | 3107 | 1 | 71 | 20500 | 3283 | 3819 | 24 | 72 | 72 | 28554 | 16215 | 13005 | 14641 | 1000 | 1000 | 29303 | 29154 | 29293 | 28991 | 29078 |
62004 | 29329 | 235 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 147 | 265 | 0 | 0 | 4640 | 29007 | 0 | 0 | 18352 | 2000 | 1000 | 1000 | 1000 | 1000 | 10899 | 8000 | 5 | 0 | 0 | 21683 | 28649 | 28970 | 3 | 10 | 2000 | 1000 | 1000 | 2000 | 3000 | 29021 | 28932 | 1 | 1 | 61001 | 1000 | 1000 | 1000 | 0 | 2 | 0 | 1000 | 0 | 2 | 0 | 1000 | 0 | 0 | 0 | 13171 | 9255 | 6944 | 3127 | 0 | 87 | 20471 | 3204 | 3826 | 15 | 73 | 77 | 28419 | 15659 | 13174 | 14387 | 1000 | 1000 | 29005 | 28886 | 29059 | 28901 | 28962 |
62004 | 29036 | 232 | 0 | 1 | 0 | 0 | 2 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 4783 | 28849 | 1 | 1 | 18001 | 2000 | 1000 | 1000 | 1000 | 1000 | 10906 | 8000 | 4 | 0 | 0 | 21786 | 28775 | 29021 | 3 | 10 | 2000 | 1000 | 1000 | 2002 | 3000 | 28746 | 28884 | 1 | 1 | 61001 | 1000 | 1000 | 1000 | 0 | 3 | 0 | 1000 | 1 | 0 | 0 | 1000 | 0 | 0 | 0 | 13102 | 9544 | 6925 | 3107 | 1 | 63 | 20308 | 3151 | 3830 | 19 | 77 | 86 | 28388 | 15613 | 12819 | 14447 | 1000 | 1000 | 29028 | 29029 | 28949 | 29030 | 28934 |
62004 | 28879 | 232 | 0 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | 135 | 0 | 0 | 0 | 4631 | 28803 | 0 | 1 | 17977 | 2000 | 1000 | 1000 | 1000 | 1000 | 10910 | 8000 | 0 | 0 | 0 | 21722 | 28695 | 29027 | 3 | 30 | 2000 | 1000 | 1000 | 2000 | 3000 | 28998 | 28801 | 1 | 1 | 61001 | 1000 | 1000 | 1000 | 0 | 3 | 0 | 1000 | 1 | 0 | 475 | 1000 | 0 | 0 | 0 | 13126 | 9394 | 6939 | 3192 | 0 | 74 | 20294 | 3246 | 3826 | 19 | 78 | 76 | 28389 | 15698 | 12956 | 14330 | 1000 | 1000 | 28876 | 28882 | 29009 | 29139 | 28982 |
62004 | 28997 | 232 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 12 | 0 | 0 | 0 | 4689 | 28833 | 0 | 0 | 18036 | 2000 | 1000 | 1000 | 1000 | 1000 | 10899 | 8000 | 5 | 0 | 0 | 21713 | 28814 | 29015 | 7 | 10 | 2000 | 1000 | 1000 | 2000 | 3000 | 28843 | 28815 | 1 | 1 | 61001 | 1000 | 1000 | 1000 | 0 | 2 | 0 | 1000 | 0 | 0 | 395 | 1000 | 3 | 0 | 0 | 13010 | 9346 | 6929 | 3155 | 0 | 62 | 20281 | 3250 | 3831 | 25 | 76 | 66 | 28415 | 15786 | 13113 | 14563 | 1000 | 1000 | 28892 | 28942 | 29094 | 28902 | 29037 |
Count: 8
Code:
st3 { v0.s, v1.s, v2.s }[1], [x6] st3 { v0.s, v1.s, v2.s }[1], [x6] st3 { v0.s, v1.s, v2.s }[1], [x6] st3 { v0.s, v1.s, v2.s }[1], [x6] st3 { v0.s, v1.s, v2.s }[1], [x6] st3 { v0.s, v1.s, v2.s }[1], [x6] st3 { v0.s, v1.s, v2.s }[1], [x6] st3 { v0.s, v1.s, v2.s }[1], [x6]
mov x7, x6 mov x8, x6 mov x9, x6 mov x10, x6 mov x11, x6 mov x12, x6 mov x13, x6
(fused SUBS/B.cc loop)
Result (median cycles for code divided by count): 0.5005
retire uop (01) | cycle (02) | 03 | mmu table walk data (08) | 09 | l2 tlb miss data (0b) | 18 | 19 | 1e | 1f | 22 | 24 | 37 | 3a | 3f | 46 | 49 | 4f | 50 | 51 | schedule uop (52) | schedule int uop (53) | schedule simd uop (54) | schedule ldst uop (55) | dispatch int uop (56) | dispatch simd uop (57) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | ldst uops in schedulers (5b) | 60 | 69 | 6d | 6e | map stall dispatch (70) | rob full (74) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map simd uop (7e) | map int uop inputs (7f) | map ldst uop inputs (80) | map simd uop inputs (81) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int alu (97) | inst simd store (99) | inst ldst (9b) | 9f | l1d tlb access (a0) | l1d tlb miss (a1) | l1d cache miss st (a2) | a4 | ld unit uop (a6) | st unit uop (a7) | l1d cache writeback (a8) | ac | af | bc | l1d cache miss st nonspec (c0) | c2 | cf | d0 | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ? int output thing (e9) | ? ldst retires (ed) | ? simd retires (ee) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
160206 | 40057 | 310 | 0 | 0 | 0 | 0 | 0 | 9 | 6 | 0 | 0 | 3963 | 0 | 40027 | 16 | 16 | 0 | 0 | 25 | 161111 | 100 | 83440 | 80000 | 100 | 80000 | 80000 | 500 | 1839712 | 642734 | 0 | 40021 | 40049 | 40042 | 19959 | 0 | 3 | 20000 | 160100 | 200 | 80000 | 80000 | 200 | 160000 | 240000 | 40043 | 40042 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 80000 | 0 | 34 | 0 | 0 | 80002 | 0 | 2 | 80002 | 2 | 34 | 0 | 5110 | 0 | 1 | 16 | 1 | 1 | 40039 | 0 | 80000 | 80000 | 100 | 40043 | 40044 | 40043 | 40044 | 40043 |
160204 | 40043 | 310 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 1025 | 0 | 40027 | 16 | 16 | 0 | 0 | 25 | 161242 | 100 | 83340 | 80000 | 100 | 80000 | 80000 | 500 | 1839856 | 642959 | 0 | 40021 | 40042 | 40042 | 19959 | 0 | 3 | 20001 | 160100 | 200 | 80000 | 80000 | 200 | 160000 | 240000 | 40042 | 40043 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 80000 | 0 | 34 | 0 | 0 | 80002 | 0 | 5 | 80002 | 2 | 34 | 0 | 5110 | 3 | 1 | 16 | 1 | 1 | 40049 | 0 | 80000 | 80000 | 100 | 40044 | 40043 | 40043 | 40043 | 40043 |
160204 | 40049 | 311 | 0 | 0 | 0 | 0 | 0 | 12 | 3 | 1 | 0 | 2631 | 0 | 40034 | 16 | 0 | 0 | 0 | 25 | 161486 | 100 | 82935 | 80000 | 100 | 80000 | 80000 | 500 | 1839712 | 647961 | 1 | 40023 | 40042 | 40048 | 19959 | 0 | 3 | 20007 | 160100 | 200 | 80000 | 80000 | 200 | 160000 | 240000 | 40042 | 40049 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 80000 | 0 | 34 | 0 | 0 | 80002 | 0 | 2 | 80000 | 2 | 34 | 0 | 5110 | 0 | 1 | 16 | 1 | 1 | 40039 | 0 | 80000 | 80000 | 100 | 40050 | 40043 | 40049 | 40050 | 40043 |
160204 | 40043 | 311 | 0 | 0 | 0 | 0 | 0 | 12 | 0 | 0 | 0 | 2814 | 0 | 40034 | 16 | 0 | 0 | 0 | 25 | 162086 | 100 | 81434 | 80000 | 100 | 80000 | 80000 | 500 | 1839712 | 644392 | 0 | 40021 | 40042 | 40043 | 19959 | 0 | 3 | 20001 | 160100 | 200 | 80000 | 80000 | 200 | 160000 | 240000 | 40043 | 40052 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 80000 | 0 | 34 | 0 | 0 | 80002 | 0 | 2 | 80002 | 2 | 34 | 0 | 5110 | 0 | 1 | 16 | 1 | 1 | 40040 | 0 | 80000 | 80000 | 100 | 40049 | 40049 | 40050 | 40049 | 41004 |
160204 | 40042 | 311 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2792 | 0 | 40027 | 16 | 16 | 0 | 0 | 25 | 163057 | 100 | 83969 | 80000 | 100 | 80000 | 80000 | 511 | 1921720 | 648581 | 0 | 40021 | 40049 | 40450 | 20110 | 0 | 9 | 20006 | 160100 | 200 | 80120 | 80120 | 200 | 160240 | 240360 | 40049 | 40246 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 80000 | 2 | 34 | 196 | 0 | 80002 | 0 | 0 | 80122 | 0 | 34 | 4 | 5110 | 0 | 1 | 16 | 2 | 1 | 40229 | 0 | 80000 | 80000 | 100 | 41699 | 41648 | 41450 | 40845 | 40250 |
160204 | 40246 | 310 | 0 | 1 | 1 | 2 | 1 | 0 | 179 | 0 | 0 | 2290 | 0 | 40234 | 16 | 16 | 0 | 0 | 46 | 162086 | 100 | 81116 | 80060 | 100 | 80116 | 80000 | 500 | 1839808 | 643405 | 0 | 40208 | 40242 | 40043 | 20107 | 0 | 3 | 20483 | 160324 | 200 | 80120 | 80000 | 202 | 160238 | 240000 | 40445 | 40043 | 2 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 80067 | 7 | 34 | 89 | 0 | 80120 | 0 | 8 | 80122 | 2 | 0 | 2 | 5127 | 0 | 1 | 25 | 3 | 1 | 40040 | 0 | 80000 | 80000 | 100 | 40452 | 40054 | 40254 | 40049 | 40044 |
160204 | 40243 | 312 | 0 | 0 | 0 | 0 | 1 | 0 | 6 | 0 | 0 | 3314 | 0 | 40238 | 0 | 16 | 270 | 0 | 46 | 163800 | 100 | 83032 | 80120 | 100 | 80116 | 80000 | 500 | 1849708 | 651437 | 0 | 40021 | 40453 | 40043 | 20110 | 0 | 11 | 20001 | 160324 | 200 | 80000 | 80119 | 200 | 160000 | 240360 | 40042 | 40450 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 80000 | 0 | 34 | 194 | 0 | 80002 | 0 | 2 | 80000 | 2 | 0 | 0 | 5110 | 0 | 1 | 16 | 1 | 1 | 40039 | 0 | 80000 | 80000 | 100 | 40043 | 40043 | 40049 | 40044 | 40043 |
160204 | 40043 | 311 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | 0 | 2933 | 0 | 40033 | 16 | 16 | 0 | 0 | 25 | 162913 | 100 | 81130 | 80000 | 100 | 80000 | 80000 | 500 | 1839712 | 645758 | 0 | 40024 | 40043 | 40049 | 19959 | 0 | 3 | 20000 | 160100 | 200 | 80000 | 80000 | 200 | 160000 | 240000 | 40043 | 40048 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 80000 | 0 | 34 | 0 | 0 | 80002 | 0 | 3 | 80002 | 2 | 34 | 0 | 5110 | 0 | 1 | 16 | 1 | 1 | 40046 | 0 | 80000 | 80000 | 100 | 40043 | 40044 | 40043 | 40044 | 40043 |
160204 | 40043 | 311 | 0 | 0 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 1069 | 0 | 40027 | 16 | 16 | 0 | 0 | 25 | 160955 | 100 | 81476 | 80000 | 100 | 80000 | 80000 | 500 | 1839712 | 644174 | 0 | 40021 | 40042 | 40043 | 19959 | 0 | 3 | 20001 | 160100 | 200 | 80000 | 80000 | 200 | 160000 | 240000 | 40042 | 40049 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 80000 | 0 | 34 | 0 | 0 | 80002 | 0 | 2 | 80002 | 2 | 34 | 0 | 5110 | 0 | 1 | 16 | 1 | 1 | 40039 | 0 | 80000 | 80000 | 100 | 40049 | 40050 | 40050 | 40050 | 40044 |
160204 | 40042 | 311 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 42172 | 0 | 40028 | 16 | 16 | 0 | 0 | 25 | 161253 | 100 | 82451 | 80000 | 100 | 80000 | 80000 | 500 | 1839712 | 644983 | 0 | 40023 | 40043 | 40049 | 19962 | 0 | 3 | 20000 | 160100 | 200 | 80000 | 80000 | 200 | 160000 | 240000 | 40043 | 40048 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 80000 | 0 | 34 | 0 | 0 | 80002 | 0 | 2 | 80002 | 0 | 0 | 0 | 5110 | 0 | 1 | 16 | 1 | 1 | 40040 | 0 | 80000 | 80000 | 100 | 40043 | 40044 | 40060 | 40044 | 40044 |
Result (median cycles for code divided by count): 0.5007
retire uop (01) | cycle (02) | 03 | l1d tlb fill (05) | mmu table walk data (08) | l2 tlb miss data (0b) | 18 | 19 | 1e | 1f | 22 | 37 | 3a | 3f | 46 | 49 | 4f | 51 | schedule uop (52) | schedule int uop (53) | schedule simd uop (54) | schedule ldst uop (55) | dispatch int uop (56) | dispatch simd uop (57) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | ldst uops in schedulers (5b) | 60 | 69 | 6d | 6e | map stall dispatch (70) | rob full (74) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map simd uop (7e) | map int uop inputs (7f) | map ldst uop inputs (80) | map simd uop inputs (81) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int alu (97) | inst simd store (99) | inst ldst (9b) | 9f | l1d tlb access (a0) | l1d tlb miss (a1) | l1d cache miss st (a2) | a4 | ld unit uop (a6) | st unit uop (a7) | l1d cache writeback (a8) | a9 | ac | af | bc | l1d cache miss st nonspec (c0) | l1d tlb miss nonspec (c1) | c2 | branch cond mispred nonspec (c5) | cf | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ? ldst retires (ed) | ? simd retires (ee) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
160026 | 40055 | 311 | 1 | 0 | 0 | 0 | 0 | 30 | 18 | 0 | 2420 | 1 | 40037 | 16 | 16 | 0 | 25 | 160057 | 10 | 81835 | 80000 | 10 | 80000 | 80000 | 50 | 1839712 | 640108 | 0 | 40025 | 40054 | 40052 | 19987 | 0 | 3 | 20034 | 160010 | 20 | 80000 | 80000 | 20 | 160000 | 240000 | 40051 | 40054 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 80016 | 14 | 44 | 0 | 0 | 80016 | 0 | 1 | 19 | 80002 | 14 | 44 | 14 | 1 | 0 | 5020 | 1 | 16 | 1 | 1 | 40051 | 80000 | 80000 | 10 | 40052 | 40053 | 40053 | 40054 | 40052 |
160024 | 40054 | 311 | 1 | 0 | 1 | 0 | 0 | 60 | 22 | 0 | 2070 | 1 | 40038 | 16 | 0 | 0 | 25 | 160068 | 10 | 83407 | 80000 | 10 | 80000 | 80000 | 50 | 1840072 | 649780 | 0 | 40028 | 40054 | 40054 | 19982 | 0 | 3 | 20023 | 160010 | 20 | 80000 | 80000 | 20 | 160000 | 240000 | 40053 | 40054 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 80014 | 14 | 44 | 0 | 1 | 80016 | 0 | 2 | 21 | 80002 | 16 | 0 | 14 | 0 | 0 | 5020 | 1 | 16 | 1 | 1 | 40049 | 80000 | 80000 | 10 | 40051 | 40055 | 40054 | 40055 | 40051 |
160024 | 40051 | 311 | 1 | 0 | 0 | 0 | 0 | 63 | 21 | 0 | 2246 | 1 | 40037 | 16 | 16 | 1 | 25 | 160093 | 10 | 83259 | 80000 | 10 | 80000 | 80000 | 50 | 1840048 | 652141 | 0 | 40029 | 40054 | 40054 | 19988 | 0 | 3 | 20034 | 160010 | 20 | 80000 | 80000 | 20 | 160000 | 240000 | 40055 | 40053 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 80014 | 14 | 44 | 0 | 0 | 80016 | 0 | 1 | 21 | 80002 | 16 | 44 | 14 | 0 | 0 | 5020 | 1 | 16 | 1 | 1 | 40050 | 80000 | 80000 | 10 | 40063 | 40064 | 40063 | 40052 | 40055 |
160024 | 40052 | 311 | 1 | 1 | 1 | 0 | 0 | 48 | 22 | 0 | 2868 | 1 | 40038 | 16 | 16 | 1 | 25 | 161089 | 10 | 81017 | 80000 | 10 | 80000 | 80000 | 50 | 1840024 | 650032 | 0 | 40029 | 40054 | 40053 | 19990 | 0 | 3 | 20034 | 160010 | 20 | 80000 | 80000 | 20 | 160000 | 240000 | 40052 | 40054 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 80014 | 14 | 44 | 0 | 1 | 80016 | 0 | 0 | 16 | 80002 | 16 | 44 | 14 | 0 | 0 | 5020 | 1 | 16 | 1 | 1 | 40051 | 80000 | 80000 | 10 | 40049 | 40053 | 40196 | 40053 | 40063 |
160024 | 40054 | 310 | 1 | 1 | 0 | 0 | 0 | 54 | 19 | 0 | 46 | 1 | 40047 | 15 | 16 | 1 | 25 | 160041 | 10 | 80033 | 80000 | 10 | 80000 | 80000 | 50 | 1840504 | 646230 | 0 | 40026 | 40064 | 40055 | 19990 | 0 | 3 | 20042 | 160010 | 20 | 80000 | 80000 | 20 | 160000 | 240000 | 40052 | 40062 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 80014 | 15 | 50 | 0 | 1 | 80016 | 0 | 0 | 17 | 80002 | 16 | 44 | 14 | 0 | 0 | 5020 | 1 | 16 | 2 | 1 | 40051 | 80000 | 80000 | 10 | 40052 | 40052 | 40052 | 40053 | 40063 |
160024 | 40054 | 310 | 1 | 0 | 1 | 0 | 0 | 417 | 20 | 0 | 3796 | 1 | 40036 | 0 | 16 | 1 | 25 | 161439 | 10 | 80055 | 80000 | 10 | 80000 | 80000 | 50 | 1840072 | 647124 | 0 | 40028 | 40054 | 40054 | 19986 | 0 | 3 | 20034 | 160010 | 20 | 80000 | 80000 | 20 | 160000 | 240000 | 40052 | 40054 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 80016 | 15 | 44 | 0 | 0 | 80016 | 0 | 0 | 16 | 80002 | 16 | 44 | 14 | 0 | 0 | 5020 | 1 | 16 | 1 | 1 | 40048 | 80000 | 80000 | 10 | 40056 | 40056 | 40056 | 40055 | 40055 |
160024 | 40055 | 311 | 1 | 1 | 1 | 0 | 0 | 18 | 17 | 0 | 3782 | 1 | 40039 | 16 | 0 | 1 | 25 | 160642 | 10 | 81329 | 80000 | 10 | 80000 | 80000 | 50 | 1840120 | 650106 | 0 | 40030 | 40053 | 40055 | 19990 | 0 | 3 | 20034 | 160010 | 20 | 80000 | 80000 | 20 | 160000 | 240000 | 40051 | 40053 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 80015 | 14 | 44 | 0 | 1 | 80016 | 0 | 1 | 17 | 80002 | 16 | 44 | 14 | 0 | 0 | 5020 | 1 | 16 | 1 | 1 | 40049 | 80000 | 80000 | 10 | 40056 | 40055 | 40055 | 40055 | 40055 |
160024 | 40051 | 310 | 1 | 1 | 0 | 0 | 0 | 255 | 18 | 0 | 2117 | 0 | 40036 | 0 | 16 | 1 | 25 | 161477 | 10 | 83020 | 80000 | 10 | 80000 | 80000 | 50 | 1840072 | 642936 | 0 | 40037 | 40051 | 40053 | 19986 | 0 | 3 | 20042 | 160010 | 20 | 80000 | 80000 | 20 | 160000 | 240000 | 40053 | 40051 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 80014 | 14 | 50 | 0 | 0 | 80016 | 0 | 1 | 18 | 80002 | 16 | 44 | 14 | 0 | 0 | 5020 | 1 | 16 | 1 | 1 | 40059 | 80000 | 80000 | 10 | 40054 | 40055 | 40055 | 40055 | 40053 |
160024 | 40053 | 310 | 1 | 1 | 0 | 0 | 0 | 453 | 17 | 0 | 3390 | 1 | 40038 | 16 | 16 | 1 | 25 | 162902 | 10 | 80593 | 80000 | 10 | 80000 | 80000 | 50 | 1840024 | 649801 | 0 | 40029 | 40054 | 40053 | 19988 | 0 | 3 | 20034 | 160010 | 20 | 80000 | 80000 | 20 | 160000 | 240000 | 40053 | 40054 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 80015 | 14 | 44 | 0 | 0 | 80016 | 0 | 0 | 18 | 80002 | 16 | 44 | 14 | 0 | 0 | 5020 | 1 | 16 | 1 | 1 | 40049 | 80000 | 80000 | 10 | 40055 | 40055 | 40055 | 40055 | 40054 |
160024 | 40053 | 310 | 1 | 1 | 1 | 0 | 0 | 342 | 18 | 1 | 2816 | 1 | 40037 | 16 | 16 | 2 | 25 | 163824 | 10 | 83606 | 80000 | 10 | 80000 | 80000 | 50 | 1839856 | 648220 | 0 | 40028 | 40042 | 40052 | 19987 | 0 | 3 | 20033 | 160010 | 20 | 80000 | 80000 | 20 | 160000 | 240000 | 40054 | 40054 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 80014 | 15 | 44 | 0 | 0 | 80014 | 0 | 2 | 20 | 80002 | 14 | 44 | 14 | 0 | 0 | 5020 | 1 | 16 | 1 | 1 | 40050 | 80000 | 80000 | 10 | 40055 | 40054 | 40064 | 40063 | 40055 |