Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

ST3 (single, post-index, B)

Test 1: uops

Code:

  st3 { v0.b, v1.b, v2.b }[1], [x6], x8
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop
  mov x0, 0
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 2.000

Issues: 3.000

Integer unit issues: 1.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)03l1i tlb fill (04)l1d tlb fill (05)mmu table walk instruction (07)mmu table walk data (08)09l2 tlb miss instruction (0a)l2 tlb miss data (0b)18191e1f2223243a3f464951schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)5e5f696d6emap rewind (75)map stall (76)dispatch uop (78)map ldst uop (7d)map simd uop (7e)map ldst uop inputs (80)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd store (99)inst ldst (9b)l1d tlb access (a0)l1d tlb miss (a1)l1d cache miss st (a2)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acafbcl1d cache miss st nonspec (c0)l1d tlb miss nonspec (c1)c2c9cfd0d2l1i cache miss demand (d3)l1i tlb miss demand (d4)d5map dispatch bubble (d6)d9dadbddfetch restart (de)e0? int output thing (e9)eaebec? ldst retires (ed)? simd retires (ee)? int retires (ef)f5f6f7f8fd
620062891423411281022100321004689287360018112300010001000100010001000100050001090680000202172728619289153103000100010003000300028838288861161001100010001002220100101110001211013130957669413189105920266332538092556522832510001566112546140411000100010002891628866289162894228844
620042873923201211021100021004719287460017901300010001000100010001000100150001090280000202169828468288677103000100010003000300028756288011161001100010001002121100100110001011013396941668873136115920261317638052560552833910001577212777138481000100010002898328858288022894928870
62004288632320120102910013511004599288390017721300010001000100010001000100050001090880000192168228705288773103000100010003000300028953289581161001100010001002220100111110001010013158949068583126115520253324738171551572837910001557812692139861000100010002898428921290392900828978
6200428851233011700241001220004710287460017844300010001000100010001000100050001090980000122172428763289423103000100010003000300328832288191161001100010001002301100100110001211013233959468793162195320241330538171955552837810001570412802140691000100010002899929011289462896428965
62004289362320121101810048901004585287150018027300310001000100010001000100050001090580000112176428745288923103000100010003000300028967288612161001100010001002200100213410001211013312947969003178145420381324538181856532844910001565612853138741000100010002904128927289182895228820
62004289272330114102110001100474028854001798030001000100010001000100010005000108988000072170128747289573103000100010003000300028860287841161001100010001004321100121110001011013307943268553078136020327320538291752542834910001576812926141051000100010002897528968289112884728913
620042887823201151022100121100473228690001801230001000100010001000100010005000109038000010217032856929023610300010001000300030002886128871116100110001000100330110011011000101101316593386928317095420236322138221954562834710001563412878139131000100010002896528997289522890728981
62004288962330117102100012210047892880900178843000100010001000100110001000500010905800001121689287442907631030001000100030003000289502883311610011000100010012201001004211000121301333094266940313995420337339538231850502844110001563612796138371000100010002887829008290382901228826
62004290502330116102100002100464328790001800230001000100010001000100010015000109108000072171028750291383103000100010003000300028961289021161001100010001002221100101410001213013149936368583115115520434327838242252542852910011588812852139591000100010002909629000290982916029199
62004290432330116101710015100046762889701182013000100010001000100010001000500010904800006217642875629118310300010001000300030002898729121116100110001000100332110010111000101101321694326969310595020421327538252255532858410001575613013141601000100010002910529006290282910429024

Test 2: throughput

Count: 8

Code:

  st3 { v0.b, v1.b, v2.b }[1], [x6], x8
  st3 { v0.b, v1.b, v2.b }[1], [x6], x8
  st3 { v0.b, v1.b, v2.b }[1], [x6], x8
  st3 { v0.b, v1.b, v2.b }[1], [x6], x8
  st3 { v0.b, v1.b, v2.b }[1], [x6], x8
  st3 { v0.b, v1.b, v2.b }[1], [x6], x8
  st3 { v0.b, v1.b, v2.b }[1], [x6], x8
  st3 { v0.b, v1.b, v2.b }[1], [x6], x8
  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0005

retire uop (01)cycle (02)03l1d tlb fill (05)mmu table walk data (08)09l2 tlb miss data (0b)18191e1f2223373a3f46494f5051schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd store (99)inst ldst (9b)9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache miss st (a2)a4ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acafbcl1d cache miss st nonspec (c0)l1d tlb miss nonspec (c1)c2branch mispred nonspec (cb)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1602068004062111100009104237180025992025242638801008214880000801008000080000435899037588486528071800158004080040599243599982401002008000080000200240360240000800408004011802011009910010080000800001008000772901800080088000182972051101161180037800008000080000801008004180041800418004180041
160204800406201000100900254018002599202524224480100821828000080100800008000043589903758848640435180015800408004059924359998240100200800008000020024000024000080040800401180201100991001008000080000100800088290280008008800008070051101161280037800008000080000801008016280041800418004180041
160204800406201010001270021111800259950252402248010082137800008010080000801084358990375884864050708001580040800405998635999824010020080000800002002400002400008004080040118020110099100100800008000010080007829008000800118000182970051101161180037800008000080000801008004180041800418004180041
16020480040621110000127001587180025992025242327801008202380000801008000080216435899037588487607781811628004080040599243599982401002008000080000200240000240360800408004011802011009910010080000800001008000772901800081088000192971051101161180037800008000080000801008004180041800418004180041
16020480040620101110090020718002598202524349580100801018000080100800008000043589943758848640233180015800408004059924359998240100200800008000020024000024000080040800401180201100991001008000080000100800077001800081188000182971051101164280037800008000080000801008004180041800418004180163
160204800406211100000700422718002599102524024780100801598000080100800008000043589903758848640380180015800408004059924359998240100200800008000020024036024000080040800401180201100991001008000080000100800077000800080088000172971051101161180037800008000080000801008004180041800418004180041
160204801626211011000900156180025891053240284801008169680000801008000080000435899037588486553690800158004080040599243599982401002008000080000200240000240000800408004021802011009910010080000800001008000782902800080088000172970051101161180037800008000080000801008004180041800418004180041
1602048004062010000012120028811800250920252436218010082769800008010080000800004359002375884864059318011980040800405992435999824010020080000800002002400002400008004080040118020110099100100800008000010080007729008000800118000182971051101161180037800008000080000801008004180041800418004180041
16020480040621110000090034521800259920252402448010080159800008010080000800004358990375884864059918001580040800405992413599982401002008000080000200240000240000800408004011802011009910010080000800001008000782901800081088000182971051101251180037800008000080000801008004180041800418004180041
16020480040620111000159001399180025090025244337801908202280000801008000080000435899837588486526431800158004080040599243599982401002008000080000200240000240000800408004021802011009910010080000800001008000773000800080078000082970051101161180037800008000080000801008004180041800418004180041

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0005

retire uop (01)cycle (02)03mmu table walk data (08)09l2 tlb miss instruction (0a)l2 tlb miss data (0b)0e18191e1f222324373f46494f51schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd store (99)inst ldst (9b)9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache miss st (a2)a4ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acafbcl1d cache miss st nonspec (c0)c2branch cond mispred nonspec (c5)cfd0d5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)f5f6f7f8fd
160026800406210000000041004697800258032524002380010800138000080010800008000043584293758848656892080118800408004059946360020240010208000080000202400002400008004080040118002110910108000080000108000002100800000008000112100502001161180037800008000080000800108004180041800418004180041
16002480040620000000004100697800258802524470480010846978000080010800008000043584293758848640054080015800408004059946360020240010208000080000202400002400008004080040118002110910108000080000108000002100800010038000112100502001161180037800008000080000800108004180041800418004180041
160024800406200000000021003755800258802524002580010846948000080010800008000043584293758848651271080015800408004059946360020240010208000080000202400002400008004080040118002110910108000080000108000002100800010038000112100502001161180037800008000080000800108004180041800418004180041
16002480040620000000004100695800258832524070480010800128000080010800008000043584293758848640054080015800408004059946360020240010208000080000202400002400008004080040118002110910108000080000108000002100800010018000112100502001161180037800008000080000800108004180041800418004180041
160024800406200000000021004694800258032524470480010813828000080010800008000043584293758848656901080015800408004059946360020240010208000080000202400002400008004080040118002110910108000080000108000002100800001038000112100502001161180037800008000080000800108004180041800418004180041
1600248004062100000001201001580025883252447048001084693800008001080000800004358429375884864003508001580040800405994636002024001020800008000020240000240000800408004011800211091010800008000010800000000800010008000112100502001161180037800008000080000800108004180146800418004180041
1600248004062000000001240011947800258802524002080010846958000080010800008000043584293758848644140080015800408004059946360020240010208000080000202400002400008004080040118002110910108000080000108000002100800000068000112100502001161180037800008000080000800108004180041800418004180041
1600248004062000000001240001580025880252447038001085631800008001080000800004358429376294064004808001580040800405994636002024001020800008000020240000240000800408004011800211091010800008000010800000210080001003800011000502001161180037800008000080000800108004180041800418004180041
160024800406210000000020014694800258812524002480010846948000080010800008000043584293758848654084080015800408004059946360020240010208000080000202400002400008004080040118002110910108000080000108000002100800010038000112100502001161180037800008000080000800108004180041800418004180041
1600248004062100000000400014800258032524470980010846978000080010800008000043584293758848640037080015800408004059946360020240010208000080000202400002400008004080040118002110910108000080000108000002100800011018000112200502001161180037800008000080000800108004180041800418004180041