Firestorm: ST4 (multiple, 16B) measurements

Code:

  st4 { v0.16b, v1.16b, v2.16b, v3.16b }, [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 12.000

Issues: 12.000

Integer unit issues: 0.000

Load/store unit issues: 4.000

SIMD/FP unit issues: 8.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	1f	22	23	24	37	3a	3f	46	49	51	schedule uop (52)	schedule simd uop (54)	schedule ldst uop (55)	dispatch simd uop (57)	dispatch ldst uop (58)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	5f	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd store (99)	inst ldst (9b)	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	c2	c9	cf	d0	d2	l1i cache miss demand (d3)	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	f5	f6	f7	f8	fd
72007	29446	237	0	39	0	1	29	1	0	0	0	1	0	0	0	0	4608	29382	3	3	15006	12000	8000	4000	8000	4000	51901	71629	14	24692	29156	29392	3	10	12000	4000	8000	8000	20000	29303	29389	1	1	61001	1000	1000	4000	0	12	0	4006	1	0	1	4001	0	12	0	126	13087	9320	6893	3164	14	59	19442	3210	3805	20	64	52	28687	16276	12887	12970	4000	8000	29333	29415	29494	29379	29397
72004	29507	237	0	27	0	0	26	0	0	0	0	2	0	0	0	0	4612	29369	3	3	15145	12000	8000	4000	8000	4000	51908	71614	1	24668	29160	29475	3	10	12000	4000	8000	8000	20000	29390	29297	1	1	61001	1000	1000	4000	0	12	0	4000	0	0	1	4001	4	12	0	0	13234	9414	6878	3218	15	62	19368	3388	3807	8	57	58	28645	16086	12974	12754	4000	8000	29247	29470	29286	29362	29427
72004	29479	236	1	26	0	0	24	0	0	0	0	2	0	0	0	0	4668	29384	3	3	15216	12000	8000	4000	8000	4000	51898	71612	5	24727	29155	29225	3	10	12000	4000	8000	8000	20000	29405	29355	1	1	61001	1000	1000	4000	5	0	0	4001	0	0	163	4001	1	12	0	0	13201	9564	6944	3092	17	63	19427	3280	3803	12	63	62	28727	16174	12814	12858	4000	8000	29435	29368	29465	29382	29472
72004	29721	237	0	21	0	0	22	1	0	0	18	2	0	0	0	0	4580	29290	4	0	15158	12000	8000	4000	8000	4000	51910	71612	4	24739	29352	29464	3	10	12000	4000	8000	8000	20000	29374	29412	1	1	61001	1000	1000	4000	0	12	0	4001	0	0	1	4000	1	12	0	0	13065	9231	6875	3093	18	64	19373	3216	3801	13	59	57	28631	15980	12903	12770	4000	8000	29441	29429	29371	29399	29416
72004	29479	236	0	29	0	0	22	1	0	0	0	2	0	0	0	0	4642	29418	0	3	15264	12000	8000	4000	8000	4000	51906	71588	13	24750	29201	29352	3	10	12000	4000	8000	8000	20000	29347	29373	1	1	61001	1000	1000	4000	0	12	0	4006	0	0	0	4001	1	12	0	0	12973	9537	6863	3156	17	59	19376	3287	3804	11	63	61	28714	16214	12877	12830	4000	8000	29474	29468	29337	29402	29600
72004	29486	236	0	20	0	0	19	0	0	0	0	1	0	0	0	0	4702	29438	3	4	15130	12000	8000	4000	8000	4000	51899	71637	8	24751	29295	29473	3	10	12000	4000	8000	8000	20000	29429	29495	1	1	61001	1000	1000	4000	0	12	0	4000	0	0	0	4000	4	0	0	0	13098	9471	6891	3122	15	69	19375	3301	3813	9	59	62	28644	16169	13045	13067	4000	8000	29433	29455	29405	29425	29519
72004	29417	236	1	25	0	0	25	0	0	0	12	1	0	0	0	0	4754	29335	4	4	15260	12000	8000	4000	8000	4000	51897	71618	7	24737	29311	29365	3	10	12000	4000	8000	8000	20000	29354	29367	1	1	61001	1000	1000	4000	5	12	0	4000	0	0	0	4000	0	12	0	0	13080	9365	6905	3134	12	61	19344	3332	3813	15	57	65	28703	16273	12769	12747	4000	8000	29504	29438	29471	29407	29439
72004	29401	236	0	21	0	0	23	0	0	0	0	1	0	0	0	1	4674	29282	4	4	15190	12000	8000	4000	8000	4000	51901	71627	7	24656	29208	29435	3	10	12000	4000	8000	8000	20000	29271	29399	1	1	61001	1000	1000	4000	0	12	0	4000	0	0	204	4000	0	0	1	0	13087	9298	6895	3186	13	59	19372	3294	3805	12	56	59	28587	16050	12944	12956	4000	8000	29374	29482	29376	29429	29362
72004	29426	237	0	22	0	0	27	1	0	0	0	0	0	1	0	0	4614	29315	0	3	15090	12000	8002	4000	8000	4000	51928	71616	10	24684	29291	29388	3	10	12000	4000	8000	8000	20000	29336	29409	1	1	61001	1000	1000	4000	0	12	0	4004	0	0	2	4000	1	12	0	0	13045	9360	6896	3158	13	56	19409	3336	3810	18	61	63	28856	16342	12839	12901	4000	8000	29411	29439	29335	29490	29361
72004	29448	237	0	24	1	0	31	0	0	0	0	2	0	0	0	1	4643	29352	4	4	15256	12000	8001	4000	8000	4000	51896	71599	5	24676	29253	29239	3	10	12000	4000	8000	8000	20000	29495	29397	1	1	61001	1000	1000	4000	0	12	0	4000	0	0	3	4001	4	12	0	0	13171	9424	6913	3182	10	52	19338	3367	3810	12	52	58	28778	16268	12874	12803	4000	8000	29438	29365	29468	29405	29451

Count: 8

Code:

  st4 { v0.16b, v1.16b, v2.16b, v3.16b }, [x6]
  st4 { v0.16b, v1.16b, v2.16b, v3.16b }, [x6]
  st4 { v0.16b, v1.16b, v2.16b, v3.16b }, [x6]
  st4 { v0.16b, v1.16b, v2.16b, v3.16b }, [x6]
  st4 { v0.16b, v1.16b, v2.16b, v3.16b }, [x6]
  st4 { v0.16b, v1.16b, v2.16b, v3.16b }, [x6]
  st4 { v0.16b, v1.16b, v2.16b, v3.16b }, [x6]
  st4 { v0.16b, v1.16b, v2.16b, v3.16b }, [x6]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 2.4966

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	1f	22	24	37	3a	3f	46	49	4e	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd store (99)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ab	ac	af	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d0	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
960207	200613	1558	1	0	1	0	0	0	0	9	19	0	0	84759	2	200089	16	16	1091	15919	25	1053100	100	732428	320000	100	640238	320000	500	9245261	10812573	0	199999	199947	201809	37152	3	38930	960100	200	320000	640000	200	640000	1600600	200889	201703	1	1	80201	100	99	100	100	80000	80000	100	320074	15	36	24834	0	320014	0	1	0	14	320002	14	36	14	0	0	0	0	5109	0	0	1	17	2	2	199720	0	320000	640000	100	197087	201557	198024	200400	201424
960204	199726	1559	0	1	0	1	0	0	0	0	90	0	0	82757	1	201035	16	16	1462	15750	25	1043545	100	729815	320000	100	640000	320000	500	9194485	10811253	0	199096	199170	198076	38375	3	40138	960100	200	320000	640000	200	640000	1600000	200683	199199	1	1	80201	100	99	100	100	80000	80000	100	320000	0	34	25225	0	320002	0	0	0	14	320062	2	34	0	0	0	0	0	5109	0	0	1	17	1	2	199611	0	320000	640000	100	200913	200867	200919	200571	201679
960204	197501	1556	0	1	0	1	0	0	0	0	2	0	0	88814	0	202051	16	0	1667	16259	25	1041327	100	725854	320060	100	640000	320000	500	9268396	10751731	0	200175	199820	197629	40620	3	41032	960100	200	320000	640240	200	640000	1600000	198995	197080	1	1	80201	100	99	100	100	80000	80000	100	320000	0	34	25650	0	320062	0	0	0	2	320000	2	34	0	0	0	0	0	5111	0	0	1	17	2	2	199116	0	320000	640000	100	202464	199190	200830	197839	199729
960204	200088	1551	0	1	0	1	0	0	1	12	5	0	0	87269	1	198417	16	16	1545	17798	25	1049601	100	721088	320000	100	640000	320000	500	9317027	10759707	0	200998	200310	200197	39483	3	39884	960100	200	320000	640000	200	640000	1600000	200389	199785	1	1	80201	100	99	100	100	80000	80000	100	320000	0	34	24995	0	320002	0	0	0	2	320002	2	34	0	0	0	0	0	5111	0	0	2	17	1	2	201580	0	320000	640000	100	199427	200463	200157	202175	200544
960204	203112	1560	0	0	0	0	0	0	0	0	5	0	0	88524	1	201464	16	0	1610	15540	25	1051376	100	724807	320000	100	640000	320000	500	9330188	10818733	1	199971	198344	199808	38538	3	39303	960100	200	320000	640000	200	640000	1600600	201374	200579	1	1	80201	100	99	100	100	80000	80000	100	320060	0	34	25525	0	320002	0	0	0	2	320004	2	34	0	0	0	0	0	5112	0	0	1	17	3	1	199977	0	320000	640000	100	200831	199219	199555	197062	200598
960204	200177	1567	0	1	0	0	0	0	0	12	0	0	0	79868	0	201759	16	0	1461	17038	25	1042513	100	724358	320000	100	640000	320000	500	9272306	10760333	0	200291	198488	201073	42173	3	39791	960446	200	320000	640000	200	640000	1600000	201771	200515	1	1	80201	100	99	100	100	80000	80000	100	320060	0	40	25671	0	320002	1	0	0	17	320002	0	34	0	0	0	0	0	5111	0	0	2	17	2	1	200024	1	320000	640000	100	201201	201693	199689	202123	200009
960204	200673	1569	0	1	1	0	1	5	2	534	440	0	0	87222	0	198677	16	16	1417	18044	131	1043731	100	719593	320180	100	640952	320432	500	9256901	10758597	0	201864	199452	202184	40958	29	40194	960100	200	320000	640000	200	640000	1600000	200574	199477	1	1	80201	100	99	100	100	80000	80000	100	320000	0	34	26643	0	320002	0	0	0	0	320002	2	34	0	0	0	0	0	5109	0	0	1	17	1	2	201502	0	320000	640000	100	199591	197457	201227	199770	201898
960204	200324	1544	0	1	0	1	0	0	0	9	5	0	0	88425	1	197983	16	0	1739	16240	25	1046977	100	726556	320000	100	640000	320000	500	9279957	10777103	0	201101	200204	199688	38616	3	41948	960100	200	320000	640000	200	640000	1600000	198876	200599	1	1	80201	100	99	100	100	80000	80000	100	320000	0	0	25063	0	320002	1	0	0	2	320002	2	34	0	0	0	0	0	5109	0	0	2	17	2	2	198788	0	320000	640000	100	200937	197703	197653	200267	200751
960204	201050	1541	0	1	0	1	0	0	0	6	8	0	0	82952	1	201475	16	0	1342	16686	25	1046571	100	722710	320000	100	640000	320000	500	9280529	10814630	0	199982	197129	199670	43772	3	38014	960100	200	320000	640000	200	640000	1600000	201108	197952	1	1	80201	100	99	100	100	80000	80000	100	320000	0	34	25257	0	320002	0	0	0	2	320000	2	34	0	0	0	0	0	5111	0	0	1	17	2	1	200174	0	320000	640000	100	199017	198434	201703	199961	199656
960204	201955	1556	0	0	0	0	0	0	0	12	2	0	0	86892	0	201352	16	16	1391	16240	25	1042711	100	716210	320000	100	640000	320000	500	9329395	10788552	0	200600	200779	201431	38314	3	40078	960100	200	320000	640000	200	640000	1600000	200139	198456	1	1	80201	100	99	100	100	80000	80000	100	320000	0	0	26598	0	320000	1	0	0	2	320002	2	0	0	0	0	0	0	5109	0	0	1	17	2	2	199660	0	320000	640000	100	200586	199344	200423	201146	201068

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 2.4960

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0f	18	19	1e	1f	22	24	37	3f	46	49	4e	4f	50	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd store (99)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	ac	af	bc	l1d cache miss st nonspec (c0)	branch cond mispred nonspec (c5)	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
960027	201434	1550	0	0	0	0	0	0	0	12	2	1	0	86792	200808	16	16	1488	16200	0	25	1043502	10	731295	320000	10	640000	320000	50	9322769	10702802	0	200958	0	200655	200196	39577	3	41855	960010	20	320000	640000	20	640000	1600000	200808	199114	2	1	80021	10	9	10	10	80000	80000	10	320000	0	0	26944	0	320002	1	856	320002	0	34	0	5019	6	12	17	7	12	200282	320000	640000	10	201313	201182	203633	200700	202156
960024	200975	1551	0	0	0	0	0	0	0	132	2	0	0	86989	199465	16	16	1593	17957	0	25	1050424	10	728061	320000	10	640000	320000	50	9327361	10733601	0	199622	0	200152	198475	40292	3	39334	960010	20	320000	640000	20	640000	1600000	200752	201733	1	1	80021	10	9	10	10	80000	80000	10	320000	0	34	25038	0	320000	0	1100	320002	2	34	0	5031	3	6	44	27	27	202629	320000	640000	10	205973	205268	200571	202364	198656
960024	201897	1562	0	0	0	1	0	3	3	528	266	0	0	88755	198160	0	16	1454	17339	0	107	1045119	10	726216	320240	10	640714	320324	50	9177675	10786852	0	199509	0	201364	196962	41116	3	39414	960010	20	320000	640000	20	640000	1600000	200199	197158	1	1	80021	10	9	10	10	80000	80000	10	320000	0	34	24880	0	320002	0	2	320002	2	34	0	5019	0	12	17	5	11	199173	320000	640000	10	199187	202124	200922	197684	200497
960024	200939	1559	0	0	0	0	0	0	0	12	2	0	0	86455	198722	16	16	1558	16028	0	25	1050078	10	727848	320000	10	640000	320000	50	9253013	10736365	0	197277	0	202097	200392	38215	3	39901	960010	20	320000	640000	20	640000	1600000	201559	199981	1	1	80021	10	9	10	10	80000	80000	10	320000	0	34	24688	0	320002	0	5	320002	2	34	0	5019	13	12	17	12	7	200632	320000	640000	10	202081	200450	198648	200316	201396
960024	200162	1557	0	0	0	0	0	0	0	0	2	0	0	85249	200533	16	16	1488	16368	0	25	1042249	10	728338	320000	10	640000	320000	50	9310748	10878608	0	199328	3	197936	201413	39990	3	40970	960010	20	320000	640000	20	640000	1600000	200832	199007	1	1	80021	10	9	10	10	80000	80000	10	320000	0	34	26256	0	320000	0	5	320002	2	34	0	5019	6	7	17	12	12	201231	320000	640000	10	199192	200898	201257	199055	197473
960024	198236	1535	0	0	0	0	0	0	0	0	8	0	0	83478	199919	16	16	1472	17002	0	25	1043820	10	722506	320000	10	640000	320000	50	9302043	10798672	1	199281	0	196522	200083	40359	3	40514	960010	20	320000	640000	20	640000	1600000	200404	201439	1	1	80021	10	9	10	10	80000	80000	10	320000	0	34	26356	0	320002	0	2	320000	2	34	0	5020	3	12	17	13	14	201707	320000	640000	10	198246	197119	200237	200638	198009
960024	197531	1538	0	0	0	0	0	0	0	0	8	0	0	80593	199028	16	16	1354	16652	0	25	1048537	10	727993	320000	10	640000	320000	50	9217306	10806213	0	199491	0	201244	200129	41597	3	41010	960010	20	320000	640000	20	640000	1600000	201394	199981	1	1	80021	10	9	10	10	80000	80000	10	320000	0	34	26850	0	320000	0	2	320002	0	34	0	5019	3	12	17	5	12	200753	320000	640000	10	198152	198017	199812	200438	200814
960024	198892	1550	0	0	0	0	0	0	0	0	2	1	0	92882	198462	16	16	1539	16504	4	25	1043597	10	725963	320000	10	640000	320000	50	9280985	10814069	0	198767	0	198461	201114	39748	3	41709	960010	20	320000	640240	20	640960	1601800	199006	198045	4	1	80021	10	9	10	10	80000	80000	10	320180	2	34	24951	2	322462	0	41268	321682	2	34	0	5068	19	15	53	6	18	201628	320000	640000	10	200643	201137	200572	200491	202077
960024	199424	1553	0	0	0	0	0	0	0	0	2	0	0	86996	201662	16	16	1340	16454	0	25	1047825	10	730269	320060	10	640476	320432	50	9263984	10758736	0	198883	0	201110	198127	40101	3	41652	960010	20	320000	640000	20	640000	1600000	200427	200154	1	1	80021	10	9	10	10	80000	80000	10	320000	0	34	26572	0	320002	0	2	320002	2	34	0	5019	3	12	17	5	13	202072	320000	640000	10	200933	200837	199619	200054	201489
960024	199683	1544	0	0	0	0	0	0	0	408	176	0	0	85007	200902	16	0	1398	17584	0	25	1047922	10	729831	320000	10	640000	320000	50	9188697	10839022	0	201257	0	201041	200746	42362	3	39641	960010	20	320360	640480	20	640480	1600000	198176	198070	1	1	80021	10	9	10	10	80000	80000	10	320122	0	34	26489	2	320002	3	8	320002	2	34	0	5019	13	12	17	12	13	200620	320000	640000	10	201621	199997	198389	197954	199270

ST4 (multiple, 16B)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations