Firestorm: ST4 (multiple, 2D) measurements

Code:

  st4 { v0.2d, v1.2d, v2.2d, v3.2d }, [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 12.000

Issues: 12.000

Integer unit issues: 0.000

Load/store unit issues: 4.000

SIMD/FP unit issues: 8.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	1f	24	37	3a	3f	46	49	51	schedule uop (52)	schedule simd uop (54)	schedule ldst uop (55)	dispatch simd uop (57)	dispatch ldst uop (58)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	5f	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd store (99)	inst ldst (9b)	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	c9	cf	d0	d2	l1i cache miss demand (d3)	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	f5	f6	f7	f8	fd
72007	29145	234	1	24	2	2	26	0	2	2	396	181	0	0	4671	29045	0	3	14897	12001	8000	4004	8000	4000	51905	71605	9	24637	29219	29194	3	10	12000	4000	8000	8000	20000	29006	28980	1	1	61001	1000	1000	4005	7	0	1	4004	1	1	7	4000	4	8	4	0	3088	13287	9310	6944	3115	8	60	18986	3198	3812	19	67	59	28546	15679	12525	12833	4000	8000	28964	29010	29004	29395	29117
72004	29300	234	1	25	1	1	23	1	0	0	0	5	0	0	4777	29065	0	0	15347	12000	8000	4000	8000	4004	51893	71599	8	24681	28676	28841	3	10	12000	4029	8030	8000	20000	29273	29300	1	1	61001	1000	1000	4005	5	0	0	4004	0	2	7	4000	4	0	4	1	376	13278	9380	6808	3067	14	64	19618	3274	3813	26	68	73	28638	15985	12999	13146	4000	8000	29682	29195	29439	29240	29158
72004	29235	233	1	21	0	0	23	1	0	0	0	5	0	0	4835	28718	3	0	14740	12012	8001	4000	8008	4000	51900	71606	8	24606	29152	30137	3	10	12000	4000	8000	8000	20000	28886	29019	1	1	61001	1000	1000	4005	5	0	1	4004	1	2	4	4000	4	8	4	1	0	13210	9550	6987	3087	12	67	18746	3229	3815	26	72	69	28439	15485	12435	12516	4000	8000	29057	28914	28932	28967	28865
72004	29069	233	1	22	0	1	26	1	0	0	9	4	0	0	4753	28949	0	3	14511	12000	8000	4000	8000	4000	51897	71616	12	24706	28774	28927	3	10	12000	4000	8000	8000	20000	28793	28801	1	1	61001	1000	1000	4005	5	12	1	4004	0	1	4	4000	4	0	4	1	648	12982	9237	6875	3125	12	61	19051	3210	3812	14	76	69	28222	15246	12352	11981	4000	8000	28606	28644	28887	28916	28699
72004	28632	228	1	33	1	0	30	0	0	0	0	5	0	0	4794	29464	4	4	15130	12001	8000	4000	8000	4000	51894	71592	2	24752	29382	29740	3	10	12000	4000	8000	8000	20000	29391	29501	1	1	61001	1000	1000	4004	5	0	0	4004	1	0	4	4000	4	0	4	1	315	12370	8117	6452	2696	14	65	19477	3352	3820	14	71	63	28744	16345	12933	13237	4000	8000	29626	29592	29571	29583	29446
72004	29538	237	1	24	1	0	27	1	0	0	1794	1236	0	5	4533	30237	0	0	15524	12184	8099	4041	8108	4034	53064	72466	1	25025	29893	30189	75	338	12121	4052	8080	8122	20195	30134	30195	16	1	61001	1000	1000	4031	10	12	1	4004	0	1	4	4000	4	8	4	1	0	13151	9338	7006	3114	12	62	19476	3176	3814	14	72	63	28980	16059	12926	12954	4000	8000	29423	29458	29580	29572	29539
72004	29388	237	1	23	1	0	26	1	0	0	0	4	0	0	4664	29433	0	1	15342	12000	8000	4000	8000	4000	51904	71610	1	24759	29365	29528	3	31	12000	4000	8000	8000	20000	29433	29572	1	1	61001	1000	1000	4004	5	8	1	4005	0	1	4	4000	4	0	4	1	0	12953	9568	6872	3136	15	68	19534	3344	3817	21	70	64	29201	16344	12947	13051	4000	8000	29612	29561	29662	29746	29847
72004	29853	239	1	26	1	0	25	1	0	0	0	5	0	0	4643	29834	4	4	14660	12000	8000	4000	8000	4000	51891	71605	11	24957	29238	29027	3	10	12000	4000	8008	8008	20000	28733	28934	1	1	61001	1000	1000	4005	5	12	1	4004	0	1	4	4000	4	0	4	1	0	13089	9633	6909	3165	12	56	18785	3151	3820	18	62	63	28273	15581	12334	12403	4000	8000	28881	28831	28808	28779	28802
72004	28795	223	1	21	1	0	25	1	0	0	0	5	1	0	4613	28691	4	4	14460	12000	8000	4004	8000	4000	51895	71604	4	24675	28746	28726	3	10	12000	4000	8000	8000	20000	28839	28858	1	1	61001	1000	1000	4011	5	8	0	4004	0	1	4	4000	4	8	4	1	0	13194	9518	6987	3140	13	56	18707	3176	3818	8	61	62	28199	15835	12387	12360	4000	8000	28715	28792	28737	28884	28713
72004	28780	223	1	17	1	0	32	1	0	0	0	4	0	0	4695	28731	0	0	14497	12000	8000	4000	8000	4000	51913	71624	1	24708	28528	28842	3	10	12000	4000	8000	8000	20020	28842	28787	1	1	61001	1000	1000	4006	5	8	1	4004	0	0	4	4000	4	8	4	1	0	13161	9507	6880	3119	13	54	18793	3271	3815	14	61	65	28307	15639	12358	12531	4000	8000	28780	28800	28747	28778	28854

Count: 8

Code:

  st4 { v0.2d, v1.2d, v2.2d, v3.2d }, [x6]
  st4 { v0.2d, v1.2d, v2.2d, v3.2d }, [x6]
  st4 { v0.2d, v1.2d, v2.2d, v3.2d }, [x6]
  st4 { v0.2d, v1.2d, v2.2d, v3.2d }, [x6]
  st4 { v0.2d, v1.2d, v2.2d, v3.2d }, [x6]
  st4 { v0.2d, v1.2d, v2.2d, v3.2d }, [x6]
  st4 { v0.2d, v1.2d, v2.2d, v3.2d }, [x6]
  st4 { v0.2d, v1.2d, v2.2d, v3.2d }, [x6]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 2.4999

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	22	23	24	37	3a	3f	46	49	4e	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd store (99)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	aa	ac	af	atomic or exclusive succ (b3)	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	branch cond mispred nonspec (c5)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
960207	201957	1559	0	0	0	0	0	12	93	0	0	0	80820	0	200075	16	16	1406	17148	25	1046641	100	725985	320000	100	640714	320000	500	9274424	10826160	0	201852	199762	202292	41612	3	40731	960100	200	320000	640240	200	640000	1600000	200949	199761	1	1	80201	100	99	100	100	80000	80000	100	320434	17	0	24658	3	320496	0	0	0	8565	320002	0	16	34	14	0	0	5109	1	17	1	1	199743	0	320000	640000	100	198562	199440	199358	200101	200051
960204	199145	1534	0	0	0	0	0	0	2	0	0	0	88566	0	200795	16	16	1456	17031	25	1044656	100	725573	320000	100	640000	320000	500	9130535	10727345	0	200342	200144	198825	37438	3	41645	960100	208	320960	640000	200	640000	1600000	198330	200258	1	1	80201	100	99	100	100	80000	80000	100	320015	15	34	25847	0	320016	78	1	0	359	320062	0	16	36	14	0	0	5109	1	17	1	1	201183	0	320000	640000	100	198028	199538	199495	200727	199260
960204	200125	1545	1	1	0	0	0	12	102	0	0	0	89973	1	198645	0	16	1469	17797	25	1046973	100	729385	320000	100	640000	320000	500	9296744	10982851	0	200173	202075	201107	39942	3	38939	960100	200	320000	640000	200	640000	1600000	197375	201252	1	1	80201	100	99	100	100	80000	80000	100	320015	15	36	24082	0	320076	1	0	0	52	320002	0	2	34	0	0	0	5120	1	17	1	1	199714	0	320000	640000	100	202023	199996	199381	198912	199642
960204	200622	1553	0	0	0	0	0	21	5	0	0	0	85952	0	201532	16	16	1620	16770	25	1041199	100	727276	320000	100	640000	320000	500	9288147	10571901	0	202886	201607	200271	40510	13	39808	960100	200	320000	640000	200	640000	1600000	200682	199375	1	1	80201	100	99	100	100	80000	80000	100	320014	14	36	25315	1	320018	0	1	0	237	320000	0	2	34	0	2	0	5109	1	17	1	1	200511	0	320000	640000	100	199708	198799	198940	200458	198844
960204	200349	1598	0	0	0	0	0	12	2	0	0	0	87334	0	201082	16	16	1421	16458	25	1044270	100	726467	320000	100	640000	320000	500	9283340	10736673	0	200101	200488	197824	37714	3	43359	960100	200	320000	640000	200	640000	1600000	200871	199416	1	1	80201	100	99	100	100	80000	80000	100	320014	14	36	26187	0	320014	1	1	0	151	320002	0	16	34	14	1	0	5109	1	17	1	1	200169	0	320000	640000	100	199671	200779	199990	200502	198814
960204	198794	1603	1	0	1	1	0	0	18	0	0	0	81797	1	199489	16	0	1506	15719	25	1046525	100	732321	320000	100	640952	320000	500	9285411	10813744	0	200709	199673	201345	41236	3	40541	960100	200	320000	640000	200	640000	1600000	199650	201968	2	1	80201	100	99	100	100	80000	80000	100	320015	15	36	26130	1	320014	0	0	0	54	320002	0	0	36	0	0	0	5109	1	26	1	1	201662	0	320000	640000	100	202917	200997	201361	201815	198761
960204	197052	1605	1	0	0	0	0	9	20	0	0	0	87210	1	197005	16	16	1376	16611	25	1043886	100	729197	320000	100	640000	320108	500	9270970	10843057	0	201964	202167	199715	40625	429	42281	961484	200	320360	640960	200	640960	1601800	201437	201063	5	1	80201	100	99	100	100	80000	80000	100	320074	17	0	25606	3	320256	0	0	0	3007	320182	0	2	34	0	0	0	5154	2	44	1	2	199939	0	320000	640000	100	200349	198343	198191	201108	199634
960204	199089	1609	0	0	0	0	0	0	2	0	0	0	81555	0	199262	16	16	1638	16972	25	1045455	100	730589	320000	100	640000	320000	500	9271225	10728502	0	200001	201596	201417	40575	3	39937	960792	200	320000	640000	200	640000	1600000	201033	201186	1	1	80201	100	99	100	100	80000	80000	100	320014	15	36	26772	0	320016	0	0	0	40	320002	0	2	34	0	0	1	5109	1	17	1	1	198992	0	320000	640000	100	199083	200734	199934	197557	201082
960204	198996	1615	0	0	0	0	0	12	8	0	0	0	81563	0	199389	16	16	1674	17024	25	1047901	100	726141	320000	102	640000	320000	500	9187320	10811798	0	200657	199652	199984	40715	3	39835	960100	200	320000	640000	200	640000	1600000	200035	199248	1	1	80201	100	99	100	100	80000	80000	100	320015	15	36	26460	0	320016	0	0	0	125	320002	0	2	34	0	0	0	5110	1	17	2	1	197919	0	320000	640000	100	200687	199482	198485	201291	200191
960204	200273	1626	1	1	1	0	0	0	17	0	0	0	93960	1	199084	16	0	1361	16847	25	1046048	100	722774	320000	100	640000	320000	500	9412037	10786648	0	201486	201932	202046	41566	3	40143	960100	200	320000	640000	200	640000	1600000	200210	198628	1	1	80201	100	99	100	100	80000	80000	100	320016	14	36	25557	0	320016	0	1	0	42	320002	0	2	34	0	0	0	5109	1	17	1	1	202003	0	320000	640000	100	200256	200748	201996	201180	196973

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 2.5015

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	22	23	24	37	3f	46	49	4e	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd store (99)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	ac	af	bc	l1d cache miss st nonspec (c0)	c2	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
960027	197566	1562	0	0	0	0	0	138	3	1	0	0	90665	200373	0	16	1402	17012	25	1051395	10	724910	320000	10	640000	320000	50	9320882	10712490	0	201171	200327	200002	37809	16	40025	960010	20	320000	640000	20	640000	1600000	200311	201215	1	1	80021	10	9	10	10	80000	80000	10	320000	0	42	26232	0	320002	0	5	320002	2	42	2	0	0	5019	1	17	1	1	201501	0	320000	640000	10	200864	200646	201910	200408	197813
960024	200731	1541	0	0	0	0	0	0	91	1	0	0	85781	199954	16	16	1500	17298	25	1040209	10	724018	320000	10	640000	320000	50	9344942	10832205	0	198406	198954	199246	38956	3	39933	960010	20	320000	640000	20	640000	1600000	201447	202056	2	1	80021	10	9	10	10	80000	80000	10	320060	0	0	25903	0	320002	0	1091	320002	2	42	0	0	0	5019	1	17	1	1	201314	0	320000	640000	10	198757	200748	202399	199531	200763
960024	200512	1546	0	0	0	0	0	0	3	0	0	0	88619	199113	16	16	1589	16724	25	1047468	10	729430	320000	10	640000	320000	50	9270154	10680479	0	199710	200486	199209	39805	3	40431	960010	20	320000	640000	20	640000	1600000	200721	199557	1	1	80021	10	9	10	10	80000	80000	10	320000	0	42	25967	0	320002	0	3	320002	2	0	0	0	0	5019	1	17	1	1	197724	0	320000	640000	10	198892	199959	198193	200948	199898
960024	198430	1547	0	0	0	0	0	12	4	0	0	0	89712	197321	0	16	1462	15999	25	1049053	10	720531	320060	10	640000	320000	50	9203175	10799525	1	200501	200325	198956	41398	3	40515	960010	20	320000	640000	20	640000	1600000	211843	199256	2	1	80021	10	9	10	10	80000	80000	10	320070	0	42	25551	0	320000	1	2	320000	0	42	0	0	0	5032	1	17	1	1	201793	0	320000	640000	10	201605	201934	199107	200275	198779
960024	199344	1541	0	0	0	0	0	0	3	0	1	0	84890	200143	16	16	1417	17168	25	1049623	10	730706	320000	10	640000	320000	50	9287140	10736502	0	200967	200202	200481	39939	3	39769	960010	20	320000	640000	20	640000	1600000	199866	200764	1	1	80021	10	9	10	10	80000	80000	10	320000	0	42	25742	2	320002	1	8	320002	2	42	0	0	0	5031	2	35	1	1	199629	0	320000	640000	10	200616	201064	202373	198630	201873
960024	199394	1550	1	1	0	3	4	264	440	0	0	0	80681	199976	16	16	1213	17302	132	1039209	10	725894	320180	10	640714	320216	50	9257554	10894549	0	200326	199395	200710	38755	3	39085	960010	20	320000	640000	20	640000	1600000	199728	197980	1	1	80021	10	9	10	10	80000	80000	10	320000	0	0	24463	0	320002	0	2	320002	2	42	0	0	0	5019	1	17	1	1	198996	0	320000	640000	10	196414	201040	198685	198178	201588
960024	201195	1529	0	0	0	0	0	18	4	0	0	0	82979	199683	16	16	1410	16627	25	1051765	10	727739	320000	10	640000	320000	50	9164838	10734418	0	199770	202761	200313	40940	3	39380	960010	20	320000	640000	20	640000	1600000	202093	197955	1	1	80021	10	9	10	10	80000	80000	10	320000	0	42	25112	0	320002	0	2	320002	2	42	0	0	0	5019	1	17	1	1	199601	0	320000	640000	10	199469	198265	201533	199554	200926
960024	201914	1548	0	0	0	0	0	0	3	0	0	0	84062	199089	16	16	1722	17030	25	1049677	10	717903	320000	10	640000	320000	50	9241905	10717062	0	199585	199948	201794	42014	3	39387	960010	20	320000	640000	20	640000	1600000	199445	199450	1	1	80021	10	9	10	10	80000	80000	10	320000	0	42	25693	0	320002	0	5	320002	2	42	0	0	0	5019	1	17	1	1	199972	0	320000	640000	10	199760	198260	200121	201957	198768
960024	200119	1551	0	0	0	0	0	0	3	0	0	0	88056	197103	0	16	1443	16916	25	1047490	10	725309	320000	10	640000	320000	50	9192040	10865590	0	200208	202099	200470	39988	3	38701	960010	20	320000	640000	20	640000	1600000	200195	200845	1	1	80021	10	9	10	10	80000	80000	10	320000	0	42	25178	0	320002	1	2	320002	2	42	0	0	0	5019	1	17	1	1	201392	0	320000	640000	10	198452	201637	199431	200666	200657
960024	199788	1555	0	0	0	0	0	0	3	0	0	0	86049	200316	16	16	1597	15577	25	1047039	10	729858	320000	10	640000	320000	50	9236494	10748617	0	200982	197276	200114	39594	3	56055	960010	20	320000	640000	20	640000	1600000	198733	198686	1	1	80021	10	9	10	10	80000	80000	10	320000	0	0	24181	0	320002	0	2	320002	2	42	0	1	0	5020	1	17	1	1	201046	0	320000	640000	10	199625	201665	197647	200360	201127

ST4 (multiple, 2D)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations