Firestorm: ST4 (multiple, 2S) measurements

Code:

  st4 { v0.2s, v1.2s, v2.2s, v3.2s }, [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 6.000

Issues: 6.000

Integer unit issues: 0.000

Load/store unit issues: 2.000

SIMD/FP unit issues: 4.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	1f	22	24	37	3a	3f	46	49	51	schedule uop (52)	schedule simd uop (54)	schedule ldst uop (55)	dispatch simd uop (57)	dispatch ldst uop (58)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	5f	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd store (99)	inst ldst (9b)	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	l1d cache miss st nonspec (c0)	c2	c9	cf	d0	d2	l1i cache miss demand (d3)	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	f5	f6	f7	f8	fd
66007	29247	229	5	1	0	4	0	0	0	0	1	1	0	1	4609	29234	0	2	16050	6000	4000	2000	4000	2000	25614	35804	18	23730	28978	29217	3	10	6000	2000	4000	4000	10000	29280	29124	1	1	61001	1000	1000	2000	2	0	0	2000	0	0	3	2000	6	0	0	13023	9220	6925	3110	0	56	20145	3233	3801	17	59	59	28440	16378	13253	14239	2000	4000	29280	29384	29392	29284	29111
66004	29223	227	0	0	0	1	0	0	0	0	0	0	0	0	4630	29329	2	0	16144	6000	4000	2000	4000	2000	25624	35804	4	23852	29103	29318	3	10	6000	2000	4000	4000	10000	29197	29374	1	1	61001	1000	1000	2000	0	4	0	2000	0	0	0	2000	0	0	0	12972	9198	6911	3118	0	57	20095	3193	3812	20	52	55	28476	16061	13574	14076	2000	4000	29391	29309	29317	29404	29352
66004	29330	227	1	1	0	0	0	0	0	0	1	0	0	0	4618	29200	0	0	15866	6000	4000	2000	4000	2000	25621	35805	13	23804	29054	29493	3	10	6000	2000	4000	4000	10000	29274	29293	1	1	61001	1000	1000	2004	2	4	0	2000	2	0	0	2000	4	0	0	13132	9178	6885	3165	1	56	20108	3217	3812	21	54	56	28571	15877	13502	14141	2000	4000	29497	29370	29279	29334	29383
66004	29285	227	1	1	0	0	0	0	0	0	0	1	0	0	4673	29324	2	0	16083	6000	4000	2000	4000	2000	25608	35799	8	23871	29150	29237	3	10	6000	2000	4000	4000	10000	29304	29299	1	1	61001	1000	1000	2000	0	0	0	2000	1	0	0	2000	4	0	0	13120	9245	6961	3119	0	56	20020	3231	3814	25	55	58	28517	16542	13241	14173	2000	4000	29149	29194	29379	29462	29288
66004	29436	228	0	0	0	0	0	0	0	0	0	0	0	0	4676	29234	0	2	15957	6001	4000	2000	4000	2000	25605	35800	7	23806	29092	29217	3	10	6000	2000	4000	4000	10000	29252	29381	1	1	61001	1000	1000	2000	0	6	0	2000	0	0	6	2000	4	0	0	13015	9260	6920	3124	0	57	20194	3234	3805	19	57	56	28552	16101	13262	13934	2000	4000	29352	29349	29353	29246	29343
66004	29341	228	4	1	0	0	0	0	0	0	0	0	0	0	4709	29244	2	0	16149	6000	4000	2000	4000	2000	25617	35808	10	23842	29096	29297	3	10	6000	2000	4000	4000	10000	29324	29348	1	1	61001	1000	1000	2000	0	0	0	2000	0	0	0	2000	4	0	0	13136	9494	6874	3156	1	57	20041	3260	3810	18	54	58	28596	16248	13616	14072	2000	4000	29270	29302	29455	29365	29392
66004	29400	227	1	1	0	1	0	0	0	0	0	0	0	0	4564	29212	2	0	16136	6000	4000	2000	4000	2000	25607	35838	5	23803	29119	29402	3	10	6000	2000	4000	4000	10000	29288	29331	1	1	61001	1000	1000	2000	0	4	0	2000	0	0	3	2000	0	0	0	12920	9368	6917	3060	0	49	20129	3156	3810	22	59	57	28491	16426	13407	14206	2000	4000	29313	29286	29515	29335	29476
66004	29345	229	0	0	0	1	0	0	0	0	0	0	1	0	4561	29171	0	2	16108	6000	4000	2000	4000	2000	25608	35813	4	23788	29144	29326	3	28	6000	2000	4000	4000	10000	29359	29326	1	1	61001	1000	1000	2004	0	4	0	2000	0	0	3	2000	4	0	0	13097	9213	6867	3096	0	56	20147	3233	3812	24	51	55	28581	16241	13507	14193	2000	4000	29368	29277	29227	29264	29383
66004	29292	228	1	0	0	0	0	0	0	0	1	0	0	0	4589	29278	0	0	16017	6000	4000	2000	4000	2002	25597	35810	0	23814	29210	29286	3	10	6000	2000	4000	4000	10000	29190	29266	1	1	61001	1000	1000	2000	0	0	0	2000	0	0	0	2000	0	0	0	13156	9455	6873	3154	1	52	20157	3226	3815	16	58	61	28611	16477	13331	13909	2000	4000	29252	29403	29347	29309	29149
66004	29388	227	1	1	0	1	0	0	0	9	1	0	1	0	4666	29170	0	0	16038	6000	4000	2000	4000	2000	25607	35810	3	23844	29122	29416	3	10	6000	2000	4000	4000	10000	29252	29385	1	1	61001	1000	1000	2000	0	6	0	2000	0	0	0	2000	6	0	0	13022	9401	6967	3157	1	60	20168	3210	3811	16	50	51	28547	16447	13202	14209	2000	4000	29335	29401	29299	29316	29299

Count: 8

Code:

  st4 { v0.2s, v1.2s, v2.2s, v3.2s }, [x6]
  st4 { v0.2s, v1.2s, v2.2s, v3.2s }, [x6]
  st4 { v0.2s, v1.2s, v2.2s, v3.2s }, [x6]
  st4 { v0.2s, v1.2s, v2.2s, v3.2s }, [x6]
  st4 { v0.2s, v1.2s, v2.2s, v3.2s }, [x6]
  st4 { v0.2s, v1.2s, v2.2s, v3.2s }, [x6]
  st4 { v0.2s, v1.2s, v2.2s, v3.2s }, [x6]
  st4 { v0.2s, v1.2s, v2.2s, v3.2s }, [x6]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.2629

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	22	24	37	3a	3f	46	49	4e	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd store (99)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	da	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
480207	100287	784	0	0	0	0	0	0	0	5	0	0	43657	0	101392	16	16	2147	6615	25	518071	100	362248	160000	100	320000	160000	500	4587826	5690723	0	102246	0	99620	101049	20414	3	21526	480100	200	160000	320000	200	320000	800000	100987	102806	1	1	80201	100	99	100	100	80000	80000	100	160000	0	34	11548	0	160002	2	0	2	160000	2	34	0	0	5109	1	17	0	0	1	1	102000	0	0	160000	320000	100	103011	100929	101887	100449	101276
480204	101030	788	0	0	0	0	0	0	0	2	0	0	41308	0	102443	16	16	2192	7231	25	521034	100	361495	160000	100	320000	160000	500	4694044	5838584	0	100543	0	99526	101721	21176	3	21548	480100	200	160000	320000	200	320000	800000	99447	100298	1	1	80201	100	99	100	100	80000	80000	100	160000	0	34	10696	0	160002	0	0	2	160002	2	34	0	0	5110	1	17	0	0	1	1	100035	0	0	160000	320000	100	99877	101214	101115	99926	100405
480204	100532	778	0	0	0	0	0	0	0	8	0	0	43450	0	102888	16	16	1836	6812	25	519323	100	359693	160000	100	320000	160000	500	4587408	5786437	0	100727	0	100803	99807	20148	3	22283	480100	200	160000	320000	200	320000	800000	101582	101646	1	1	80201	100	99	100	100	80000	80000	100	160000	0	34	10907	0	160002	1	0	0	160002	2	34	0	0	5109	1	17	0	0	1	1	99517	0	0	160000	320000	100	101979	100781	102185	101014	101473
480204	101683	779	0	0	0	0	0	0	0	0	0	0	40772	0	102023	16	16	2231	6415	25	521526	100	362284	160000	100	320000	160000	500	4649924	5681175	0	101143	0	101058	100282	20481	3	22483	480100	200	160000	320000	200	320000	800000	101075	100490	1	1	80201	100	99	100	100	80000	80000	100	160000	0	34	10403	0	160002	0	0	2	160002	2	38	0	0	5109	1	17	0	0	2	1	102093	0	2	160000	320000	100	101177	99967	100019	100883	101172
480204	100545	788	0	0	0	0	0	0	0	3	0	0	45424	0	100718	16	16	2473	6788	25	524391	100	360772	160000	100	320000	160000	500	4679319	5567044	1	101904	3	100050	100769	21806	3	21406	480100	200	160000	320000	200	320000	800000	100906	101519	1	1	80201	100	99	100	100	80000	80000	100	160000	0	34	11113	0	160002	1	2	8	160002	0	34	0	0	5109	2	17	0	0	1	1	101139	0	0	160000	320000	100	100239	100638	101423	99984	101375
480204	101531	787	0	0	0	0	0	0	0	2	0	0	40384	0	101674	16	16	2334	6939	25	521753	100	361297	160000	100	320000	160000	500	4769361	5539595	0	103180	0	100872	100235	20477	3	21720	480100	200	160000	320000	200	320000	800000	101206	101300	1	1	80201	100	99	100	100	80000	80000	100	160000	0	34	8884	0	160002	0	0	2	160002	2	34	0	0	5109	1	17	0	0	1	1	100819	0	0	160000	320000	100	100861	101273	102492	100719	101441
480204	100637	786	0	0	0	0	0	0	12	0	0	0	41107	0	101521	16	16	1977	6626	25	521510	100	361044	160000	100	320000	160000	500	4648058	5638873	0	99873	0	100877	100578	20171	3	21205	480100	200	160000	320000	200	320000	800000	100586	102318	1	1	80201	100	99	100	100	80000	80000	100	160000	0	34	10231	0	160002	1	0	5	160002	2	34	0	0	5109	1	17	0	0	1	1	102234	0	0	160000	320000	100	101674	101131	100756	99338	101304
480204	100391	794	0	0	0	0	0	0	138	2	0	0	40164	0	101118	16	16	2351	6403	52	523416	100	362256	160000	100	320000	160000	500	4702818	5503912	0	101033	0	100946	101059	19794	3	21295	480100	200	160000	320000	200	320000	800000	100216	100325	1	1	80201	100	99	100	100	80000	80000	100	160000	0	34	10083	0	160002	0	0	2	160002	2	34	0	0	5110	1	17	0	0	1	1	101665	0	0	160000	320000	100	102558	100979	99067	100110	101574
480204	100976	788	0	0	0	0	0	0	18	8	0	0	41090	0	101330	16	16	2186	6360	25	522828	100	361703	160000	100	320000	160000	500	4744951	5559405	0	102086	0	101744	99701	19548	3	21070	480100	200	160000	320000	200	320000	800000	100004	102802	1	1	80201	100	99	100	100	80000	80000	100	160000	0	34	10962	0	160002	0	0	2	160002	2	34	0	0	5122	3	35	0	0	3	3	100609	1	0	160000	320000	100	100611	100766	103221	101965	101773
480204	100365	792	0	1	1	1	21	22	2640	1674	0	0	41465	0	102665	16	16	2277	6502	78	522274	100	362130	160120	100	320472	160216	500	4744800	5556795	0	100899	0	101526	101084	21106	12	21683	480788	200	160240	320480	200	320480	801800	101153	102473	3	1	80201	100	99	100	100	80000	80000	100	160120	2	34	10764	2	160062	1	4	1042	160062	2	34	0	0	5109	1	17	0	0	1	1	101324	0	0	160000	320000	100	101205	100954	100619	101465	102462

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.2647

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	23	24	37	3a	3f	46	49	4e	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd store (99)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d cache miss st (a2)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	c2	branch mispred nonspec (cb)	cd	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
480027	101201	747	0	0	0	0	0	0	3	0	0	40259	0	101036	0	16	2204	6569	25	521628	10	360847	160000	10	320000	160000	50	4705696	5606471	101977	99992	100303	22337	3	21081	480010	20	160000	320000	20	320000	800000	102212	99749	1	1	80021	10	9	10	10	80000	80000	10	160000	42	10053	0	160002	0	0	2	160062	2	42	0	0	0	5019	0	18	17	18	35	101776	160000	320000	10	102135	101683	100735	102028	102157
480024	101586	790	0	0	0	0	0	0	2	0	1	40636	0	102948	16	16	2033	7132	25	519832	10	360992	160000	10	320000	160000	50	4712664	5672311	101088	99714	101866	22162	3	19989	480010	20	160000	320000	20	320000	800000	101861	101204	1	1	80021	10	9	10	10	80000	80000	10	160000	34	10588	0	160002	1	0	2	160002	2	0	0	0	0	5019	0	11	17	19	19	100922	160000	320000	10	100699	100987	101946	100529	101275
480024	102312	790	0	0	0	0	0	12	2	0	1	40536	0	99641	16	16	2401	6339	25	522736	10	364941	160000	10	320000	160000	50	4682130	5781663	101281	101274	101231	21711	3	21072	480010	20	160000	320000	20	320000	800000	100091	102135	1	1	80021	10	9	10	10	80000	80000	10	160000	34	10679	0	160002	0	0	2	160000	0	34	0	0	0	5019	0	19	17	19	20	101453	160000	320000	10	101793	100856	102124	101057	101269
480024	100079	780	0	0	0	0	0	0	8	0	1	42189	0	101493	16	16	2025	7195	25	523246	10	359028	160000	10	320000	160000	50	4713619	5669015	100419	101097	101610	21387	3	21529	480010	20	160000	320000	20	320000	800000	102267	101046	1	1	80021	10	9	10	10	80000	80000	10	160000	36	10858	0	160002	0	0	2	160000	2	34	0	0	0	5020	0	18	17	18	18	100195	160000	320000	10	101940	101309	99575	101520	101382
480024	101704	792	0	0	0	0	0	0	2	0	0	40863	0	101260	16	16	2216	6488	25	521022	10	362344	160000	10	320000	160000	50	4686227	5539524	102652	102627	101690	21500	3	21481	480010	20	160000	320000	20	320000	800000	101840	102251	1	1	80021	10	9	10	10	80000	80000	10	160000	34	11168	0	160002	1	0	0	160002	2	34	0	0	0	5019	0	25	17	20	19	101276	160000	320000	10	100875	100845	101708	102113	101982
480024	100754	812	0	0	0	0	0	12	2	0	1	42627	0	102095	16	16	2123	6396	25	522474	10	361678	160000	10	320000	160000	50	4690402	5727515	101279	101615	101490	21426	3	21112	480010	20	160000	320000	20	320000	800000	101389	99674	1	1	80021	10	9	10	10	80000	80000	10	160000	34	11164	0	160002	0	0	2	160000	2	34	0	0	0	5019	0	18	17	19	19	101856	160000	320000	10	100771	102170	102377	101658	100341
480024	100923	776	0	0	0	0	0	0	2	0	0	42606	0	99523	16	16	2355	6673	25	521531	10	360715	160000	10	320000	160000	50	4641662	5698820	101158	102812	99630	21380	3	21221	480354	20	160000	320240	20	320000	800000	100643	101270	1	1	80021	10	9	10	10	80000	80000	10	160000	34	17464	0	160002	0	0	2	160002	2	34	0	1	0	5020	0	17	17	18	17	100759	160000	320000	10	100334	100586	101624	101736	101267
480024	102147	782	0	0	0	0	0	0	2	0	0	38858	0	101331	0	0	2413	7069	25	521425	10	363273	160000	10	320000	160000	50	4612427	5654321	100720	100377	100727	22177	3	21446	480354	20	160000	320000	20	320000	800000	102347	99491	1	1	80021	10	9	10	10	80000	80000	10	160000	34	10603	0	160000	0	0	2	160002	2	34	0	0	0	5020	0	9	17	19	20	101499	160000	320000	10	100971	99948	101208	101362	101590
480024	102278	778	0	0	0	0	0	0	2	0	0	39092	0	100891	0	16	1947	6745	25	520815	10	358404	160000	10	320000	160000	50	4765421	5679362	99444	100800	101181	19886	3	22556	480010	20	160000	320000	20	320000	800000	100759	98328	2	1	80021	10	9	10	10	80000	80000	10	160000	34	10750	0	160002	0	0	0	160002	2	34	0	0	0	5032	0	12	17	10	18	101372	160000	320000	10	100933	101325	102685	101635	100547
480024	99166	770	0	0	0	0	0	0	8	0	0	42131	0	100767	0	16	2129	6614	25	518869	10	361863	160000	10	320000	160000	50	4641910	5794914	99461	101022	102003	20995	3	20340	480010	20	160000	320000	20	320000	800000	101535	101419	1	1	80021	10	9	10	10	80000	80000	10	160000	34	10469	0	160002	1	0	2	160002	0	34	0	0	0	5020	0	18	17	19	12	101589	160000	320000	10	99746	101680	101756	100459	101359

ST4 (multiple, 2S)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations