Firestorm: ST4 (multiple, 4H) measurements

Code:

  st4 { v0.4h, v1.4h, v2.4h, v3.4h }, [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 6.000

Issues: 6.000

Integer unit issues: 0.000

Load/store unit issues: 2.000

SIMD/FP unit issues: 4.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	09	l2 tlb miss instruction (0a)	18	19	1e	1f	22	23	24	37	3a	3f	46	49	51	schedule uop (52)	schedule simd uop (54)	schedule ldst uop (55)	dispatch simd uop (57)	dispatch ldst uop (58)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	5f	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd store (99)	inst ldst (9b)	l1d tlb access (a0)	l1d cache miss st (a2)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	l1d cache miss st nonspec (c0)	cf	d0	d2	l1i cache miss demand (d3)	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	f5	f6	f7	f8	fd
66007	28806	223	26	0	18	1	0	0	0	1	0	0	0	4797	28720	0	0	15491	6000	4000	2000	4000	2000	25596	35807	14	23735	28822	28919	3	10	6000	2000	4000	4000	10000	28642	28758	1	1	61001	1000	1000	2000	5	2000	0	0	0	2000	0	13398	9874	6924	3310	11	44	19265	3162	3804	7	50	51	28241	15044	12407	12929	2000	4000	28550	28599	28487	28760	28539
66004	28719	223	21	0	22	0	0	0	1	0	0	0	0	4559	29033	2	0	15915	6000	4000	2000	4000	2000	25599	35801	23	23695	28965	29169	3	10	6000	2000	4000	4000	10000	29152	29183	1	1	61001	1000	1000	2000	0	2000	0	0	0	2000	0	12992	9166	6919	3084	8	44	20077	3252	3798	14	46	47	28591	16135	13449	13998	2000	4000	29137	29144	29389	29175	29232
66004	29394	227	24	0	19	0	0	0	1	0	0	0	1	4618	29215	0	0	15947	6000	4000	2000	4000	2000	25634	35807	18	23680	28912	29244	3	10	6000	2000	4000	4000	10000	29278	29054	1	1	61001	1000	1000	2000	4	2000	0	0	0	2000	4	12992	9276	6835	3040	6	48	19963	3152	3804	8	48	47	28589	16401	13472	14017	2000	4000	29183	29321	29356	29289	29378
66004	29325	227	11	0	23	0	0	0	1	1	0	0	0	4603	29180	0	0	15912	6000	4001	2000	4000	2000	25609	35812	9	23762	29028	29315	3	10	6000	2004	4000	4000	10000	29174	29203	1	1	61001	1000	1000	2000	4	2000	0	0	0	2000	4	13086	9250	6907	3116	8	39	20181	3242	3809	14	50	44	28402	16366	13690	13846	2000	4000	29332	29663	30796	30657	30613
66004	29207	237	20	1	22	0	0	0	0	1	0	1	0	4660	29268	0	0	16294	6000	4000	2000	4000	2000	25601	35804	8	23885	29379	29459	3	10	6000	2000	4000	4000	10000	29416	29438	1	1	61001	1000	1000	2000	6	2000	0	0	18	2000	6	13236	9588	6895	3187	6	52	20428	3316	3806	9	45	49	28840	16204	13353	14135	2000	4000	29487	29560	29493	29656	29556
66004	29462	237	23	0	17	1	0	0	598	0	0	1	0	4628	29381	2	0	16132	6000	4000	2000	4000	2000	25612	35802	0	23819	29065	29416	3	10	6000	2000	4000	4000	10000	29337	29306	1	1	61001	1000	1000	2000	4	2000	0	0	0	2000	6	13131	9350	6883	3135	11	49	20143	3245	3813	9	45	45	28683	15962	13362	13765	2000	4000	29347	29384	29323	29307	29470
66004	29323	227	22	0	21	0	0	0	0	0	0	1	0	4672	29291	0	0	16110	6000	4000	2000	4000	2000	25689	35799	0	23877	29292	29475	3	28	6000	2000	4000	4000	10000	29280	29334	1	1	61001	1000	1000	2000	4	2000	0	0	0	2000	0	13081	9479	6887	3100	9	50	20165	3252	3807	11	39	38	28659	16203	13241	14199	2000	4000	29436	29347	29423	29498	29464
66004	29306	228	19	0	18	0	0	0	1	0	0	0	0	4649	29282	0	0	16195	6000	4000	2000	4000	2000	25609	35806	3	23791	29208	29436	3	10	6000	2000	4000	4000	10010	29336	29273	1	1	61001	1000	1000	2000	6	2000	0	0	0	2000	6	12985	9540	6892	3140	12	48	20082	3328	3805	13	52	48	28670	16119	13294	14177	2000	4000	29394	29427	29504	29360	29473
66004	29248	227	16	0	18	0	0	0	1	0	0	1	0	4712	29270	0	2	16136	6000	4000	2000	4000	2000	25613	35844	5	23789	29227	29401	3	28	6000	2000	4000	4000	10000	29345	29350	1	1	61001	1000	1000	2000	0	2000	0	0	395	2000	6	13088	9327	6918	3139	11	53	20166	3347	3809	6	46	41	28676	16097	13479	14247	2000	4000	29349	29449	29419	29440	29354
66004	29260	228	16	0	18	0	0	9	1	0	0	1	0	4650	29339	0	0	16067	6001	4000	2000	4000	2002	25629	35801	4	23831	29171	29476	3	10	6000	2000	4000	4000	10000	29337	29416	2	1	61001	1000	1000	2000	0	2000	0	0	0	2000	0	13181	9259	6918	3173	6	49	20127	3305	3810	7	53	52	28717	16083	13188	13861	2000	4000	29453	29311	29482	29349	29332

Count: 8

Code:

  st4 { v0.4h, v1.4h, v2.4h, v3.4h }, [x6]
  st4 { v0.4h, v1.4h, v2.4h, v3.4h }, [x6]
  st4 { v0.4h, v1.4h, v2.4h, v3.4h }, [x6]
  st4 { v0.4h, v1.4h, v2.4h, v3.4h }, [x6]
  st4 { v0.4h, v1.4h, v2.4h, v3.4h }, [x6]
  st4 { v0.4h, v1.4h, v2.4h, v3.4h }, [x6]
  st4 { v0.4h, v1.4h, v2.4h, v3.4h }, [x6]
  st4 { v0.4h, v1.4h, v2.4h, v3.4h }, [x6]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.2641

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	18	19	1e	1f	22	23	24	37	3f	46	49	4e	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd store (99)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
480207	99906	790	0	0	0	0	3	0	0	0	40747	101789	16	16	2269	6508	25	518545	100	361501	160000	100	320000	160000	500	4691682	5553508	100920	101819	101929	21389	12	21804	480100	200	160000	320000	200	320000	800000	101161	100736	1	1	80201	100	99	100	100	80000	80000	100	160000	0	42	11001	0	160002	0	0	2	160062	2	42	0	5109	1	17	1	1	101091	160000	320000	100	101606	100663	99771	102339	101092
480204	102376	782	0	0	0	0	3	0	0	0	40213	99494	16	16	2010	6021	25	522350	100	361559	160000	100	320000	160000	500	4726163	5722810	100083	100176	101518	20328	3	21817	480100	200	160000	320000	200	320000	800000	101207	101238	1	1	80201	100	99	100	100	80000	80000	100	160000	0	42	10883	0	160002	0	0	5	160002	2	44	0	5109	1	17	1	1	101843	160000	320000	100	102178	102457	100533	99909	100896
480204	100160	792	0	0	0	0	4	0	0	0	41624	100203	16	16	2397	6855	25	519983	100	362390	160000	100	320000	160000	500	4614993	5669215	100661	101972	100831	21181	230	22202	480788	200	160000	320000	200	320000	800000	101492	102128	1	1	80201	100	99	100	100	80000	80000	100	160060	0	0	10491	0	160000	1	0	0	160000	2	42	0	5110	1	17	1	1	101454	160000	320000	100	102605	100539	100897	100029	100830
480204	106164	795	0	0	0	0	3	0	0	0	40330	102422	0	16	2284	6591	25	518784	100	365541	160000	100	320000	160000	500	4733225	5689211	99616	102287	101478	21083	3	20872	480444	200	160000	320000	200	320000	800000	101666	102099	1	1	80201	100	99	100	100	80000	80000	100	160000	0	45	11218	0	160000	0	0	0	160002	4	42	0	5110	1	17	1	1	100642	160000	320000	100	102323	100667	101528	101285	100304
480204	101816	784	0	0	0	0	3	0	0	0	43834	101362	16	16	2139	7003	25	522208	100	359886	160000	100	320000	160000	500	4694486	5652483	100676	102319	100992	21248	3	22863	480100	200	160000	320000	200	320000	800000	101548	100653	1	1	80201	100	99	100	100	80000	80000	100	160000	0	42	10849	0	160002	1	0	5	160002	2	42	0	5109	1	26	1	1	100461	160000	320000	100	100982	99101	100560	101660	99614
480204	101439	787	0	0	0	0	3	0	0	0	39000	100741	16	16	2267	5761	25	522912	100	362823	160000	100	320000	160000	500	4653578	5683910	99941	101458	101082	21723	3	21370	480100	200	160000	320000	200	320000	800000	101710	98169	2	1	80201	100	99	100	100	80000	80000	100	160000	0	42	10454	0	160002	0	0	2	160002	2	42	0	5109	1	17	1	1	102210	160000	320000	100	100640	102059	101923	100993	101971
480204	101732	787	0	0	0	0	91	0	0	0	41990	97999	16	16	1935	6624	25	520285	100	361852	160000	100	320000	160108	500	4707593	5734853	100838	101615	100062	21868	3	20670	480100	200	160000	320000	200	320000	800000	100976	101288	1	1	80201	100	99	100	100	80000	80000	100	160000	0	42	9891	0	160002	0	0	2	160002	2	42	0	5109	1	17	1	1	101472	160000	320000	100	101293	101232	101187	101016	101157
480204	100874	783	0	0	0	0	3	0	0	0	42680	100616	16	16	2180	6693	25	522432	100	362196	160000	100	320000	160000	500	4657852	5561293	101374	101003	99429	20439	12	21668	480790	200	160240	320480	200	320720	800600	102744	101891	3	1	80201	100	99	100	100	80000	80000	100	160062	2	42	10913	2	160182	0	0	1907	160122	2	44	2	5135	1	35	1	1	101152	160000	320000	100	101689	102189	102543	100589	101237
480204	101783	779	0	17	18	2376	1587	0	0	0	42356	101111	16	0	1761	7243	80	522019	100	361365	160120	100	320472	160324	500	4620894	5646395	102299	100363	101940	20379	19	21123	480790	200	160370	320480	200	320480	801200	101897	101430	3	1	80201	100	99	100	100	80000	80000	100	160000	0	42	10402	0	160002	0	0	2	160002	2	42	0	5110	1	17	1	1	101154	160000	320000	100	99985	102029	100781	102397	101303
480204	101255	771	0	0	0	24	4	0	0	0	42500	99974	16	16	2325	5386	25	521651	100	359336	160000	100	320000	160000	500	4636715	5585126	101079	101157	100701	21197	3	20867	480100	200	160000	320000	200	320000	800000	100462	99884	1	1	80201	100	99	100	100	80000	80000	100	160000	0	42	10403	0	160002	0	0	2	160002	2	42	0	5110	1	17	1	1	102156	160000	320000	100	100848	100747	100530	102362	99854

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.2627

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	22	24	37	3a	3f	46	49	4e	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	91	inst branch cond (94)	inst int alu (97)	inst simd store (99)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	branch cond mispred nonspec (c5)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
480027	100730	781	0	0	0	0	0	0	15	3	0	0	40289	0	101221	16	16	2258	5924	25	521375	10	360503	160000	10	320000	160000	50	4730257	5635751	1	101485	101294	100164	17628	3	21169	480010	20	160000	320000	20	320000	800000	99845	100695	1	1	80021	10	9	0	10	10	80000	80000	10	160000	0	49	9784	0	160062	0	0	5	160002	16	44	14	0	0	5019	13	17	13	13	101792	160000	320000	10	100309	102506	101791	100321	102101
480024	100443	776	1	0	0	0	0	0	0	14	1	0	41888	1	102013	16	16	2485	7127	25	523193	10	364605	160000	10	320000	160000	50	4634510	5813248	1	102040	100450	102489	21159	3	21411	480010	20	160000	320000	20	320000	800000	101719	101913	1	1	80021	10	9	0	10	10	80000	80000	10	160015	15	43	11480	0	160014	3	0	16	160002	14	44	14	0	0	5019	6	17	10	13	100346	160000	320000	10	100488	99565	99523	101044	99810
480024	99735	782	1	0	0	0	1	0	18	14	1	0	42311	1	101017	16	16	2215	7126	51	523386	10	363668	160000	10	320000	160000	50	4677359	5579564	0	99810	101433	101988	21914	3	21779	480010	20	160000	320256	20	320000	800000	101791	101928	1	1	80021	10	9	0	10	10	80000	80000	10	160015	14	44	11107	0	160016	0	1	17	160002	16	44	14	0	0	5019	13	17	6	13	101741	160000	320000	10	101458	101870	101536	99529	102123
480024	101236	776	1	0	1	0	0	0	0	17	0	0	40568	1	102163	16	16	2116	6118	25	520675	10	363903	160000	10	320000	160000	50	4707204	5611223	0	101365	104256	99912	21634	3	21380	480010	20	160000	320000	20	320000	800000	102027	101237	1	1	80021	10	9	0	10	10	80000	80000	10	160014	15	44	11500	1	160016	0	0	16	160002	16	44	14	1	0	5019	6	17	13	13	101601	160000	320000	10	100314	99872	100800	102140	101272
480024	99789	782	1	0	2	1	0	2	396	102	1	0	41176	1	99848	0	16	2219	6803	80	521295	10	361934	160120	10	320472	160216	50	4686195	5653490	0	102398	102783	100770	21483	22	20731	480354	20	160240	320240	20	320240	801200	101227	100509	2	1	80021	10	9	0	10	10	80000	80000	10	160074	14	43	11779	3	160136	0	3	2036	160122	16	44	14	0	0	5033	14	26	14	8	100891	160000	320000	10	100332	100269	101465	100830	100715
480024	101489	777	1	2	0	0	3	1	396	17	0	0	39941	1	103591	16	16	2148	6685	25	523152	10	364269	160000	10	320000	160000	50	4676946	5702265	0	100813	101834	100176	19229	3	21919	480010	20	160000	320000	20	320000	800000	101523	100583	1	1	80021	10	9	0	10	10	80000	80000	10	160014	14	0	10803	1	160014	0	0	14	160002	16	0	14	1	0	5019	11	17	15	9	101936	160000	320000	10	100079	101354	101405	101646	99450
480024	102057	789	1	0	1	1	0	0	0	14	0	0	42662	1	100813	0	0	2152	7008	25	516890	10	363194	160000	10	320000	160000	50	4766909	5891398	0	100865	101295	100745	21157	3	21951	480010	20	160000	320000	20	320000	800000	102096	101173	1	1	80021	10	9	0	10	10	80000	80000	10	160016	16	44	11423	0	160016	0	0	16	160002	14	2	14	0	0	5019	13	17	13	13	101568	160000	320000	10	101547	102678	100174	101200	102728
480024	101431	787	1	1	1	1	0	0	0	17	0	0	42487	1	100697	15	16	2056	6355	25	522066	10	362790	160000	10	320000	160000	50	4676210	5582265	0	101538	101090	100491	21182	3	18893	480010	20	160000	320000	20	320000	800000	99136	100603	1	1	80021	10	9	2	10	10	80000	80000	10	160014	15	46	10130	1	160016	0	0	19	160002	16	44	14	0	0	5019	14	17	13	6	102174	160000	320000	10	101896	99794	100921	102027	100416
480024	101175	791	1	1	1	1	0	0	0	14	0	0	39108	1	101657	16	16	2163	5970	25	519196	10	363878	160000	10	320000	160000	50	4677557	5557814	0	100929	101936	101031	19575	3	21296	480010	20	160000	320000	20	320000	800000	102796	101840	1	1	80021	10	9	0	10	10	80000	80000	10	160015	15	44	9575	0	160014	0	0	16	160002	16	44	14	0	0	5019	6	17	11	13	101902	160000	320000	10	101438	101614	100254	100988	100217
480024	99649	785	1	1	0	0	0	0	0	15	0	0	42387	1	101315	16	16	1602	6593	25	523115	10	362924	160000	10	320000	160000	50	4742741	5567109	0	101227	100874	101078	21134	3	21424	480010	20	160000	320000	20	320000	800000	100812	100641	1	1	80021	10	9	0	10	10	80000	80000	10	160015	15	44	11081	1	160016	1	0	16	160002	16	44	14	1	0	5019	6	17	13	11	101149	160000	320000	10	100874	101222	101301	100201	101763

ST4 (multiple, 4H)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations