Firestorm: ST4 (multiple, 4S) measurements

Code:

  st4 { v0.4s, v1.4s, v2.4s, v3.4s }, [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 12.000

Issues: 12.000

Integer unit issues: 0.000

Load/store unit issues: 4.000

SIMD/FP unit issues: 8.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	1f	37	3a	3f	46	49	51	schedule uop (52)	schedule simd uop (54)	schedule ldst uop (55)	dispatch simd uop (57)	dispatch ldst uop (58)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	5e	5f	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd store (99)	inst ldst (9b)	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	c2	c9	cf	d0	d2	l1i cache miss demand (d3)	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	f5	f6	f7	f8	fd
72007	29613	238	22	1	0	17	0	0	0	0	0	0	4729	29526	0	0	15216	12000	8000	4000	8000	4000	51900	71610	0	12	24646	29332	29511	3	10	12000	4004	8000	8000	20000	29518	29548	1	1	61001	1000	1000	4000	0	12	0	4000	0	0	490	4000	0	12	0	0	13227	9493	6929	3230	6	61	19571	3329	3810	9	59	52	28756	16433	13064	13112	4000	8000	29448	29489	29540	29478	29436
72004	29493	237	22	0	0	16	0	0	0	0	0	0	4765	29462	0	4	15389	12000	8000	4000	8000	4000	51894	71602	0	5	24708	29572	29712	12	31	12005	4000	8008	8000	20000	29585	29545	2	1	61001	1000	1000	4006	0	12	2	4001	0	0	1560	4005	1	12	0	231	13139	9440	6917	3151	8	48	19606	3312	3808	21	59	53	28856	16590	12876	13272	4000	8000	29520	29632	29636	29590	29716
72004	29595	239	18	0	0	20	0	1	0	0	88	1	4648	29595	0	0	15345	12008	8004	4004	8000	4008	52020	71730	1	5	24854	29318	29691	8	49	12024	4012	8016	8008	20040	29638	29618	3	1	61001	1000	1000	4006	0	8	0	4004	0	0	933	4008	0	0	0	254	13267	9452	6878	3108	5	52	19921	3309	3817	11	56	57	28757	16139	13033	13212	4000	8000	29628	29557	29479	29550	29683
72004	29393	238	20	0	0	23	0	0	0	39	2	1	4611	29439	0	0	15376	12000	8000	4000	8000	4000	51909	71623	0	5	24724	29346	29587	3	10	12000	4000	8000	8000	20000	29609	29769	1	1	61001	1000	1000	4000	0	8	0	4000	0	0	1	4000	0	8	0	978	13063	9301	6943	3124	8	53	20237	3267	3808	15	50	49	28679	16331	12911	13051	4000	8000	29327	29390	29434	29379	30041
72004	30198	241	21	0	0	16	0	0	0	27	0	0	4530	29640	0	0	15858	12000	8000	4000	8000	4000	51908	71607	0	8	24682	29308	29572	3	10	12000	4000	8000	8000	20000	29589	30341	3	1	61001	1000	1000	4000	0	0	0	4000	0	0	1	4000	1	8	0	0	13120	9348	6974	3107	4	47	19469	3361	3813	8	52	55	28627	16390	12866	13117	4000	8000	29804	29712	29827	29470	29384
72004	30040	241	20	0	0	21	0	0	0	27	108	0	4678	29606	3	0	15218	12000	8000	4000	8000	4000	51900	71609	0	5	24643	29308	29374	3	10	12000	4000	8000	8000	20000	29403	29364	1	1	61001	1000	1000	4000	0	0	0	4000	1	0	0	4000	0	0	0	0	13075	9424	6903	3129	12	56	19541	3330	3804	18	60	54	28583	16124	12870	12916	4000	8000	29307	29398	29363	29428	29379
72004	29285	235	16	0	0	21	0	0	0	24	1	0	4604	29374	0	0	15031	12001	8000	4000	8000	4000	51896	71608	0	9	24659	29164	29644	3	10	12000	4000	8000	8000	20000	29582	29496	1	1	61001	1000	1000	4000	0	0	0	4000	0	2	0	4001	0	8	0	0	12927	9380	6919	3156	6	50	19367	3309	3810	23	50	56	29239	15977	12827	12816	4000	8000	30135	29898	30005	30174	29377
72004	29385	236	16	0	0	20	0	0	0	9	1	0	4644	30120	0	0	16024	12000	8000	4000	8035	4019	52735	72412	0	9	25014	29474	29417	80	259	12060	4039	8116	8084	20235	30159	29781	2	1	61001	1000	1000	4042	4	8	0	4026	1	0	8643	4026	0	8	0	0	13030	9435	6969	3169	6	57	19176	3375	3812	12	55	56	28646	16009	12718	13075	4000	8000	29415	29380	29393	29403	29398
72004	29407	237	20	0	0	19	0	0	0	0	1	0	4658	29316	4	0	15097	12000	8008	4000	8000	4000	51903	71631	0	5	24712	29317	29486	3	10	12011	4000	8000	8000	20000	29367	29400	1	1	61001	1000	1000	4000	0	8	0	4000	0	0	0	4000	0	0	0	0	13270	9242	6979	3118	7	49	19422	3297	3815	12	52	51	28796	16191	12893	12896	4000	8000	29559	29515	29334	29538	29471
72004	29424	236	18	0	0	19	0	0	0	0	1	0	4652	29302	0	0	15068	12000	8000	4000	8000	4000	51963	71618	0	1	24672	29175	29439	10	10	12012	4000	8000	8000	20000	29580	29681	4	1	61001	1000	1000	4024	2	8	0	4022	3	2	3391	4013	0	8	0	0	13072	9271	6949	3068	8	55	19927	3175	3816	12	53	52	29286	15945	12768	13044	4000	8000	29660	29552	29338	29326	29775

Count: 8

Code:

  st4 { v0.4s, v1.4s, v2.4s, v3.4s }, [x6]
  st4 { v0.4s, v1.4s, v2.4s, v3.4s }, [x6]
  st4 { v0.4s, v1.4s, v2.4s, v3.4s }, [x6]
  st4 { v0.4s, v1.4s, v2.4s, v3.4s }, [x6]
  st4 { v0.4s, v1.4s, v2.4s, v3.4s }, [x6]
  st4 { v0.4s, v1.4s, v2.4s, v3.4s }, [x6]
  st4 { v0.4s, v1.4s, v2.4s, v3.4s }, [x6]
  st4 { v0.4s, v1.4s, v2.4s, v3.4s }, [x6]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 2.5054

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	18	19	1e	1f	22	23	24	37	3a	3f	46	49	4e	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd store (99)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	c2	branch cond mispred nonspec (c5)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
960207	201382	1536	0	0	0	0	21	19	0	0	0	75826	0	201131	15	16	1344	17294	25	1045829	100	730081	320000	100	640000	320000	500	9313121	10799938	0	200042	200693	200984	41104	3	39618	960100	200	320120	640000	200	641200	1600600	198975	197673	3	1	80201	100	99	100	100	80000	80000	100	320254	0	36	25912	3	320196	0	0	1992	320002	16	34	4	0	0	5131	2	386	1	1	198968	320000	640000	100	198475	200244	199643	200091	200364
960204	199274	1532	0	1	0	0	0	8	0	0	0	87990	0	200597	16	16	1166	16913	25	1039294	100	726483	320000	100	640000	320000	500	9254584	10875532	0	200535	199397	199779	38329	3	38355	960100	200	320000	640000	200	640000	1600000	198930	198191	1	1	80201	100	99	100	100	80000	80000	100	320000	0	0	25363	0	320002	0	0	5	320002	2	34	0	0	0	5109	1	17	1	1	199291	320000	640000	100	200291	199078	199694	200599	199523
960204	199900	1558	0	0	0	0	6	2	1	0	0	88153	0	199150	16	16	1302	16703	25	1043526	100	723386	320000	100	640000	320000	500	9255309	10717764	0	201828	199522	201521	40363	3	39899	960100	200	320000	640000	200	640000	1600000	200982	199687	1	1	80201	100	99	100	100	80000	80000	100	320000	0	34	25496	0	320002	2	0	5	320002	2	34	0	0	0	5109	1	17	1	1	199596	320000	640000	100	201255	203080	199282	199494	201638
960204	200267	1547	0	0	0	0	9	0	0	0	0	79481	0	199350	0	0	1556	17768	25	1046374	100	726111	320000	100	640000	320000	500	9209300	10749072	0	201078	197539	199253	37826	3	40726	960100	200	320000	640000	200	640000	1600000	198549	200111	1	1	80201	100	99	100	100	80000	80000	100	320000	0	34	24431	0	320002	0	0	2	320002	2	0	0	0	0	5109	1	17	1	1	198491	320000	640000	100	198001	199497	201166	218655	200874
960204	199964	1550	0	0	0	0	0	2	0	0	0	83759	0	199680	16	16	1773	16471	25	1039204	100	725651	320000	100	640000	320000	500	9190850	10679363	0	200878	200401	197733	40720	3	40859	960100	200	320000	640000	200	640000	1600000	200669	200840	1	1	80201	100	99	100	100	80000	80000	100	320000	0	34	26674	0	320002	1	0	8	320002	2	36	0	0	0	5110	2	17	1	1	200625	320000	640000	100	200897	199442	201098	201140	199816
960204	200782	1553	0	0	1	0	51	8	0	1	0	80922	0	201035	16	16	1465	16888	25	1041046	100	729598	320000	100	640000	320000	500	9295157	10732547	1	198913	200737	200705	40565	3	38796	960100	200	320000	640000	200	640000	1600000	197491	200871	1	1	80201	100	99	100	100	80000	80000	100	320000	0	34	25806	0	320002	0	0	2	320002	2	34	0	0	0	5110	1	17	1	1	201100	320000	640000	100	199997	200893	199018	199359	201065
960204	201792	1557	0	0	0	0	0	2	0	0	0	86168	0	200338	16	16	1287	17267	133	1046130	102	727501	320240	104	640950	320324	500	9195021	10918333	0	201365	200572	199681	41695	46	53004	961484	202	320480	640960	200	640720	1602400	199174	201651	5	1	80201	100	99	100	100	80000	80000	100	320249	2	34	25521	7	320242	0	4	1915	320002	0	36	0	0	0	5109	1	17	1	1	201663	320000	640000	100	201059	198675	201561	201144	198941
960204	200803	1570	0	0	0	0	0	9	0	0	0	87592	0	199321	16	0	1465	17822	25	1046000	100	731611	320000	100	640000	320000	500	9088829	10900199	0	199389	201648	201251	40569	3	40208	960100	200	320000	640000	200	640000	1600000	199572	200107	1	1	80201	100	99	100	100	80000	80000	100	320000	0	34	24897	0	320000	0	0	2	320002	0	34	0	0	0	5122	2	17	1	1	220376	320000	640000	100	198467	201863	202331	200728	199487
960204	200917	1547	0	0	0	0	6	8	0	0	0	84546	0	199835	16	16	1223	16310	52	1050698	100	726057	320000	100	640000	320000	500	9242090	10879427	0	201047	201261	201820	39621	3	38596	960100	200	320000	640000	200	640000	1600000	198977	196672	1	1	80201	100	99	100	100	80000	80000	100	320000	0	34	25276	0	320002	0	0	1160	320002	2	36	0	0	0	5109	1	17	1	1	199018	320000	640000	100	201219	200685	198508	200593	201405
960204	199757	1553	0	0	0	0	30	2	0	0	0	87853	0	199147	0	16	1508	16485	25	1049109	100	729318	320000	100	640000	320000	500	9315569	10791892	0	202347	200727	201577	39420	121	42292	963910	200	321200	642400	200	642640	1606595	199490	200052	9	1	80201	100	99	100	100	80000	80000	100	320660	0	34	26782	0	320722	1	0	10067	320482	2	34	0	0	0	5109	1	26	1	1	198324	320000	640000	100	201300	200302	198648	201181	201434

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 2.5004

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	1f	23	37	3a	3f	46	49	4e	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd store (99)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d cache miss st (a2)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
960027	200631	1597	6	1	2	0	74	44	25611	14382	0	87808	0	199493	16	16	1603	16976	25	1040550	10	721905	320000	10	640000	320000	50	9301066	10831380	199729	199177	202012	41235	3	39954	960010	20	320000	640000	20	640000	1601200	200008	202121	1	1	80021	10	9	10	10	80000	80000	10	320000	34	25592	0	320000	1	0	14	320002	2	34	0	0	0	5019	12	17	14	8	199293	0	0	320000	640000	10	199574	199721	198756	202124	201143
960024	201331	1587	0	0	0	0	0	0	12	2	0	82447	0	196856	16	0	1348	16403	25	1046402	10	730092	320000	10	640000	320000	50	9233737	10725567	199590	198692	201864	38870	3	39537	960010	20	320000	640000	20	640000	1600000	201232	200633	1	1	80021	10	9	10	10	80000	80000	10	320000	34	26861	0	320002	1	0	2	320002	0	34	0	0	0	5019	6	17	13	7	201845	16	0	320000	640000	10	200362	199964	200692	202421	201190
960024	200923	1566	0	0	0	0	0	0	12	2	1	91135	0	197054	16	0	1104	17469	25	1049214	10	733089	320000	10	640000	320000	50	9374655	10789005	202038	196979	200670	40276	3	40553	960010	20	320000	640000	20	640000	1600600	198636	197911	1	1	80021	10	9	10	10	80000	80000	10	320000	34	25255	0	320240	2	0	2	320002	2	34	0	0	0	5019	12	17	7	13	199262	0	0	320000	640000	10	199261	200452	201226	200267	202585
960024	200538	1552	0	0	0	0	0	0	0	2	0	83796	0	200976	16	16	1438	16598	25	1042814	10	723203	320000	10	640238	320000	50	9259001	10778012	199969	200645	201724	40779	3	41076	960010	20	320000	640000	20	640000	1600000	197677	200277	1	1	80021	10	9	10	10	80000	80000	10	320000	34	26381	0	320002	0	0	2	320002	2	34	0	1	0	5019	12	17	12	12	202029	2	0	320000	640000	10	199524	199227	197969	201342	199412
960024	199291	1555	0	0	0	0	1	0	0	5	0	84213	0	200245	16	16	1805	17200	25	1053312	10	731334	320060	10	640000	320000	50	9266123	10819570	199291	199578	197759	41619	3	41876	960010	20	320120	640000	20	640000	1600000	200745	200061	1	1	80021	10	9	10	10	80000	80000	10	320000	34	24891	0	320002	1	0	5	320060	0	34	0	0	0	5019	8	17	12	12	199745	0	0	320000	640000	10	198851	197840	200579	197795	198744
960024	201037	1563	0	0	0	0	0	0	12	2	0	87193	0	201149	16	0	1559	17125	52	1048511	10	722556	320000	10	640000	320000	50	9253346	10762850	199948	199093	200846	40320	3	40006	960010	20	320000	640000	20	640000	1600000	199351	201145	2	1	80021	10	9	10	10	80000	80000	10	320000	36	25772	0	320062	1	0	827	320002	2	0	0	0	0	5019	12	17	12	12	199080	0	0	320000	640000	10	197816	200244	200987	202061	198624
960024	200761	1559	0	0	0	0	0	0	0	90	0	93124	0	199961	16	16	1344	16142	53	1046051	10	729804	320000	10	640000	320000	50	9091147	10980658	200726	198875	198872	39883	3	38279	960356	20	320000	640000	20	640000	1600000	200176	198320	1	1	80021	10	9	10	10	80000	80000	10	320060	34	24486	0	320002	0	0	17	320002	2	34	0	0	0	5019	13	17	12	5	201648	16	0	320000	640000	10	200537	201054	198031	197871	199490
960024	201117	1562	0	0	0	0	0	1	0	8	0	81903	0	196569	16	16	1371	16593	25	1049811	10	722036	320060	10	640000	320000	50	9319342	10753582	200240	196850	211265	36340	3	40462	960010	20	320120	640000	20	640000	1600000	200915	200546	1	1	80021	10	9	10	10	80000	80000	10	320000	0	26033	0	320062	1	0	2	320002	2	34	0	0	0	5020	12	17	13	7	199904	0	0	320000	640000	10	200029	200954	198998	201149	198724
960024	199616	1544	0	0	0	0	0	0	0	90	0	85259	0	202361	16	16	1565	17127	130	1039521	10	736101	320180	10	640952	320540	50	9384384	10752324	198469	202593	200185	40907	32	38577	961394	20	325040	641440	20	640960	1603000	197397	200099	5	1	80021	10	9	10	10	80000	80000	10	320180	34	27223	2	320180	0	2	43537	320122	2	34	0	1	0	5067	16	44	17	8	200381	102	0	320000	640000	10	197970	199342	198217	200325	199698
960024	199620	1517	0	0	0	0	0	0	0	8	0	79368	0	200674	16	0	1679	16719	25	1043993	10	728397	320000	10	640000	320000	50	9246928	10938181	199588	197980	200246	40865	3	41412	960010	20	320000	640000	20	640000	1600000	199848	199301	1	1	80021	10	9	10	10	80000	80000	10	320000	34	25681	0	320002	0	0	3	320002	2	34	0	0	0	5019	12	17	12	12	200306	0	0	320000	640000	10	201430	199784	200220	199727	199140

ST4 (multiple, 4S)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations