Firestorm: ST4 (multiple, 8H) measurements

Code:

  st4 { v0.8h, v1.8h, v2.8h, v3.8h }, [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 12.000

Issues: 12.000

Integer unit issues: 0.000

Load/store unit issues: 4.000

SIMD/FP unit issues: 8.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	1f	22	23	24	37	3a	3f	46	49	50	51	schedule uop (52)	schedule simd uop (54)	schedule ldst uop (55)	dispatch simd uop (57)	dispatch ldst uop (58)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	5f	60	61	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd store (99)	inst ldst (9b)	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	c9	cf	d0	d2	l1i cache miss demand (d3)	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	f5	f6	f7	f8	fd
72007	29370	237	1	14	0	1	15	1	0	0	21	4	1	0	0	0	4694	29336	0	1	0	15106	12000	8000	4000	8000	4000	51910	71611	5	0	0	24729	29240	29461	3	10	12000	4000	8000	8000	20000	29336	29343	1	1	61001	1000	1000	4005	5	15	3	4006	2	1	5	4000	6	0	4	1	0	13106	9487	6893	3138	10	40	19211	3258	3816	9	46	41	28642	16258	12920	12850	4000	8000	29591	29472	29492	29387	29331
72004	29463	236	1	18	0	1	23	1	0	0	366	4	1	0	0	0	4603	29141	1	3	0	15160	12000	8000	4000	8000	4000	51902	71633	3	0	0	24634	29256	29383	3	10	12000	4000	8000	8000	20000	29363	29396	1	1	61001	1000	1000	4006	5	0	1	4004	0	1	4	4000	4	0	4	2	0	13260	9479	6954	3149	7	45	19386	3381	3812	10	37	39	28713	16253	12810	13121	4000	8000	29340	29445	29338	29417	29339
72004	29366	237	1	19	0	1	15	1	0	0	45	9	0	0	0	0	4695	29306	3	2	0	15040	12000	8000	4000	8000	4000	51901	71621	9	0	0	24692	29281	29332	3	10	12000	4000	8000	8000	20000	29341	29349	1	1	61001	1000	1000	4005	5	8	1	4004	0	2	4	4002	4	15	4	1	0	13217	9570	6918	3085	11	42	19576	3184	3813	11	39	44	28802	16152	12749	13073	4000	8000	29316	29328	29561	29356	29350
72004	29348	236	1	23	1	1	17	1	0	0	21	9	0	0	0	0	4637	29327	0	3	0	15123	12000	8000	4000	8000	4000	51900	71632	5	0	0	24708	29235	29415	3	10	12000	4000	8000	8000	20000	29364	29237	1	1	61001	1000	1000	4005	4	0	1	4004	0	1	6	4002	4	0	4	2	0	13282	9338	6947	3105	10	48	19376	3152	3819	11	45	41	28674	15936	13089	13011	4000	8000	29312	29290	29415	29332	29310
72004	29481	236	1	21	1	1	17	0	0	0	270	5	0	0	0	0	4686	29243	3	3	0	15158	12000	8000	4000	8000	4000	51903	71616	8	0	7	24658	29160	29280	3	10	12000	4000	8000	8000	20000	29366	29258	1	1	61001	1000	1000	4005	5	15	1	4006	0	1	4	4000	6	8	4	0	0	13278	9531	6865	3130	10	38	19282	3307	3817	12	43	51	28572	16477	12951	13044	4000	8000	29352	29153	29197	29322	29357
72004	29416	236	1	17	0	1	14	1	0	0	297	9	1	0	0	1	4654	29279	0	3	0	15070	12000	8000	4000	8000	4000	51900	71606	9	0	0	24698	29138	29305	3	10	12000	4000	8000	8000	20000	29310	29276	1	1	61001	1000	1000	4005	5	15	1	4004	0	1	7	4000	4	15	4	1	0	13255	9499	6897	3109	4	51	19300	3225	3816	14	50	44	28795	16225	12812	12883	4000	8000	29404	29418	29320	29353	29414
72004	29446	236	1	15	1	1	19	1	0	0	264	4	1	0	0	1	4675	29290	2	2	0	15051	12000	8000	4000	8000	4000	51895	71584	6	0	0	24700	29181	29294	50	182	12084	4000	8000	8000	20000	29432	29358	1	1	61001	1000	1000	4005	4	8	1	4004	0	1	6	4000	6	8	4	3	0	13044	9383	6886	3128	5	39	19385	3298	3825	21	51	47	28797	16142	13094	13106	4000	8000	29464	29396	29389	29362	29410
72004	29426	237	1	12	0	1	19	2	0	0	171	4	0	0	0	1	4684	29312	2	0	0	15121	12000	8000	4000	8000	4000	51890	71607	5	0	0	24713	29287	29423	3	10	12000	4000	8000	8000	20000	29401	29393	1	1	61001	1000	1000	4005	5	15	0	4005	0	1	6	4000	4	15	4	1	0	13157	9183	6982	3101	5	38	19325	3347	3810	8	45	47	28699	16215	12975	12804	4000	8000	29348	29274	29480	29514	29303
72004	29420	236	1	23	1	1	18	1	0	0	414	9	0	0	0	0	4638	29264	2	3	0	15083	12000	8002	4000	8000	4000	51901	71608	2	0	0	24619	29290	29521	3	10	12000	4000	8000	8000	20000	29353	29422	1	1	61001	1000	1000	4006	5	15	1	4004	0	1	6	4000	4	16	4	1	0	13177	9334	6902	3098	7	43	19464	3335	3821	15	50	49	28801	16120	12686	13109	4000	8000	29400	29247	29461	29310	29405
72004	29229	236	1	7	1	0	13	1	0	0	495	4	0	0	0	0	4712	29341	0	0	0	15091	12000	8000	4000	8000	4000	51889	71590	8	0	0	24669	29252	29302	3	10	12000	4000	8000	8000	20000	29344	29358	1	1	61001	1000	1000	4005	6	15	1	4005	0	1	5	4000	4	0	4	1	0	13144	9487	6919	3117	9	44	19394	3337	3812	6	48	46	28685	16188	13160	13100	4000	8000	29415	29405	29348	29382	29387

Count: 8

Code:

  st4 { v0.8h, v1.8h, v2.8h, v3.8h }, [x6]
  st4 { v0.8h, v1.8h, v2.8h, v3.8h }, [x6]
  st4 { v0.8h, v1.8h, v2.8h, v3.8h }, [x6]
  st4 { v0.8h, v1.8h, v2.8h, v3.8h }, [x6]
  st4 { v0.8h, v1.8h, v2.8h, v3.8h }, [x6]
  st4 { v0.8h, v1.8h, v2.8h, v3.8h }, [x6]
  st4 { v0.8h, v1.8h, v2.8h, v3.8h }, [x6]
  st4 { v0.8h, v1.8h, v2.8h, v3.8h }, [x6]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 2.4976

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	1f	22	23	24	37	3f	46	49	4c	4e	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	61	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd store (99)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	c2	branch cond mispred nonspec (c5)	cf	d0	d2	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
960209	202311	1620	0	0	1	1	0	0	450	794	0	0	1	82635	212382	16	16	4	1389	22342	2861	1076849	104	749997	321320	100	640000	324879	500	9391947	10813227	1	0	203158	0	201200	201063	39521	3	37980	960100	200	320000	640000	200	640000	1600000	201005	198534	1	1	80201	100	99	100	100	80000	80000	100	320000	0	0	25481	0	320002	0	0	2	320002	2	34	0	0	5109	0	2	16	17	15	13	198556	0	320000	640000	100	200185	199423	201385	200591	199353
960204	198919	1489	0	0	0	0	0	0	0	0	0	0	0	87686	201482	0	16	0	1517	16736	35	1053779	100	722129	320060	100	640000	320000	500	9220826	10709959	0	0	200820	0	199743	199668	38152	3	36860	960100	200	320000	640000	200	640000	1600000	201198	199319	1	1	80201	100	99	100	100	80000	80000	100	320000	0	42	24932	0	320002	0	0	0	320002	2	42	0	0	5109	0	0	13	17	12	13	197604	0	320000	640000	100	197816	196912	201639	200469	199417
960204	202143	1545	0	0	0	0	0	0	0	3	0	0	0	84164	201771	16	16	0	1392	17419	51	1042021	100	726071	320000	100	640000	320000	500	9343439	10751125	1	0	200077	0	198658	199993	39006	3	41185	960100	200	320000	640000	200	640000	1600000	200926	199256	1	1	80201	100	99	100	100	80000	80000	100	320000	0	42	25051	0	320002	1	0	182	320002	2	44	0	0	5109	0	0	10	17	13	13	200591	0	320000	640000	100	198975	199260	199314	200610	200932
960204	201578	1543	1	0	0	0	0	0	0	0	0	0	0	84676	197876	0	0	0	1554	16591	25	1044518	100	727401	320060	100	640000	320000	500	9319117	10695063	0	0	200137	0	200481	200650	41114	3	40428	960100	200	320000	640000	200	640000	1600600	201734	197562	1	1	80201	100	99	100	100	80000	80000	100	320000	0	0	26018	0	320002	0	0	2	320002	0	0	0	0	5110	0	0	6	17	13	13	199030	0	320000	640000	100	201425	202081	199118	201823	199145
960204	200987	1540	0	0	0	0	0	0	12	3	0	0	0	87903	199877	16	16	0	1500	17072	25	1047553	100	723741	320000	100	640238	320000	500	9265653	10817405	1	0	200918	0	197975	200752	41298	3	40715	960100	200	320000	640000	200	640512	1600000	198379	201241	1	1	80201	100	99	100	100	80000	80000	100	320000	0	0	26162	0	320000	0	0	6	320002	0	0	0	0	5109	0	0	18	17	13	14	201196	0	320000	640000	100	198284	201886	200851	198483	201133
960204	197689	1555	0	0	0	0	0	0	12	0	0	0	0	84558	200587	0	16	0	1652	16958	25	1054110	100	729707	320000	100	640000	320000	500	9358630	10666685	0	0	199232	0	200955	199478	39560	3	39428	960100	200	320000	640000	200	640000	1600000	200049	200567	1	1	80201	100	99	100	100	80000	80000	100	320180	0	42	26101	0	320000	1	0	2	320002	2	42	0	0	5109	0	0	12	17	13	12	200236	0	320000	640000	100	201090	200796	198226	198379	200934
960204	200082	1567	0	0	0	0	0	0	132	3	0	0	0	84951	200256	16	16	0	1098	16141	25	1048653	100	722970	320000	100	640000	320000	500	9140874	10680543	0	0	201071	0	202088	199273	39954	3	40716	960446	200	320000	640000	200	640000	1600000	204375	209016	31	1	80201	100	99	100	100	80000	80000	100	320000	0	42	26354	0	320002	0	0	2	320002	2	0	0	0	5109	0	0	15	17	13	14	199831	0	320000	640000	100	198678	202789	199226	200860	201432
960204	198868	1561	0	0	0	0	0	0	0	3	0	0	0	84539	200406	16	0	0	1685	16277	25	1049922	100	723770	320000	100	640000	320000	500	9396733	10844931	0	0	199324	3	201375	200034	41971	3	39228	960100	200	320000	640000	200	640000	1600000	200580	202822	1	1	80201	100	99	100	100	80000	80000	100	320000	0	42	27032	0	320002	2	2	0	320002	0	42	0	0	5109	0	4	15	17	14	12	201672	0	320000	640000	100	202331	199939	200579	199032	199629
960205	199215	1553	0	0	0	0	0	1	174	3	0	0	0	88493	199746	16	16	0	1456	16797	25	1043498	100	718349	320060	100	640000	320000	500	9304454	10749102	0	0	200626	0	199841	201425	40214	3	39601	960100	200	320000	640000	200	640000	1600000	196509	198452	1	1	80201	100	99	100	100	80000	80000	100	320000	0	42	25916	0	320000	0	0	0	320002	2	0	2	0	5109	0	3	13	26	13	13	200555	0	320000	640000	100	203007	200632	201642	200070	200999
960204	201962	1552	0	0	0	0	3	5	396	440	0	0	0	83412	203960	16	16	0	1231	16708	134	1049875	100	730581	320240	100	640952	320324	500	9249985	10885828	1	0	200025	0	204720	207206	39643	45	39900	961830	200	320360	640720	200	640720	1601800	198937	199275	5	1	80201	100	99	100	100	80000	80000	100	320240	2	42	24545	0	320000	0	0	0	320002	2	42	0	0	5109	0	3	5	17	14	13	198958	0	320000	640000	100	198377	201214	200443	199703	201454

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 2.4999

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	23	37	3f	46	49	4e	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd store (99)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
960027	201000	1558	0	0	0	0	0	0	21	0	85027	199701	0	16	1163	16296	25	1042346	10	725704	320000	10	640000	320000	50	9350328	10795698	1	199531	0	200455	198594	39295	3	40190	960010	20	320000	640000	20	640000	1600000	199961	200751	1	1	80021	10	9	10	10	80000	80000	10	320014	14	36	26123	0	320016	0	0	16	320002	0	34	5019	19	17	19	20	198131	320000	640000	10	200936	199500	202368	200816	200236
960025	202825	1610	58	0	0	0	0	0	8	0	87092	198324	16	16	1539	16012	911	1041766	10	730756	320000	10	640000	320108	50	9248845	10742233	0	201535	0	202783	202087	37549	13	39046	960010	20	320000	640000	20	640000	1600000	201231	199176	1	1	80021	10	9	10	10	80000	80000	10	320000	0	34	24538	0	320002	2	0	8	320002	2	34	5019	23	17	21	16	201159	320000	640000	10	197497	201200	201281	203303	200567
960024	201096	1556	0	0	0	0	0	0	2	0	87986	199068	16	16	1295	16318	25	1043778	10	730860	320060	10	640000	320000	50	9443129	10844652	0	201805	3	199081	200798	41886	3	38527	960010	20	320120	641440	20	673100	1683325	220522	216850	137	1	80021	10	9	10	10	80000	80000	10	320014	14	44	26314	0	320016	3	0	43	320002	2	0	5019	19	17	13	19	199152	320000	640000	10	200064	200263	200130	201236	198294
960024	199230	1507	0	0	0	0	0	21	3	1	92486	200208	0	0	1375	16434	25	1050368	10	729036	320000	10	640000	320000	50	9187534	10793132	1	195479	0	197290	200890	39474	3	40271	960010	20	320000	640000	20	640000	1600000	197590	197746	1	1	80021	10	9	10	10	80000	80000	10	320000	0	42	26377	0	320000	1	2	868	320000	2	0	5055	18	17	18	18	199656	320000	640000	10	202638	197480	201909	201972	199910
960024	199124	1500	0	0	0	0	0	0	3	0	87292	199004	16	0	1341	16794	25	1042611	10	728784	320000	10	640000	320000	50	9255375	10837437	0	200120	0	199216	198037	38054	3	39301	960010	20	320000	640000	20	640000	1600000	199717	201344	1	1	80021	10	9	10	10	80000	80000	10	320000	0	42	25921	0	320000	2	0	2	320002	0	0	5019	17	17	10	19	201966	320000	640000	10	200638	198300	199507	200351	201547
960024	199994	1547	0	0	0	0	0	33	3	0	88435	199406	0	16	1380	17259	25	1042157	10	722308	320000	10	640000	320000	50	9275978	10726600	0	200593	0	198288	200187	38326	3	39469	960010	20	320000	640240	20	640000	1600000	200945	199089	1	1	80021	10	9	10	10	80000	80000	10	320000	0	42	24119	0	320002	0	0	0	320002	0	42	5019	19	17	18	17	200693	320000	640000	10	198170	202279	198523	200609	200120
960024	200823	1554	0	0	0	0	0	0	3	0	92995	202326	16	16	1338	16611	63	1038288	10	725948	320000	10	640000	320000	50	9126178	11019668	0	201263	0	201166	199016	40378	3	38620	960010	20	320000	640000	20	640000	1600000	199989	203065	30	1	80021	10	9	10	10	80000	80000	10	320000	0	0	25164	0	320002	0	0	2	320002	2	0	5019	14	17	17	17	200219	320000	640000	10	201628	200524	199884	200538	198398
960024	198986	1568	0	0	0	0	0	12	0	1	92057	200446	0	16	1647	15913	25	1052230	10	724169	320000	10	640000	320108	50	9234568	10795969	0	198814	0	200098	201517	40774	12	40648	960010	20	320000	640000	20	640000	1600000	202328	200326	1	1	80021	10	9	10	10	80000	80000	10	320000	0	0	24726	0	320060	0	0	2	320002	0	0	5033	20	17	17	18	202650	320000	640000	10	198635	202036	200049	201091	198687
960024	201157	1543	0	0	0	0	0	162	3	1	84065	199381	16	16	1358	17461	53	1050509	10	717186	320000	10	640000	320000	50	9206528	10894757	0	201910	0	201492	202722	38651	3	40479	960010	20	320000	640000	20	640000	1600000	199100	201404	1	1	80021	10	9	10	10	80000	80000	10	320000	0	42	24654	0	320000	0	0	2	320000	0	0	5019	17	17	16	19	202657	320000	640000	10	200436	201234	201164	196790	201065
960024	198966	1534	0	0	0	0	0	3	0	0	76040	199057	16	16	1409	15343	25	1045683	10	723259	320000	10	640000	320108	50	9269843	10696557	0	200456	0	200442	198777	41173	3	41703	960010	20	320000	640000	20	640240	1600000	199663	200774	1	1	80021	10	9	10	10	80000	80000	10	320000	0	42	26917	0	320062	0	0	5	320002	0	42	5031	18	17	12	17	199317	320000	640000	10	201755	198552	199028	200357	200134

ST4 (multiple, 8H)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations