Firestorm: ST4 (multiple, post-index, 16B) measurements

Code:

  st4 { v0.16b, v1.16b, v2.16b, v3.16b }, [x6], x8
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 0
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 12.000

Issues: 13.000

Integer unit issues: 1.000

Load/store unit issues: 4.000

SIMD/FP unit issues: 8.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	1f	37	3a	3f	46	49	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	5e	5f	60	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd store (99)	inst ldst (9b)	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	l1d cache miss st nonspec (c0)	c2	cf	d0	d2	l1i cache miss demand (d3)	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
72007	28915	223	1	0	0	0	0	0	0	0	0	0	4867	28575	4	0	14438	13000	1000	8000	4000	1000	8000	4000	5000	51888	71620	0	15	0	24692	28454	28587	3	10	13000	4000	8000	9000	20000	28630	28740	1	1	61001	1000	1000	4000	0	8	0	4000	0	0	0	4000	8	0	13084	9673	6919	3238	1	44	18659	3163	3804	11	38	39	28195	1000	15402	11965	12273	4000	8000	1000	28578	28632	28579	28759	28604
72004	28720	222	1	0	0	1	0	0	0	12	0	0	4695	28538	3	0	14526	13000	1000	8001	4000	1000	8000	4000	5000	51898	71596	0	19	0	24644	28499	28522	3	10	13000	4000	8000	9000	20000	28531	28574	1	1	61001	1000	1000	4000	0	0	0	4000	0	0	0	4000	0	0	13356	9416	6970	3150	0	44	18579	3205	3811	11	40	45	28252	1000	15467	12009	12378	4000	8000	1000	28543	28578	28653	28625	28560
72004	28513	221	1	0	0	1	0	0	0	12	0	1	4853	28668	0	4	14486	13000	1000	8002	4000	1000	8000	4000	5000	51902	71605	0	19	0	24631	28588	28663	3	10	13000	4000	8000	9000	20000	28602	28799	1	1	61001	1000	1000	4000	0	8	0	4000	0	4	0	4000	8	0	13328	9515	6936	3188	0	41	18600	3250	3812	10	34	36	28075	1000	15146	11964	12369	4000	8000	1000	28617	28656	28600	28607	28665
72004	28615	222	1	1	1	0	0	0	0	0	0	0	4716	28541	3	4	14334	13001	1000	8000	4000	1000	8000	4000	5000	51905	71629	0	14	0	24678	28568	28710	3	10	13000	4000	8000	9000	20000	28628	28557	1	1	61001	1000	1000	4000	0	0	0	4000	0	0	0	4000	0	0	13181	9594	7032	3226	0	39	18519	3255	3802	8	34	35	28086	1000	15525	12000	12014	4000	8000	1000	28593	28586	28615	28656	28585
72004	28747	222	2	0	0	1	0	0	0	0	0	0	4663	28583	0	0	14294	13000	1000	8000	4000	1000	8000	4000	5000	51896	71612	0	12	0	24616	28464	28609	10	10	13000	4000	8000	9000	20000	28483	28571	1	1	61001	1000	1000	4000	0	8	0	4000	0	0	0	4000	0	0	13387	9455	6980	3235	1	32	18460	3155	3805	13	35	37	28258	1000	15230	12144	12221	4000	8000	1000	28696	28680	28624	28691	28829
72004	28606	222	0	0	0	1	0	0	0	0	0	0	4814	28574	4	0	14336	13000	1000	8000	4000	1000	8000	4000	5000	51908	71616	0	14	0	24633	28667	28693	3	10	13000	4000	8000	9000	20000	28661	28692	1	1	61001	1000	1000	4000	0	8	0	4000	0	0	0	4000	0	0	13294	9556	6982	3179	1	40	18634	3192	3808	13	41	35	28136	1000	15257	12328	12325	4000	8000	1000	28636	28561	28631	28296	28655
72004	28513	222	2	0	0	1	0	0	0	0	0	0	4803	28635	4	4	14348	13000	1000	8000	4000	1000	8000	4000	5000	51906	71634	0	12	0	24638	28454	28638	9	10	13000	4000	8000	9000	20000	28447	28510	1	1	61001	1000	1000	4000	0	8	0	4000	0	0	0	4000	8	0	13156	9644	7031	3184	1	39	18755	3188	3806	10	42	42	28206	1000	15539	12173	12149	4000	8000	1000	28521	28599	28664	28666	28580
72004	28438	221	0	0	0	0	0	0	0	0	0	0	4837	28525	4	4	14280	13000	1000	8001	4000	1000	8000	4000	5000	51912	71632	0	13	0	24582	28472	28649	3	10	13000	4000	8000	9000	20000	28687	28693	1	1	61001	1000	1000	4000	0	8	0	4000	1	0	6	4000	8	0	13066	9558	7041	3203	0	39	18820	3194	3816	11	30	30	28141	1000	15339	11909	12028	4000	8000	1000	28670	28518	28542	28670	28665
72004	28607	223	1	0	0	2	0	0	0	0	0	0	4826	28517	4	4	14239	13001	1000	8000	4000	1000	8000	4000	5000	51901	71642	0	11	0	24592	28455	28751	3	10	13000	4000	8000	9000	20000	28507	28705	1	1	61001	1000	1000	4000	0	0	0	4000	0	0	0	4000	8	0	13526	9884	7026	3214	0	33	18599	3257	3811	16	37	32	28177	1000	14833	12247	12414	4000	8000	1000	28728	28738	28522	28670	28603
72004	28676	223	1	0	0	1	0	0	0	0	0	0	4892	28561	0	4	14384	13000	1000	8000	4000	1000	8000	4000	5000	51906	71660	0	14	0	24626	28499	28629	3	10	13000	4000	8000	9000	20000	28404	28513	1	1	61001	1000	1000	4000	0	0	0	4000	0	0	0	4000	8	0	13303	9714	7062	3181	0	38	18492	3233	3817	8	36	29	28175	1000	15536	12166	12021	4000	8000	1000	28503	28620	28725	28557	28664

Count: 8

Code:

  st4 { v0.16b, v1.16b, v2.16b, v3.16b }, [x6], x8
  st4 { v0.16b, v1.16b, v2.16b, v3.16b }, [x6], x8
  st4 { v0.16b, v1.16b, v2.16b, v3.16b }, [x6], x8
  st4 { v0.16b, v1.16b, v2.16b, v3.16b }, [x6], x8
  st4 { v0.16b, v1.16b, v2.16b, v3.16b }, [x6], x8
  st4 { v0.16b, v1.16b, v2.16b, v3.16b }, [x6], x8
  st4 { v0.16b, v1.16b, v2.16b, v3.16b }, [x6], x8
  st4 { v0.16b, v1.16b, v2.16b, v3.16b }, [x6], x8

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 2.5033

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	1f	22	23	37	3a	3f	46	49	4e	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	67	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd store (99)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	c2	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
960207	200388	1547	0	0	0	0	0	15	0	2	0	0	85046	1	200681	0	16	1386	16592	25	1127216	80100	724053	320000	80100	640000	320000	400500	9385083	10807496	0	0	200530	0	198313	198535	43113	3	38251	1040100	200	320000	640000	200	720000	1600000	198750	201048	2	1	80201	100	99	100	100	80000	80000	100	320060	0	34	25893	0	320002	1	0	3	321742	0	34	0	0	5111	2	16	2	2	199575	80000	0	320000	640000	80100	200444	201531	200063	200755	198059
960204	200336	1546	1	0	0	0	1	0	0	2	0	0	87576	1	198743	16	16	1438	16361	25	1125697	80100	723252	320000	80100	640238	320000	400500	9352736	10696243	0	0	201449	0	200094	199181	37620	14	39746	1040100	200	320000	640000	200	720270	1600000	200028	200106	1	1	80201	100	99	100	100	80000	80000	100	320000	0	34	25043	0	320002	2	2	2	320002	2	34	0	0	5111	2	16	1	2	199440	80000	0	320000	640000	80100	200440	198940	201881	200072	197460
960204	201072	1545	0	0	0	0	0	0	0	2	0	0	88724	0	201498	16	16	1648	16869	25	1125595	80100	719882	320000	80100	640000	320000	400500	9246565	10817056	0	0	199001	0	200015	198927	40549	3	42170	1040100	200	320000	640000	200	720000	1600000	201089	201660	1	1	80201	100	99	100	100	80000	80000	100	320000	0	34	25818	0	320000	0	0	0	320002	2	34	0	0	5111	1	17	1	1	202487	80000	0	320000	640000	80100	198858	201565	202049	200104	200881
960204	200344	1563	0	1	0	0	0	0	150	2	0	0	89251	0	201916	16	16	1383	16332	25	1129825	80100	728799	320120	80100	640000	320000	400500	9314040	10871094	0	0	201672	0	198307	200254	40758	3	40825	1040100	200	320000	640000	200	720000	1600000	199663	201697	1	1	80201	100	99	100	100	80000	80000	100	320000	0	0	25315	0	320002	1	0	5	320002	2	34	0	0	5110	2	17	2	5	198719	80031	1	320000	640000	80100	200117	199800	198739	203134	198222
960204	200770	1563	0	0	0	0	0	0	0	2	0	0	93957	0	199264	16	16	1807	16558	25	1128555	80100	726460	320060	80100	640000	320000	400500	9247163	10727989	0	0	199093	0	199815	198202	37716	3	41134	1040100	200	320120	641200	200	720000	1600000	202312	200798	1	1	80201	100	99	100	100	80000	80000	100	320000	0	34	25208	0	320062	0	0	8	320002	2	34	0	0	5109	1	16	1	2	198616	80000	0	320000	640000	80100	202089	197419	200491	200438	200092
960204	215666	1550	0	0	1	0	0	0	12	2	0	0	91627	1	199655	16	16	1576	17320	25	1128146	80100	725270	320000	80100	640000	320000	400500	9302557	10895378	0	0	198200	0	199854	214185	41946	3	38709	1040100	200	320000	640000	200	720000	1600000	199452	197574	1	1	80201	100	99	100	100	80000	80000	100	320000	0	34	25758	0	320002	1	0	0	320004	2	34	0	0	5111	2	17	1	2	201603	80000	0	320000	640000	80100	200647	199654	201096	199646	200785
960204	202202	1556	1	0	0	0	0	0	12	0	0	0	86148	1	203790	16	0	1251	16832	25	1123965	80101	725910	320000	80100	640000	320000	400500	9277036	10782610	0	0	200571	0	198937	199493	40257	3	39617	1040100	200	320000	640000	200	720000	1600000	197877	201365	1	1	80201	100	99	100	100	80000	80000	100	320000	0	34	26138	0	320002	0	0	2	320002	2	34	2	0	5259	1	53	3	3	199775	80116	0	320000	640000	80100	197361	198947	199972	201425	201033
960204	201293	1571	1	1	1	0	16	2	528	442	0	0	85056	0	198912	16	0	1476	17601	36	1125578	80100	725107	320000	80100	640000	320000	400500	9340372	10857612	0	0	200686	3	201956	200825	40864	3	36761	1040100	200	320000	640000	200	720000	1600000	200613	199066	1	1	80201	100	99	100	100	80000	80000	100	320000	0	34	24799	0	320002	0	0	2	320002	2	34	0	0	5109	1	16	2	1	199197	80000	0	320000	640000	80100	198173	201005	199211	198696	199578
960205	201947	1553	0	0	0	0	0	0	12	2	0	0	83071	0	201439	16	16	1272	17041	25	1126839	80101	725338	320000	80100	640000	320000	400509	9361676	10731079	0	1	202143	0	202104	200325	37540	3	40611	1040100	200	320000	640000	200	720000	1600000	200144	198969	1	1	80201	100	99	100	100	80000	80000	100	320000	0	34	24791	0	320000	1	0	2	320000	2	34	0	0	5109	1	17	2	1	199246	80000	0	320000	640000	80100	201066	200761	199457	201440	200752
960204	202182	1559	1	0	1	0	0	0	3	2	1	0	91061	0	198726	16	0	1372	16672	25	1127283	80100	724459	320000	80100	640000	320000	400500	9401405	10811594	0	2	199641	0	201141	199066	37188	3	40714	1040100	200	320120	640000	200	720000	1600000	200320	201545	1	1	80201	100	99	100	100	80000	80000	100	320000	0	34	24567	0	320002	0	0	5	320002	2	0	0	0	5111	1	17	1	2	200533	80001	0	320000	640000	80100	200024	200734	200440	201931	200458

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 2.4970

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	22	23	37	3a	3f	46	49	4e	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	5f	60	67	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd store (99)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	d9	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
960027	201072	1571	0	0	0	0	0	0	1056	3	1	0	81696	1	196746	16	16	1435	16307	25	1123764	80010	724124	320000	80010	640000	320108	400050	9288912	10780233	0	0	0	198943	0	201842	200517	40211	3	40128	1040010	20	320000	640000	20	720000	1600600	199531	200837	1	1	80021	10	9	10	10	80000	80000	10	320000	0	42	26707	0	320002	2	16	5	320002	16	43	14	0	0	5039	10	16	0	12	7	197198	80000	320000	640000	80010	202728	198907	199253	198678	199481
960024	197706	1544	0	0	0	0	0	1	609	3	0	0	81511	0	201526	0	16	1263	16380	25	1125909	80010	727175	320060	80010	640000	320000	400050	9332020	10821895	0	0	0	198149	0	199158	200410	38199	3	39059	1040010	20	320000	640000	20	720000	1600000	199920	199887	1	1	80022	10	9	10	10	80000	80000	10	320000	0	42	24965	0	320000	0	0	5	320062	2	42	0	0	0	5227	12	17	0	12	10	198739	80000	320000	640000	80010	199947	199787	200116	196316	199707
960024	199539	1561	1	0	1	1	0	0	429	0	0	0	89067	0	202611	16	16	1564	16761	25	1119815	80039	727702	320000	80010	640000	320000	400055	9163439	10878413	0	0	0	202858	0	200542	199844	56869	3	38661	1040010	20	320000	640000	20	720000	1600655	200028	200325	2	1	80022	10	9	10	10	80000	80000	10	320000	0	42	25719	0	320002	1	0	2	320000	2	42	0	0	0	5019	6	17	0	10	7	199282	80000	320000	640000	80010	196802	202234	201626	200379	199636
960024	198603	1535	0	0	0	0	0	0	546	3	0	0	84610	0	199978	16	0	1187	16715	25	1121067	80010	725913	320000	80010	640000	320000	400050	9322926	10673153	0	0	0	200122	0	200531	200452	39041	3	40858	1040010	20	320000	640000	20	720000	1600000	201661	199722	1	1	80021	10	9	10	10	80000	80000	10	320000	0	42	26239	0	320002	0	0	2	320002	0	42	0	0	0	5019	12	16	0	12	12	215567	80000	320000	640000	80010	203456	200816	198198	197350	201484
960024	201733	1554	0	0	0	0	0	0	444	3	0	0	89830	0	199658	16	0	1509	17003	25	1129920	80010	723073	320000	80010	640000	320000	400050	9241153	10929331	0	0	1	198600	0	200918	199791	38066	34	40581	1041510	20	320480	640720	20	720540	1601800	198561	199352	4	1	80021	10	9	10	10	80000	80000	10	320240	0	0	26808	2	320242	0	0	4612	320242	2	42	0	0	0	5066	10	53	0	7	14	200308	80058	320000	640000	80010	199418	207336	198138	199956	199918
960024	198568	1553	0	0	0	0	0	0	69	3	0	0	90719	0	200091	16	16	1376	17100	25	1131665	80011	730215	320000	80010	640000	320000	400050	9259471	10650718	0	0	1	200663	0	201130	200049	39691	3	41093	1040010	20	320000	640000	20	720000	1600000	199031	199490	1	1	80021	10	9	10	10	80000	80000	10	320000	0	42	26497	0	320002	0	0	5	320002	2	46	0	0	0	5019	6	17	0	12	12	199747	80000	320000	640000	80010	197689	199361	201798	200617	200103
960024	198578	1536	0	0	0	0	0	0	0	3	0	0	84814	0	201169	16	16	1453	17406	25	1125167	80010	730562	320000	80010	640000	320116	400050	9356291	10718695	4	1	0	199701	3	200871	200201	41193	3	40938	1040010	20	320000	640000	20	720000	1600000	200993	202626	1	1	80021	10	9	10	10	80000	80000	10	320000	0	42	26029	0	320002	0	0	5	320002	2	42	0	0	0	5019	5	16	0	12	12	200495	80000	320000	640000	80010	201152	202732	197717	196649	198610
960024	201621	1554	0	0	0	0	0	0	0	3	0	0	83435	0	200395	0	16	1463	16071	25	1130208	80010	724924	320000	80010	640000	320000	400050	9296318	10907037	2	0	0	200911	0	198269	198107	39464	3	39579	1040010	20	320000	640000	20	720000	1600000	200537	200149	1	1	80021	10	9	10	10	80000	80000	10	320000	0	42	26025	0	320002	0	0	2	320000	2	42	0	0	0	5019	10	16	0	9	12	199863	80000	320000	640000	80010	198939	201736	201016	200398	199200
960024	199768	1531	0	0	0	0	0	0	24	3	0	0	80657	0	198150	16	16	1443	16383	25	1126027	80010	730058	320000	80010	640000	320000	400050	9215611	10884093	2	0	0	199154	0	200534	198837	38695	3	40604	1040010	20	320000	640000	20	720000	1600000	200622	202086	1	1	80021	10	9	10	10	80000	80000	10	320000	0	42	25869	0	320002	0	0	5	320002	2	42	0	0	0	5020	7	52	0	10	12	199275	80000	320000	640000	80010	201486	201344	199434	200183	199734
960024	200215	1556	0	0	0	0	0	0	18	3	0	0	82350	0	200406	0	16	1363	16554	25	1128884	80010	724110	320000	80010	640000	320000	400050	9213010	10710579	2	0	0	200911	0	200868	199745	42123	3	38725	1040010	20	320000	640000	20	720000	1600000	201124	199909	1	1	80021	10	9	10	10	80000	80000	10	320000	0	42	26282	0	320002	0	0	0	320002	2	42	0	0	0	5019	13	16	4	12	7	199893	80000	320000	640000	80010	200578	198676	201003	198651	199828

ST4 (multiple, post-index, 16B)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations