Firestorm: ST4 (multiple, post-index, 2D) measurements

Code:

  st4 { v0.2d, v1.2d, v2.2d, v3.2d }, [x6], x8
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 0
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 12.000

Issues: 13.000

Integer unit issues: 1.000

Load/store unit issues: 4.000

SIMD/FP unit issues: 8.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	19	1e	1f	23	37	3a	3f	46	49	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	5e	5f	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd store (99)	inst ldst (9b)	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	c9	cf	d0	d2	l1i cache miss demand (d3)	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
72007	29239	237	0	30	0	0	22	0	0	0	0	0	0	4856	28514	4	0	14430	13000	1000	8000	4000	1000	8000	4000	5000	51926	71619	0	6	24661	28574	28655	3	10	13000	4004	8000	9000	20000	28645	28786	1	1	61001	1000	1000	4000	4	8	0	4000	0	0	21	4000	4	8	4	0	0	13127	9313	6965	3176	13	53	18745	3244	3809	16	49	48	28244	1000	15575	12179	12623	4000	8000	1000	28959	28801	28718	28753	28706
72004	28821	223	0	11	0	0	15	1	0	0	0	0	0	4622	28740	0	0	14510	13000	1000	8000	4000	1000	8000	4000	5005	51909	71599	0	10	24662	28668	28901	3	10	13000	4000	8000	9000	20000	28824	28764	1	1	61001	1000	1000	4000	0	8	0	4000	0	0	0	4000	0	8	0	0	0	13023	9372	6938	3129	9	52	18840	3146	3816	20	50	50	28269	1000	15385	12494	12528	4000	8000	1000	28820	28854	28808	28763	28888
72004	28758	224	0	17	0	0	20	0	0	0	0	0	0	4748	28690	0	4	14813	13001	1000	8000	4000	1000	8000	4000	5000	51938	71618	0	7	24610	28871	28945	3	10	13000	4000	8000	9000	20000	29145	29029	1	1	61001	1000	1000	4000	0	8	3	4020	4	4	3	4000	0	8	0	0	0	13161	9453	6728	3014	6	53	19247	3258	3808	15	49	54	28645	1001	15869	12273	12328	4000	8000	1000	29818	29755	29799	28950	28821
72004	28827	239	0	14	1	0	17	0	0	0	0	0	0	4513	29368	4	0	14434	13000	1000	8000	4000	1000	8008	4000	5000	51898	71614	0	4	24635	28527	28699	10	10	13000	4000	8008	9000	20000	28797	28728	1	1	61001	1000	1000	4000	0	4	0	4000	0	0	0	4000	0	4	0	0	0	13109	9418	6901	3158	8	51	18863	3102	3807	14	45	54	28329	1000	15487	12258	12313	4000	8000	1000	28828	28807	28861	28713	28737
72004	28762	222	0	17	0	0	21	0	0	0	0	0	0	4807	28653	4	0	14465	13001	1000	8000	4000	1000	8000	4004	5000	51908	71614	0	10	24593	28775	28716	3	10	13000	4004	8000	9000	20000	28738	28771	1	1	61001	1000	1000	4000	0	8	0	4000	0	0	0	4000	0	0	0	0	0	13132	9409	6998	3170	9	48	18490	3183	3805	12	47	43	28231	1000	15020	11910	11828	4000	8000	1000	28715	28761	28689	28425	28657
72004	28551	221	0	22	0	0	25	0	0	0	0	0	0	4878	28553	0	3	14209	13000	1000	8000	4000	1000	8000	4000	5000	51908	71597	1	5	24639	28699	28760	3	10	13000	4000	8000	9000	20000	28787	28710	1	1	61001	1000	1000	4000	0	0	0	4000	52	0	12	4000	0	0	0	0	0	13704	9369	6951	3129	13	47	18624	3236	3816	16	53	56	28171	1000	14996	11873	11981	4000	8000	1000	28580	28473	28759	28694	28691
72004	28794	223	0	17	0	0	16	0	0	0	1	0	1	4722	28681	4	0	14272	13000	1000	8001	4000	1000	8000	4000	5000	51909	71618	0	17	24664	28428	28707	3	10	13000	4000	8000	9000	20000	28546	28693	1	1	61001	1000	1000	4000	0	8	0	4000	2	0	0	4000	0	4	0	0	0	13270	9582	7042	3117	10	48	18654	3271	3817	13	55	52	28273	1000	15297	12036	12055	4000	8000	1000	28827	28635	28693	28545	28383
72004	28630	222	0	19	0	0	21	0	0	0	0	0	1	4745	28661	4	4	14381	13000	1000	8000	4000	1000	8000	4000	5000	51897	71638	0	15	24632	28456	28654	3	10	13000	4000	8000	9000	20000	28543	28392	1	1	61001	1000	1000	4000	0	8	0	4000	0	0	0	4000	0	0	0	0	0	13045	9351	6850	3078	7	55	19218	3100	3814	14	63	65	28393	1000	16227	12723	12765	4000	8000	1000	29431	29191	29268	29339	29179
72004	29285	228	0	16	0	0	18	0	0	0	0	0	0	4687	29290	0	0	15003	13000	1000	8000	4000	1000	8000	4000	5000	51886	71610	0	12	24653	29053	29219	3	10	13000	4000	8000	9000	20000	29282	29285	1	1	61001	1000	1000	4000	0	4	0	4001	0	0	0	4001	0	12	0	0	0	12982	9233	6967	3101	7	50	19456	3207	3808	14	57	60	28548	1000	16143	12874	12804	4000	8000	1000	29351	29505	29471	29409	29349
72004	29346	228	0	19	0	0	18	0	0	0	1	0	0	4687	29294	0	4	15124	13000	1000	8000	4004	1000	8000	4000	5000	51899	71614	0	11	24723	29473	29357	10	10	13000	4000	8000	9000	20000	29349	29374	1	1	61001	1000	1000	4000	2	0	0	4000	0	0	1785	4000	0	0	0	0	165	13172	9489	6938	3087	11	53	19591	3363	3808	16	54	59	29141	1000	14404	12026	11374	4000	8000	1000	28100	28356	28232	28471	28308

Count: 8

Code:

  st4 { v0.2d, v1.2d, v2.2d, v3.2d }, [x6], x8
  st4 { v0.2d, v1.2d, v2.2d, v3.2d }, [x6], x8
  st4 { v0.2d, v1.2d, v2.2d, v3.2d }, [x6], x8
  st4 { v0.2d, v1.2d, v2.2d, v3.2d }, [x6], x8
  st4 { v0.2d, v1.2d, v2.2d, v3.2d }, [x6], x8
  st4 { v0.2d, v1.2d, v2.2d, v3.2d }, [x6], x8
  st4 { v0.2d, v1.2d, v2.2d, v3.2d }, [x6], x8
  st4 { v0.2d, v1.2d, v2.2d, v3.2d }, [x6], x8

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 2.4980

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	22	23	37	3a	3f	46	49	4e	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	67	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	7b	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	91	inst branch cond (94)	inst int alu (97)	inst simd store (99)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	branch cond mispred nonspec (c5)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
960207	201787	1548	1	0	1	0	0	0	15	17	0	0	84067	0	199620	16	0	1381	15981	25	1130374	80100	725985	320000	80100	640000	320000	400508	9267554	10822346	0	201365	199369	200138	40395	3	40621	1040100	0	200	320000	640000	200	720000	1600000	200606	199931	1	1	80201	100	99	0	100	100	80000	80000	100	320014	15	44	25212	0	320016	0	1	18	320002	16	44	14	0	0	0	5109	1	16	1	1	201848	80000	320000	640000	80100	198465	201895	196894	200310	200358
960204	198164	1560	1	1	2	1	0	0	0	19	0	0	81426	1	199131	16	16	1473	15928	25	1126481	80101	725506	320000	80100	640000	320000	400500	9395670	10776795	0	199904	200513	201750	39449	3	39900	1040475	0	200	320000	640000	200	720000	1600000	200671	198727	1	1	80201	100	99	0	100	100	80000	80000	100	320014	14	44	26316	1	320002	0	0	999	320002	16	44	14	1	0	0	5109	1	16	1	1	198026	80029	320000	640000	80100	199570	200424	197608	199253	199741
960204	200619	1550	1	2	0	0	0	0	12	18	0	0	87667	1	200357	16	16	1429	17602	25	1129495	80100	729367	320000	80100	640000	320000	400645	9283979	10819404	0	200830	200639	201726	41144	3	41117	1040475	0	200	320000	640000	200	720000	1600000	200783	199134	1	1	80201	100	99	0	100	100	80000	80000	100	320075	14	44	25622	1	320002	0	0	21	320002	16	44	14	2	0	0	5109	1	16	1	1	199322	80001	320000	640000	80100	200263	200415	201611	199062	201486
960204	198678	1613	1	0	0	0	0	0	9	17	0	0	81494	0	200261	16	0	1433	16701	25	1127257	80100	726844	320000	80100	640238	320000	400500	9240539	10884959	0	198929	199505	199393	41080	3	38545	1040100	0	200	320240	640000	200	720000	1600000	197131	196904	2	1	80201	100	99	0	100	100	80000	80000	100	320015	0	0	24674	1	320076	1	1	16	320002	16	44	14	2	0	0	5122	1	16	1	1	199531	80000	320000	640000	80100	199964	214943	200059	197735	200065
960204	199422	1588	1	1	0	0	53	1	0	19	0	0	90349	1	200089	15	16	1217	17497	25	1128342	80102	720689	320060	80100	640000	320000	400500	9168734	10777733	0	200326	197899	196679	40397	3	38962	1040100	0	200	320120	640000	200	720000	1600000	197591	198304	1	1	80201	100	99	0	100	100	80000	80000	100	320015	15	44	25984	0	320016	2	0	2	320062	14	44	14	1	0	0	5110	1	17	1	1	199358	80000	320000	640000	80100	198838	199998	197907	201626	201445
960204	199493	1620	1	0	1	0	0	0	144	18	0	0	86370	1	201256	16	16	1358	17094	25	1129068	80101	725304	320000	80100	640000	320000	400500	9300337	10641629	1	199169	200111	200936	43344	3	38913	1040475	0	200	320000	640000	200	720000	1600000	199430	199301	1	1	80201	100	99	0	100	100	80000	80000	100	320080	14	44	25386	1	320016	0	0	16	320002	16	44	14	0	1	0	5109	1	16	1	1	199681	80000	320000	640000	80100	197741	201650	201437	199462	199741
960204	201734	1617	1	0	1	0	0	1	0	17	0	0	90668	1	200605	16	16	1559	17060	25	1127241	80100	726200	320060	80133	640000	320000	400500	9307383	10736025	0	200251	200569	198629	39612	3	40243	1040100	0	200	320120	640000	200	720000	1600000	199341	199752	1	1	80201	100	99	0	100	100	80000	80000	100	320015	14	42	25432	0	320136	5	0	1176	321622	16	43	14	9	0	0	5143	1	43	1	1	201657	80116	320000	640000	80100	199626	200370	197728	198193	201487
960204	203931	1620	1	0	2	2	4	4	528	369	0	0	81727	0	199216	16	16	1326	16804	25	1122140	80100	720701	320000	80100	640000	320000	400500	9271978	10770323	1	200101	213503	200363	38344	3	40550	1040100	0	200	320000	640000	200	720000	1600000	199251	198945	1	1	80201	100	99	0	100	100	80000	80000	100	320014	15	44	24196	0	320016	0	1	5	320002	16	46	14	0	0	0	5109	1	17	1	1	202236	80000	320000	640000	80100	199733	201697	200300	199134	201382
960204	200399	1603	1	1	0	1	0	0	0	17	0	1	84418	1	197870	0	0	1599	15832	25	1119469	80100	725797	320000	80100	640000	320000	400500	9210827	10728762	0	199797	197608	198961	39687	3	37390	1040100	0	200	320000	640000	200	720000	1600000	201890	199157	1	1	80201	100	99	0	100	100	80000	80000	100	320014	15	43	24971	1	320002	0	0	16	320002	16	44	14	1	0	0	5109	1	16	1	1	200274	80000	320000	640000	80100	199962	200530	201787	200053	201133
960204	199536	1608	1	0	0	1	0	0	0	18	0	0	87410	1	198750	16	16	1328	16317	25	1133706	80100	727005	320000	80100	640000	320000	400500	9305089	10748711	0	200131	200297	201459	38063	3	40435	1040100	0	200	320000	640000	200	720000	1600000	200516	199767	1	1	80201	100	99	0	100	100	80000	80000	100	320000	14	44	23752	0	320016	0	1	18	320002	16	44	14	0	0	0	5109	1	17	1	1	201104	80001	320000	640000	80100	200939	199832	199087	198110	199961

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 2.4994

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	22	23	24	37	3a	3f	46	49	4e	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	67	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd store (99)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	branch cond mispred nonspec (c5)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
960027	199563	1499	0	0	0	0	0	0	0	2	0	0	0	85475	0	199370	16	16	1548	16300	25	1128309	80011	723767	320000	80010	640000	320000	400050	9164465	10735576	0	203734	0	199378	198674	37954	224	42706	1040010	20	320120	640000	20	720000	1600000	200510	200863	1	1	80021	10	9	10	10	80000	80000	10	320000	0	0	26874	0	320002	0	0	2	320002	2	42	0	0	0	5019	6	17	6	4	196634	80001	320000	640000	80010	201098	198845	199358	198090	198248
960024	199341	1497	0	0	0	0	1	0	1083	8	0	0	1	81422	0	201382	0	16	1297	15727	25	1128975	80011	724344	320000	80010	640000	320000	400050	9391411	10650670	0	198391	0	201781	200308	41579	3	39660	1040010	20	320240	640000	20	720270	1600000	199240	197798	1	1	80021	10	9	10	10	80000	80000	10	320060	0	34	25199	0	320004	2	0	3614	320002	2	34	0	0	0	5020	5	16	6	6	199034	80000	320000	640000	80010	200906	200000	198430	198757	200764
960024	200875	1578	0	1	1	0	0	0	21	19	0	0	1	87589	1	200388	16	16	1493	16579	25	1130905	80010	730086	320000	80010	640000	320108	400050	9239643	10824410	0	201281	0	201199	201104	40519	3	40155	1040010	20	320000	640000	20	720000	1600000	200525	200054	1	1	80021	10	9	10	10	80000	80000	10	320014	15	44	25507	1	320076	0	0	32	320002	16	44	14	0	0	5019	5	16	7	6	200535	80000	320000	640000	80010	199560	198009	200403	202665	200055
960024	201684	1594	1	0	0	1	0	0	132	14	0	1	0	82208	1	199307	16	16	1533	17161	52	1123511	80010	728248	320000	80010	640000	320000	400050	9423936	10763686	1	201943	0	200040	200271	40742	3	40793	1040010	20	320000	640000	20	720000	1600000	202164	198836	2	1	80021	10	9	10	10	80000	80000	10	320014	16	0	25678	1	320016	0	0	1058	320002	16	42	14	0	0	5019	4	16	4	4	199565	80001	320000	640000	80010	201417	199651	199690	201349	201078
960024	199300	1562	1	0	1	0	0	0	0	14	0	0	0	80572	1	199355	16	16	1285	17067	25	1123923	80010	722618	320000	80010	640000	320113	400050	9275029	10695413	1	199140	0	201345	200250	39665	3	38766	1040385	20	320000	640000	20	720000	1600000	199996	202675	2	1	80021	10	9	10	10	80000	80000	10	320015	14	44	25382	0	320016	0	0	14	320000	14	0	14	1	0	5019	5	17	6	6	201687	80000	320000	640000	80010	200250	201430	199801	199871	200310
960024	198592	1530	1	0	1	1	0	0	0	17	0	0	0	84618	1	201545	15	16	1379	16003	25	1119170	80010	730940	320000	80010	640000	320000	400195	9361588	10784074	0	199819	0	201811	203504	40785	3	41008	1040010	20	320000	640000	20	720000	1600600	202943	197324	1	1	80021	10	9	10	10	80000	80000	10	320074	14	43	25083	0	320016	1	0	20	320002	16	46	14	0	0	5019	6	17	6	5	199622	80000	320000	640000	80010	201082	202724	199603	199192	202113
960024	196977	1543	1	0	1	0	0	0	0	14	0	0	0	86113	1	200747	0	16	1514	16170	25	1128906	80010	725953	320000	80010	640000	320108	400050	9355370	10717574	0	199788	0	201024	200839	38896	3	38077	1040010	20	320000	640000	20	720270	1600000	200817	200588	1	1	80021	10	9	10	10	80000	80000	10	320015	15	0	25049	0	320016	0	1	17	320002	20	44	14	1	0	5019	4	17	4	4	200750	80000	320000	640000	80010	200904	200963	199814	200596	199161
960024	199629	1556	1	0	0	1	0	1	12	18	0	0	0	87057	1	200186	16	16	1477	15433	25	1126340	80010	728599	320060	80010	640000	320000	400050	9270704	10804129	0	200394	0	198575	200194	38724	3	41115	1040010	20	320120	640000	20	720000	1600000	199105	201847	1	1	80021	10	9	10	10	80000	80000	10	320015	15	0	26451	2	320016	0	2	16	320002	16	44	14	0	0	5019	4	16	5	5	200219	80001	320000	640000	80010	200538	199337	200622	199241	202036
960024	199515	1555	1	0	0	2	0	0	0	107	0	0	0	95146	1	201263	16	16	1286	16697	25	1126602	80011	726705	320000	80010	640000	320000	400050	9265545	10797077	1	201532	0	199387	198681	39749	3	41975	1040010	20	320000	640000	20	720000	1600000	200641	200543	2	1	80021	10	9	10	10	80000	80000	10	320194	14	44	27882	0	320196	0	0	2944	320180	14	44	14	8	0	5055	5	35	4	5	198698	81247	320000	640000	80010	199778	199329	199599	201569	200154
960024	199357	1560	1	0	0	0	3	3	396	369	0	0	0	88949	1	200619	16	16	1525	17887	25	1121519	80010	725485	320000	80010	640000	320000	400050	9300373	10721305	0	201049	0	200652	201559	38201	3	41073	1040010	20	320000	640000	20	720000	1600000	199423	198132	1	1	80021	10	9	10	10	80000	80000	10	320014	16	44	25781	1	320016	0	1	16	320002	20	46	14	0	0	5019	6	17	5	6	200938	80000	320000	640000	80010	198007	202233	200265	201637	200248

ST4 (multiple, post-index, 2D)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations