Firestorm: ST4 (multiple, post-index, 2S) measurements

Code:

  st4 { v0.2s, v1.2s, v2.2s, v3.2s }, [x6], x8
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 0
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 6.000

Issues: 7.000

Integer unit issues: 1.000

Load/store unit issues: 2.000

SIMD/FP unit issues: 4.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	1f	22	24	3a	3f	46	49	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	5f	69	6b	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	91	inst simd store (99)	inst ldst (9b)	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	c9	cf	d0	d2	l1i cache miss demand (d3)	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
66007	28818	224	0	26	0	0	21	0	0	0	0	0	0	0	4835	28441	2	2	15248	7000	1000	4000	2000	1000	4000	2000	5000	25601	35803	11	23762	0	28589	28673	3	10	7000	2000	4000	5000	10000	28461	28688	1	1	61001	0	1000	1000	2000	0	5	0	2000	0	0	1	2000	2	0	0	0	0	13161	9475	7036	3226	4	59	19481	3193	3810	12	52	51	28134	1000	15309	12414	12818	2000	4000	1000	28484	28539	28518	28761	28647
66004	28697	222	0	18	0	0	21	0	0	0	243	0	0	0	4902	28610	1	2	15282	7000	1000	4000	2000	1000	4000	2000	5000	25621	35810	10	23802	0	28487	28573	3	10	7000	2000	4000	5000	10000	28588	28586	1	1	61001	0	1000	1000	2002	4	6	2	2002	0	0	2	2000	2	0	2	1	0	13350	9899	6988	3160	6	51	19390	3229	3804	16	51	51	28146	1000	15214	12515	12691	2000	4000	1000	28612	28527	28619	28506	28639
66004	28590	222	1	18	0	0	17	0	0	0	12	0	0	0	4876	28572	2	2	15199	7000	1000	4000	2000	1000	4000	2000	5000	25652	35809	13	23833	0	28630	28629	3	10	7000	2000	4000	5000	10000	28577	28602	1	1	61001	0	1000	1000	2000	0	5	0	2001	0	0	1	2000	1	0	2	2	149	13404	9541	7010	3300	7	60	19410	3186	3807	14	55	52	28159	1000	15414	12358	12448	2000	4000	1000	28548	28488	28480	28563	28617
66004	28638	222	1	15	1	1	18	1	0	0	0	3	0	0	4984	28517	0	0	15395	7000	1000	4000	2000	1000	4000	2000	5000	25621	35804	13	23747	0	28467	28690	3	10	7000	2000	4000	5000	10000	28550	28688	1	1	61001	0	1000	1000	2000	0	0	0	2001	0	0	0	2000	1	5	0	0	0	13340	9669	6985	3213	6	56	19482	3181	3806	13	49	48	28151	1000	14985	12432	12624	2000	4000	1000	28682	28611	28536	28571	28720
66004	28622	222	0	22	0	0	21	0	0	0	12	3	0	0	4721	28641	2	0	15474	7000	1000	4000	2000	1000	4000	2000	5000	25608	35802	13	23817	0	28531	28725	3	10	7000	2000	4000	5000	10000	28586	28641	1	1	61001	0	1000	1000	2004	3	6	1	2002	0	1	2	2001	2	4	0	0	0	13440	9593	7016	3272	7	57	19512	3192	3808	15	54	54	28233	1000	15301	12665	12772	2000	4000	1000	28628	28631	28546	28636	28642
66004	28625	222	0	13	0	0	24	0	0	0	12	0	0	0	4772	28649	0	0	15237	7000	1000	4000	2000	1000	4000	2000	5000	25619	35801	13	23842	0	28536	28590	3	10	7000	2000	4000	5000	10000	28693	28611	1	1	61001	0	1000	1000	2003	3	4	2	2003	0	0	5	2000	2	6	2	1	0	13403	9511	6990	3260	5	51	19483	3149	3804	19	48	51	28172	1000	15336	12648	12743	2000	4000	1000	28607	28621	28600	28632	28597
66004	28717	223	1	23	0	1	14	1	0	0	6	0	0	0	4696	28675	0	1	15365	7000	1000	4000	2000	1000	4000	2000	5000	25619	35810	10	23794	0	28533	28735	3	10	7000	2000	4000	5000	10000	28672	28694	1	1	61001	0	1000	1000	2000	0	5	0	2000	0	0	1	2001	0	4	2	2	0	13165	9693	6925	3219	3	50	19372	3253	3802	14	48	53	28048	1000	15324	12503	12801	2000	4000	1000	28721	28677	28830	28744	28685
66004	28685	222	1	15	0	0	10	1	0	0	39	3	0	0	4900	28660	2	2	15449	7000	1000	4000	2000	1000	4000	2000	5000	25614	35821	5	23776	0	28489	28655	3	10	7000	2000	4000	5000	10000	28683	28608	1	1	61001	0	1000	1000	2000	0	5	0	2000	2	0	0	2000	0	5	0	0	0	13186	9547	6945	3200	7	43	19362	3260	3810	10	54	53	28156	1000	15428	12418	12791	2000	4000	1000	28833	28608	28619	28544	28657
66004	28555	222	0	17	0	0	19	0	0	0	6	1	0	0	4886	29570	1	0	15237	7000	1000	4000	2000	1000	4000	2000	5000	25606	35811	12	23762	0	28583	28624	3	10	7000	2000	4000	5000	10000	28688	28373	1	1	61001	0	1000	1000	2003	3	6	1	2002	0	2	2	2000	2	0	2	3	0	13231	9611	7015	3224	4	52	19457	3193	3808	16	45	49	28140	1000	15191	12687	12725	2000	4000	1000	28662	28643	28718	28747	28595
66004	28507	221	1	17	1	1	23	0	0	0	0	2	0	0	4898	28604	0	0	15491	7000	1000	4000	2000	1000	4000	2000	5000	25620	35816	13	23749	0	28386	28607	3	10	7000	2000	4000	5000	10000	28535	28652	1	1	61001	0	1000	1000	2000	0	0	0	2000	1	0	0	2000	0	4	0	0	0	13386	9756	6963	3213	9	58	19430	3175	3805	16	53	51	28162	1000	15455	12610	12766	2000	4000	1000	28739	28617	28668	28653	28699

Count: 8

Code:

  st4 { v0.2s, v1.2s, v2.2s, v3.2s }, [x6], x8
  st4 { v0.2s, v1.2s, v2.2s, v3.2s }, [x6], x8
  st4 { v0.2s, v1.2s, v2.2s, v3.2s }, [x6], x8
  st4 { v0.2s, v1.2s, v2.2s, v3.2s }, [x6], x8
  st4 { v0.2s, v1.2s, v2.2s, v3.2s }, [x6], x8
  st4 { v0.2s, v1.2s, v2.2s, v3.2s }, [x6], x8
  st4 { v0.2s, v1.2s, v2.2s, v3.2s }, [x6], x8
  st4 { v0.2s, v1.2s, v2.2s, v3.2s }, [x6], x8

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.2650

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	22	23	37	3f	46	49	4e	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	67	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst simd store (99)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ab	ac	af	bc	l1d cache miss st nonspec (c0)	c2	branch cond mispred nonspec (c5)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
480207	100286	775	0	0	0	0	12	5	1	0	37420	100761	16	16	2138	6528	25	603083	80100	364342	160000	80100	320000	160000	475231	4679702	5568944	0	0	101552	0	100838	99994	21025	3	20878	560100	200	160000	320000	200	400000	800000	102396	102022	1	1	80201	100	99	100	100	0	80000	80000	100	160000	2	32	11169	0	160002	0	0	7	0	160002	2	32	0	0	0	5110	1	17	1	1	100459	80000	160000	320000	80100	101839	100909	101103	101240	101032
480204	101942	790	0	0	0	0	0	2	0	0	41071	99967	16	16	2222	6528	25	602489	80100	360019	160000	80100	320000	160108	476007	4672761	5780815	0	0	100947	0	100922	100816	19817	3	20599	560100	200	160000	320000	200	400000	800000	103229	99784	1	1	80201	100	99	100	100	0	80000	80000	100	160000	0	0	10694	0	160062	0	0	0	2	160002	0	32	0	0	0	5122	1	17	1	1	102118	80000	160000	320000	80100	102045	100429	101087	100637	102376
480204	101825	788	0	1	0	0	0	2	0	0	38819	102185	16	16	2212	6445	25	599726	80100	360332	160000	80100	320000	160000	475697	4661463	5694575	0	0	101511	0	100431	101440	20690	3	21929	560100	200	160000	320000	200	400000	800000	99922	101944	1	1	80201	100	99	100	100	0	80000	80000	100	160000	0	32	10123	0	160002	0	2	0	5	160002	2	32	0	0	0	5109	1	17	1	1	101392	80000	160000	320000	80100	101881	99053	100917	101867	100295
480204	100131	783	0	0	0	0	0	90	1	0	42276	101121	0	16	2081	7054	25	601659	80100	362027	160000	80100	320000	160000	475858	4685062	5648432	0	1	100299	0	102551	100853	21645	3	20685	560100	200	160000	320000	200	400000	800000	101668	101506	1	1	80201	100	99	100	100	0	80000	80000	100	160000	0	32	10276	0	160000	0	0	0	2	160002	2	32	0	0	0	5110	1	17	1	1	101265	80000	160000	320000	80100	101878	99606	99756	101892	99918
480204	101963	781	0	0	0	0	0	2	0	0	40159	99975	16	16	1755	6378	25	601749	80100	361300	160000	80100	320000	160000	475474	4714111	5619408	0	0	100848	0	100137	101884	20751	3	22666	560100	200	160000	320000	200	400000	800000	101625	101150	1	1	80201	100	99	100	100	0	80000	80000	100	160000	0	32	10309	0	160002	1	0	0	2	160002	2	32	0	0	0	5109	1	17	1	1	101340	80000	160000	320000	80100	102277	100808	102036	100565	101755
480204	100362	778	0	0	0	0	0	0	0	0	41830	99688	16	0	2046	5601	25	602478	80100	363331	160000	80100	320000	160000	476073	4650627	5932376	0	0	100653	0	101150	102326	22525	3	21796	560100	200	160000	320000	200	400000	800000	102216	100594	1	1	80201	100	99	100	100	0	80000	80000	100	160000	0	32	11442	0	160002	2	0	0	3	160002	2	32	0	0	0	5109	1	16	1	1	100812	80000	160000	320000	80100	101053	102117	99842	100570	100946
480204	100977	783	0	0	0	0	12	5	0	0	37498	99945	16	16	2030	6248	25	600055	80100	356571	160000	80100	320236	160000	475934	4695502	5539998	0	0	100560	0	100094	100940	21256	3	20832	560100	200	160000	320000	200	400000	800600	102266	100291	1	1	80201	100	99	100	100	0	80000	80000	100	160000	0	0	10338	0	160002	1	0	0	2	160002	0	38	0	0	0	5109	1	17	1	1	101294	80000	160000	320000	80100	102220	102982	101267	101446	100868
480204	102517	781	0	0	0	0	0	3	0	0	41237	102023	16	0	1799	6766	25	599443	80100	361443	160000	80100	320000	160000	475862	4720611	5782550	0	0	101417	0	101053	101650	22720	3	22192	560100	200	160000	320000	200	400000	800000	101914	100874	1	1	80201	100	99	100	100	0	80000	80000	100	160000	0	40	11437	0	160002	0	0	0	2	160002	2	40	0	0	0	5109	1	17	1	1	100872	80060	160000	320000	80100	101887	101040	99898	101561	102950
480204	101296	789	0	0	0	0	0	0	0	0	43477	102169	16	16	2254	7044	25	600213	80100	359314	160000	80100	320000	160000	475794	4694555	5602937	0	0	101762	0	99866	100829	21724	3	20484	560100	200	160000	320000	200	400000	800000	99589	102255	1	1	80201	100	99	100	100	0	80000	80000	100	160000	0	40	10152	0	160000	0	0	0	2	160002	2	40	0	0	0	5109	1	16	1	1	100934	80000	160000	320000	80100	100981	101410	101099	101987	100102
480204	101637	786	0	0	0	0	12	3	0	0	42170	100299	16	0	1916	6912	25	601476	80100	359675	160000	80100	320000	160000	475646	4672842	5725934	0	0	101187	0	101897	100897	21710	3	20490	560100	200	160000	320000	200	400000	800000	101687	101278	1	1	80201	100	99	100	100	0	80000	80000	100	160000	0	42	10165	0	160002	0	0	0	5	160002	2	40	0	0	0	5110	1	16	1	1	100748	80000	160000	320000	80100	101069	100478	100719	100870	101337

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.2644

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	22	23	24	37	3a	3f	46	49	4e	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	5e	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd store (99)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
480027	101150	781	1	1	0	0	0	0	12	1	0	0	43077	2	100806	16	16	2027	7372	55	603885	80010	362226	160000	80010	320000	160000	475127	4677100	5667926	0	0	101608	0	101476	100711	21796	3	21280	560010	20	160000	320000	20	400000	800000	101793	101712	1	1	80021	10	9	10	10	80000	80000	10	160012	12	46	11157	0	160014	0	0	14	160002	14	46	12	1	5019	0	9	17	10	8	100641	80000	160000	320000	80010	86822	100575	101996	100930	102374
480024	101498	769	1	1	1	0	0	0	15	0	0	0	40088	2	101023	16	16	1920	6120	25	601513	80010	363313	160000	80010	320000	160000	475140	4734065	5713931	0	0	101842	0	100579	100836	21824	3	20835	560010	20	160000	320000	20	400000	800000	101400	100959	1	1	80021	10	9	10	10	80000	80000	10	160012	12	37	10169	0	160014	0	0	17	160002	14	38	12	1	5019	0	5	17	9	5	99932	80000	160000	320000	80010	101124	102359	98722	100671	99765
480024	99011	766	1	0	1	0	0	0	18	0	0	0	40856	2	99913	0	16	1987	5721	25	601167	80010	360436	160000	80010	320000	160000	474751	4708597	5551153	0	0	101517	0	102375	101892	21765	3	19955	560010	20	160000	320000	20	400000	800000	101976	102354	1	1	80021	10	9	10	10	80000	80000	10	160012	12	0	10064	0	160012	1	1	12	160002	14	0	12	1	5049	15	4	17	4	4	99639	80000	160000	320000	80010	101329	100738	100928	100655	100937
480024	101402	759	1	0	0	0	0	0	18	0	0	0	43080	2	101550	16	0	2059	6190	25	599540	80010	364654	160000	80010	320000	160000	474799	4700713	5716253	0	0	101757	0	102333	101773	20685	3	20985	560010	20	160000	320000	20	400000	800000	100498	100361	1	1	80021	10	9	10	10	80000	80000	10	160012	12	38	11015	0	160014	0	0	14	160002	12	38	12	0	5019	0	4	17	5	5	102022	80000	160000	320000	80010	100598	101994	100932	99865	102172
480024	100766	791	0	0	1	0	0	6	15	0	0	0	42783	0	100996	16	16	2117	6387	25	600690	80010	360508	160000	80010	320000	160000	474813	4678195	5562302	0	0	101802	0	101735	100746	21172	3	20774	560010	20	160000	320000	20	400000	800000	100050	102330	1	1	80021	10	9	10	2133	80000	80000	10	160000	12	38	11014	0	160002	0	0	8	160002	2	32	0	0	5019	0	4	17	4	4	101792	80000	160000	320000	80010	101456	101032	101463	100607	99471
480024	100114	776	0	0	0	0	0	3	2	0	0	0	41332	0	100698	16	16	2049	6719	25	600511	80010	364177	160000	80010	320000	160000	474952	4694627	5650609	0	0	100637	0	100323	100678	20436	3	21120	560010	20	160000	320000	20	400000	800000	100488	100254	1	1	80021	10	9	10	10	80000	80000	10	160013	13	32	10735	0	160002	1	0	12	160000	12	38	12	0	5020	0	5	16	4	4	101686	80000	160000	320000	80010	102587	99985	102402	102738	99889
480024	100877	786	1	0	0	0	0	6	18	0	0	0	39418	2	101080	16	0	2170	5830	25	604819	80010	359696	160000	80010	320000	160000	476308	4685709	5729845	0	0	101387	0	101753	101103	22584	3	21312	560010	20	160000	320000	20	400300	800000	102131	99165	1	1	80021	10	9	10	10	80000	80000	10	160013	13	38	10054	0	160014	1	0	15	160000	14	38	12	1	5019	0	3	17	4	4	101205	80000	160000	320000	80010	100826	100467	101449	101107	100250
480024	100524	782	1	0	0	0	0	0	12	0	0	0	39215	0	100698	16	16	2038	6208	25	599988	80010	363825	160000	80069	320000	160000	474694	4744804	5595349	0	0	101048	0	101076	99518	21164	3	22102	560010	20	160000	320000	20	400000	800000	99855	101550	1	1	80021	10	9	10	10	80000	80000	10	160000	0	32	10489	0	160000	0	0	2	160002	0	32	0	0	5020	0	4	16	6	4	101261	80000	160000	320000	80010	99177	99678	100867	99319	102293
480024	99853	783	1	1	0	1	0	12	16	0	0	0	37203	2	101498	16	16	2154	6826	25	601577	80010	361998	160000	80010	320000	160000	474927	4677022	5636943	0	0	100764	0	101860	100252	22496	3	20914	560010	20	160000	320000	20	400000	800000	101231	100639	1	1	80021	10	9	10	10	80000	80000	10	160000	0	0	9960	0	160002	0	0	2	160002	2	32	0	0	5019	0	4	17	4	4	100033	80000	160000	320000	80010	101848	102738	100241	101928	101180
480024	100419	775	1	0	0	0	0	0	15	0	0	1	38969	2	102024	16	15	2185	5350	25	602256	80010	360091	160000	80010	320000	160000	475611	4654928	5732648	0	0	100705	0	102947	102463	19993	3	21306	560010	20	160000	320000	20	400000	800000	99997	101402	1	1	80021	10	9	10	10	80000	80000	10	160013	12	38	10110	0	160014	0	0	20	160002	14	38	12	0	5019	0	5	17	4	4	101653	80000	160000	320000	80010	101716	98979	101171	102529	99556

ST4 (multiple, post-index, 2S)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations