Firestorm: ST4 (multiple, post-index, 4S) measurements

Code:

  st4 { v0.4s, v1.4s, v2.4s, v3.4s }, [x6], x8
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 0
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 12.000

Issues: 13.000

Integer unit issues: 1.000

Load/store unit issues: 4.000

SIMD/FP unit issues: 8.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	1f	22	24	37	3a	3f	46	49	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	5f	60	61	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd store (99)	inst ldst (9b)	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	c9	cf	d0	d2	l1i cache miss demand (d3)	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
72007	29001	232	1	0	17	1	1	15	0	0	0	0	88	0	0	0	4723	28885	0	4	14657	13000	1000	8000	4000	1000	8000	4000	5000	51901	71609	4	1	0	24667	28798	28796	3	30	13000	4000	8000	9009	20000	28796	28874	1	1	61001	1000	1000	4000	0	0	2	4001	0	0	0	4000	0	0	0	0	0	13128	9284	6926	3159	7	33	18830	3270	3809	10	36	35	28294	1001	15470	12225	12708	4000	8000	1000	29026	28884	28849	28923	28710
72004	28812	232	0	0	15	0	0	13	0	0	0	0	0	1	0	1	4768	28759	4	0	14525	13014	1000	8000	4000	1000	8000	4000	5000	51899	71604	10	0	0	24624	28621	28813	3	10	13013	4000	8000	9000	20000	28850	28873	1	1	61001	1000	1000	4000	0	11	0	4004	2	0	0	4000	0	9	0	0	0	13126	9247	6938	3191	8	35	18844	3238	3809	10	35	39	28287	1000	15945	12374	12455	4000	8000	1000	28840	28888	28919	28970	28929
72004	28811	231	0	1	12	1	1	15	1	0	0	0	5	1	0	0	4754	28721	0	4	14483	13000	1000	8000	4000	1000	8000	4000	5000	51909	71617	11	1	9	24658	28755	28711	3	10	13000	4000	8000	9000	20000	28746	28684	1	1	61001	1000	1000	4000	0	0	0	4000	0	0	2	4000	0	0	0	0	0	13087	9229	6882	3092	4	33	18914	3189	3811	16	40	34	28400	1000	15660	12200	12526	4000	8000	1000	28829	28819	28830	28909	28732
72004	28775	231	0	0	15	0	0	15	0	0	0	0	0	0	0	0	4653	28977	4	4	14589	13001	1000	8000	4000	1000	8000	4000	5000	51900	71625	13	0	8	24654	28653	28674	6	29	13013	4000	8000	9000	20000	28722	28838	1	1	61001	1000	1000	4005	5	12	1	4004	0	1	4	4000	4	12	4	2	0	13015	9430	6879	3135	8	40	18836	3234	3817	14	41	37	28245	1000	15401	12534	12788	4000	8000	1000	28825	28854	28903	28906	28742
72004	28813	231	0	0	14	0	0	17	0	0	0	0	0	0	0	0	4707	29061	4	0	14865	13000	1000	8000	4000	1000	8000	4000	5000	51913	71601	1	0	8	24695	28832	28973	3	10	13000	4000	8000	9000	20000	28621	28588	1	1	61001	1000	1000	4000	0	0	0	4000	0	0	0	4000	0	8	0	0	0	13176	9449	6928	3089	7	28	18660	3250	3805	12	39	39	28135	1000	15252	11988	12496	4000	8000	1000	29044	29103	29046	29073	29071
72004	28922	232	0	0	12	0	0	17	0	0	0	0	0	0	0	0	4586	28721	0	0	14580	13000	1000	8000	4000	1000	8000	4000	5000	51906	71609	7	0	8	24686	28614	28768	3	29	13013	4000	8000	9000	20000	28865	28847	1	1	61001	1000	1000	4000	0	8	0	4000	0	0	0	4002	0	8	0	0	433	13090	9342	6891	3090	8	41	19319	3284	3811	10	39	44	28833	1000	16737	13206	13681	4000	8000	1000	29271	29381	28983	28900	28961
72004	29233	233	0	0	10	0	0	14	0	0	0	0	2	0	0	1	4684	28649	4	1	14310	13000	1000	8000	4000	1000	8000	4000	5000	51899	71595	6	0	8	24651	28540	28710	3	10	13000	4000	8000	9000	20000	29091	29014	1	1	61001	1000	1000	4005	5	0	0	4004	0	1	4	4000	4	12	4	1	0	13195	9453	6889	3073	5	31	18819	3236	3809	15	37	37	28217	1000	15274	12510	12730	4000	8000	1000	28757	28667	28789	28707	29158
72004	28700	232	0	0	14	0	0	13	0	0	0	0	0	1	0	0	4775	28803	4	0	14986	13000	1000	8000	4000	1000	8000	4000	5000	51895	71613	3	1	0	24642	28656	28743	3	10	13000	4000	8000	9000	20000	28811	28627	1	1	61001	1000	1000	4000	0	8	0	4000	0	0	1	4000	0	12	0	0	0	12953	9308	6826	3143	7	40	18604	3213	3816	9	34	34	28396	1000	16014	12185	12669	4000	8000	1000	28727	28832	28921	28834	28793
72004	28707	231	0	1	14	1	0	16	1	0	0	0	5	1	0	0	4693	29397	3	3	14809	13000	1000	8001	4000	1000	8000	4000	5000	52081	71612	5	0	8	24751	28993	29067	3	10	13013	4000	8000	9000	20000	29260	29203	1	1	61001	1000	1000	4000	0	8	0	4000	0	0	0	4000	0	9	0	0	0	13139	9464	6830	3066	7	33	19366	3409	3814	7	42	40	28623	1000	16059	12628	12671	4000	8000	1000	29160	29130	29131	29168	29000
72004	29198	235	0	0	14	0	0	8	0	0	0	426	0	1	0	0	4637	29229	4	3	14950	13000	1000	8000	4000	1000	8000	4000	5000	51903	71688	6	1	8	24709	28924	29159	3	10	13013	4000	8008	9000	20000	29440	28903	1	1	61001	1000	1000	4004	0	8	0	4000	0	0	0	4000	0	8	0	0	0	13182	9345	6910	3089	7	38	19455	3367	3813	14	35	32	28581	1000	15700	12404	12486	4000	8000	1000	28883	28765	28748	28914	28858

Count: 8

Code:

  st4 { v0.4s, v1.4s, v2.4s, v3.4s }, [x6], x8
  st4 { v0.4s, v1.4s, v2.4s, v3.4s }, [x6], x8
  st4 { v0.4s, v1.4s, v2.4s, v3.4s }, [x6], x8
  st4 { v0.4s, v1.4s, v2.4s, v3.4s }, [x6], x8
  st4 { v0.4s, v1.4s, v2.4s, v3.4s }, [x6], x8
  st4 { v0.4s, v1.4s, v2.4s, v3.4s }, [x6], x8
  st4 { v0.4s, v1.4s, v2.4s, v3.4s }, [x6], x8
  st4 { v0.4s, v1.4s, v2.4s, v3.4s }, [x6], x8

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 2.5060

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	1f	22	23	24	37	3a	3f	46	49	4e	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	67	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd store (99)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	branch mispred nonspec (cb)	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
960207	199097	1553	1	0	1	0	0	0	0	0	20	1	0	0	82876	1	198340	16	16	1174	17356	25	1125061	80100	729257	320000	80100	640000	320000	400500	9297274	10738645	0	0	199534	0	198191	199445	39649	3	37354	1040100	200	320000	640000	200	720000	1600000	200077	200011	13	1	80201	100	99	100	100	80000	80000	100	320014	14	38	26295	0	320196	2	1	19	320002	16	36	14	1	0	5109	0	1	17	1	1	200239	80000	0	320000	640000	80100	199192	197981	197291	201153	198913
960204	197487	1535	1	1	1	1	0	0	0	12	18	0	0	0	84790	0	201334	15	14	1330	16401	25	1129154	80100	722216	320060	80132	640000	320000	400500	9190184	10712876	0	0	200196	0	201682	199692	40840	3	39268	1040100	200	320000	640240	200	720000	1600000	202177	200682	1	1	80201	100	99	100	100	80000	80000	100	320015	15	34	25453	0	322234	1	0	20	320002	16	36	0	0	0	5109	0	1	16	1	1	201410	80000	0	320000	640000	80100	200816	204863	198847	199049	200859
960204	201351	1564	0	0	0	0	1	0	0	36	17	0	0	0	84379	1	201929	15	16	1595	16530	25	1120108	80100	728079	320000	80100	640238	320000	400500	9214773	10671136	0	0	201639	0	199253	197753	38221	3	40262	1040100	200	320000	640240	200	720000	1600000	200721	200168	2	1	80201	100	99	100	100	80000	80000	100	320014	14	36	25141	0	320016	0	1	18	320002	14	36	14	0	0	5109	0	2	17	1	1	199228	80001	0	320000	640000	80100	197686	196811	200633	202411	201379
960204	197155	1548	1	0	0	0	1	0	0	12	105	0	0	1	90439	1	199185	16	16	1353	16640	25	1125332	80129	724404	320060	80100	640000	320000	400500	9131397	10883069	0	0	199560	0	200659	201961	40730	3	40548	1040100	200	320000	640000	200	720000	1600000	200323	200933	1	1	80201	100	99	100	100	80000	80000	100	320015	15	36	25434	0	320016	1	0	1012	320002	16	34	14	1	0	5120	0	1	17	1	1	200961	80000	0	320000	640000	80100	202059	197537	201659	201890	200362
960204	201530	1548	1	2	1	0	1	0	0	0	2	0	1	0	84761	1	199815	16	16	1524	17044	25	1128453	80100	726275	320000	80129	640000	320000	400645	9302798	10704038	0	0	198108	0	201395	198952	41939	3	41091	1040100	200	320120	640000	200	720000	1600000	197806	198919	1	1	80201	100	99	100	100	80000	80000	100	320015	14	36	25433	0	320016	0	0	941	320002	2	34	14	0	0	5109	0	1	17	1	2	200392	80000	0	320000	640000	80100	199354	201505	200654	200139	199486
960204	199105	1535	1	1	0	0	0	0	0	132	19	0	1	0	82129	1	200360	16	15	1214	16281	25	1123276	80100	728654	320000	80100	640000	320108	400500	9222965	10793338	0	0	218036	0	199837	199792	39797	12	39467	1040100	200	320000	640240	200	720000	1600000	200569	201249	1	1	80201	100	99	100	100	80000	80000	100	320014	15	36	26016	1	320016	0	0	5	320002	2	36	14	0	0	5110	0	1	16	1	1	196489	80029	0	320000	640000	80100	201490	201454	201980	202458	199966
960204	200671	1549	1	1	0	0	0	0	0	0	19	0	0	0	84013	0	199758	16	16	1414	16863	25	1130061	80100	726125	320000	80100	640000	320108	400500	9240966	10806257	0	0	199533	0	201247	200991	39373	13	40692	1040100	200	320000	640000	200	720000	1600000	200758	198981	1	1	80201	100	99	100	100	80000	80000	100	320137	17	36	26846	0	320258	0	0	3009	320242	14	36	14	3	0	5166	0	1	43	1	2	200271	80667	0	320000	640000	80100	202045	202222	201729	200298	200342
960204	200013	1538	1	2	2	0	0	4	4	528	196	0	1	0	82928	1	198810	16	16	1587	15042	25	1120150	80100	727343	320000	80100	640000	320000	400500	9239577	10855299	0	0	199345	0	199953	197843	38064	3	38457	1040100	200	320000	640000	200	720000	1600000	199262	200171	1	1	80201	100	99	100	100	80000	80000	100	320015	14	36	26521	0	320017	1	0	17	320002	16	36	14	1	1	5109	0	1	16	1	1	198868	80001	0	320000	640000	80100	201923	200020	202073	200346	201546
960204	201865	1558	0	0	0	0	1	0	0	45	21	0	0	0	91833	1	198526	16	16	1725	16790	25	1130653	80100	728473	320000	80100	640000	320000	400500	9217373	10711667	0	0	200486	0	198965	200746	38411	3	37136	1040100	200	320000	640000	200	720000	1600000	199312	199820	1	1	80201	100	99	100	100	80000	80000	100	320014	15	38	26462	1	320002	0	0	17	320002	2	36	14	0	0	5109	0	1	17	1	1	200365	80000	0	320000	640000	80100	198341	201455	198384	198736	198215
960204	197929	1556	1	0	1	0	1	0	0	0	19	0	1	0	88977	1	202418	16	16	1657	16601	25	1121601	80100	724733	320000	80100	640000	320000	400500	9181589	10874236	0	0	198548	0	201732	201914	41052	3	38989	1040100	200	320000	640000	200	720000	1600000	198750	200215	1	1	80202	100	99	100	100	80000	80000	100	320015	15	40	23983	0	320016	0	0	17	320002	14	0	0	0	0	5109	0	1	17	2	1	199322	80000	0	320000	640000	80100	199913	198844	200837	198299	200362

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 2.4970

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	1f	22	24	37	3a	3f	46	49	4e	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	67	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd store (99)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	c2	cf	d2	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
960027	201335	1559	0	0	0	0	0	2555	0	0	83462	0	200632	16	16	1435	17259	25	1124405	80039	724971	320000	80010	640000	320000	400054	9265105	10752214	1	0	202317	0	218596	198691	40514	10	40852	1040010	20	320120	640000	20	720000	1600000	198808	199336	1	1	80021	10	9	10	10	80000	80000	10	320000	0	0	24537	0	320002	0	0	2	320002	2	42	0	5031	0	3	17	3	3	199214	80000	0	320000	640000	80010	198289	198915	199683	197817	199207
960024	201366	1536	0	0	0	0	0	3	0	0	84372	0	201026	0	16	1145	15652	25	1122680	80010	730733	320000	80039	640000	320000	400058	9174400	10772660	0	0	199663	0	198125	199261	38265	3	38112	1040010	20	320000	640240	20	720000	1600000	198861	198288	1	1	80021	10	9	10	10	80000	80000	10	320000	0	42	27219	0	320002	0	0	5	320002	2	42	0	5019	0	3	17	3	2	197974	80000	4	320000	640000	80010	199353	203064	199635	199143	201328
960024	199763	1559	0	0	0	0	0	3	0	0	90133	0	200028	16	16	1518	16000	25	1125425	80010	728522	320000	80010	640238	320000	400050	9160170	10770026	0	0	199993	0	200263	198268	41464	3	40476	1040010	20	320000	640000	20	720000	1600000	197394	198011	2	1	80021	10	9	10	10	80000	80000	10	320000	0	42	25084	0	320000	1	0	5	320002	2	42	0	5019	0	3	16	3	3	201007	80000	0	320000	640000	80010	198300	198481	199907	200176	200179
960024	197590	1619	0	0	0	0	132	3	0	0	85590	0	201037	16	16	2003	16262	53	1121681	80010	728373	320000	80010	640000	320000	400050	9150149	10862072	0	1	199010	0	199346	200820	39420	3	38003	1040010	20	320000	640000	20	720000	1600000	202468	201497	2	1	80021	10	9	10	10	80000	80000	10	320000	0	42	26145	0	320002	2	0	2	320060	2	42	0	5020	0	2	17	3	5	198588	80000	0	320000	640000	80010	199345	202220	199402	199151	199099
960024	200209	1556	0	0	0	0	18	3	0	0	83548	0	199114	16	0	1449	15961	25	1127576	80010	732211	320000	80010	640000	320000	400050	9096199	10967750	0	0	201343	0	197463	201469	39421	3	37838	1040010	20	320000	640000	20	720000	1600000	199854	202212	1	1	80021	10	9	10	10	80000	80000	10	320000	0	42	25549	0	320002	0	0	2	320002	2	42	0	5019	0	3	25	3	3	201059	80000	0	320000	640000	80010	201915	201572	198992	199401	202065
960024	200092	1556	0	0	0	0	12	3	0	0	83828	0	197688	16	16	1598	16262	25	1125460	80010	723454	320000	80010	640000	320000	400050	9268007	10786284	0	0	200842	0	200573	198304	38451	3	40892	1040385	20	320000	640000	20	720000	1600000	203080	198058	1	1	80021	10	9	10	10	80000	80000	10	320060	0	42	26121	0	320002	1	0	1	320000	2	42	0	5019	0	3	17	3	2	200253	80000	0	320000	640000	80010	200747	200166	201052	200494	200737
960024	199631	1561	0	0	0	0	12	3	1	0	81079	0	200846	16	16	1157	17339	137	1126968	80068	718400	320180	80126	640714	320324	401068	9469459	11092421	0	0	200006	0	199747	201338	41416	34	39993	1040760	20	320360	640720	20	720540	1601800	200723	201354	5	1	80021	10	9	10	10	80000	80000	10	320249	2	42	25813	0	320182	3	0	3127	320182	2	42	0	5019	0	2	16	3	2	199987	80000	0	320000	640000	80010	200981	200413	199794	198974	201828
960024	198141	1533	0	0	0	0	9	3	0	0	89319	0	201109	0	16	1336	16527	25	1127857	80010	727957	320000	80010	640000	320000	400050	9287846	10859121	0	1	198756	0	199580	201848	41545	3	40224	1040010	20	320000	640000	20	720000	1600000	201520	198184	1	1	80021	10	9	10	10	80000	80000	10	320000	0	42	25223	0	320002	0	0	0	320002	2	42	0	5019	0	2	17	3	3	201443	80000	0	320000	640000	80010	197550	199246	199983	200804	200876
960024	198945	1554	0	0	0	0	0	3	0	0	86559	0	198866	16	16	1476	17147	25	1128874	80010	722598	320000	80010	640000	320000	400050	9229344	10657417	0	0	200432	0	201164	200306	40473	3	41692	1040010	20	320000	640000	20	720000	1600000	198820	202203	1	1	80021	10	9	10	10	80000	80000	10	320000	0	0	24986	0	320002	0	0	2	320002	2	42	0	5019	0	3	17	2	2	197112	80000	0	320000	640000	80010	200236	200296	198706	198908	200384
960024	201724	1572	0	0	0	0	6	3	0	0	86396	0	197457	16	16	1582	16559	25	1126795	80010	725831	320000	80010	640000	320000	400055	9281532	10763831	1	0	198692	0	200673	200549	41091	3	39848	1040010	20	320000	640000	20	720000	1600000	201180	199239	1	1	80021	10	9	10	10	80000	80000	10	320000	0	42	24905	0	320002	0	0	2	320002	2	42	0	5019	0	3	16	3	2	200906	80058	0	320000	640000	80010	200780	200040	201882	198964	199893

ST4 (multiple, post-index, 4S)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations