Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

ST4 (multiple, post-index, 8B)

Test 1: uops

Code:

  st4 { v0.8b, v1.8b, v2.8b, v3.8b }, [x6], x8
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop
  mov x0, 0
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 6.000

Issues: 7.000

Integer unit issues: 1.000

Load/store unit issues: 2.000

SIMD/FP unit issues: 4.000

retire uop (01)cycle (02)03l1i tlb fill (04)l1d tlb fill (05)mmu table walk instruction (07)mmu table walk data (08)09l2 tlb miss instruction (0a)l2 tlb miss data (0b)18191e1f2223373a3f464951schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)5f696d6emap rewind (75)map stall (76)dispatch uop (78)map ldst uop (7d)map simd uop (7e)map ldst uop inputs (80)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd store (99)inst ldst (9b)l1d tlb access (a0)l1d tlb miss (a1)l1d cache miss st (a2)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acafbcl1d cache miss st nonspec (c0)l1d tlb miss nonspec (c1)c2c9cfd0d2l1i cache miss demand (d3)l1i tlb miss demand (d4)d5map dispatch bubble (d6)d9dadbddfetch restart (de)e0? int output thing (e9)eaebec? ldst retires (ed)? simd retires (ee)? int retires (ef)f5f6f7f8fd
660072953123730261024000020004722294382216305700110004000200010004000200050002562535811102388529128295773107000200040005000100002943729398116100110001000200006020000022020000600013108931569133137145020384332938141152542883810001611813250136012000400010002947729578294602941829588
66004295902370116102500002000464829376201622770001000400120001000400020005000256103584962387429307298348487007200040045000100602951529608216100110001000200200020000289520000604013289935369083153165120412330338111857572896010051612513509135992000400010002979129713295792965329623
6600429433236002610201111321760004612297760016274700010004005200010004000200050052574335875323862295072969516477014200240045010100102962129639316100110001000200444020040046520040600013177937068963164174920563331838171754542886110011757213457135882000400010002958929533295172958129959
66004298672400024001900000000453129557021646370001000400020001000400420005000255963580632388129414298093107000200040005000100002954129506116100110001000200000020000051020000400013198952368783117175620297331938141352542933610001638913354142842000400010002989029617296782972229626
6600430234240002300240003010014648295300016073700010004000200010004000200250002563135798023905295603025491070002000400050001000030291300771161001100010002000040200000020000400013288923369393180125120318342438111351522885710001634313495136062000400010002939829654298722958029761
66004300712400022002600014410004617298840016198700010004000200210004000200050002560235844323823293672945131070002000400050001000029709295771161001100010002004301200211520010400012942926569343119155420208336938141846502870310001618213457138282000400010002932129425292962933829465
66004295982360022002500001000462629851001670470001000400020001000400020005000256073581252384329204295003107000200040005000100002953429553116100110001000200000020000002000000001292893836845315212472012832203816943482873810001597713288134472000400010002948229455294252941829336
660042934422800240020000000004670293020016144700010004000200010004000200050002560835797523898292202939831070002000400050101000029307292981161001100010002000000200034320000000012984917669123133124820211318038131151442870910001639613370135912000400010002944629453292402932729414
6600429461228002300250001800004725293190016038700010004001200010004000200050002561135810323815291602953331070002000400050001000029134292211161001100010002002401200201220000400013046940968283126135620105321238121250502856910001619813507136432000400010002943829273294072926329337
660042936022700250022000010004679293270017353700010004000200010004000200050002561035805423821293192953731070002000400050001000029460294631161001100010002002340200201220000000013361954769593134115320409333338161248532876210001626013339138392000400010002947129413295132952429556

Test 2: throughput

Count: 8

Code:

  st4 { v0.8b, v1.8b, v2.8b, v3.8b }, [x6], x8
  st4 { v0.8b, v1.8b, v2.8b, v3.8b }, [x6], x8
  st4 { v0.8b, v1.8b, v2.8b, v3.8b }, [x6], x8
  st4 { v0.8b, v1.8b, v2.8b, v3.8b }, [x6], x8
  st4 { v0.8b, v1.8b, v2.8b, v3.8b }, [x6], x8
  st4 { v0.8b, v1.8b, v2.8b, v3.8b }, [x6], x8
  st4 { v0.8b, v1.8b, v2.8b, v3.8b }, [x6], x8
  st4 { v0.8b, v1.8b, v2.8b, v3.8b }, [x6], x8
  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.2630

retire uop (01)cycle (02)03mmu table walk data (08)09l2 tlb miss data (0b)0f18191e1f2223373f46494e4f51schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd store (99)inst ldst (9b)9fl1d tlb access (a0)l1d cache miss st (a2)a4ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acafbcl1d cache miss st nonspec (c0)c2branch cond mispred nonspec (c5)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)f5f6f7f8fd
48020710061179501002227617800418969965216162572565425600140801003634461600008010032000016000047573547569255843138010136399679101465209593225855601002001600003200002004000008000001018411016611180201100991001008000080000100160000329802016000210516000203200051101171110169980000160000320000801009963599800101100100237100545
4802041007247860000004085004259510185216162111628425600178801003619021600008010032000016000047532647538975637362010204910186410023020539321715560100200160000320000200400000800000997471022253180201100991001008000080000100160000321132401600020021600002320005109117111013398000016000032000080100101860100588102890101035101476
48020410045277300000048040040739101563160209268652560021280100364736160000801003200001600004757804688039560271601008331018109822318887320491560100200160000320000200400000800000999311031341180201100991001008000080000100160000321091201600020011160002232000510911711102125800001600003200008010010123298587100196100113101638
480204100212791000000387400417871010691616224969092559926280100357013160000801003200001600004760864681146559303519999399978102220208773222635601002001600003200002004000008000001017971010211180201100991001008000080000100160000321067601600020021600022320115109116111019268000016000032000080100101919101126100448102280100282
48020410103978600000052821041720998151616196563742560248680100359764160000801003200001601084757524657798563855801014791010989796721335321618560100200160000320000200400000800000102445996991180201100991001008000080000100160000321103001600020051600002320005109117111010298000016000032000080100101143100821101480100192101883
480204101314775000000396200424871012381616233855392560089680100361720160000801003200001600004759764736170550851001016169910010096920395321835560100200160000320000200400000800000100659101536118020110099100100800008000010016000032107780160002008160002032000510911611100149800001600003200008010099998101921100448100616102071
4802051019167780000007220041674100715161616786657256032738010035832416000080100320000160000475774471885755568860101016100970102615207593209805601002001600003200002004000008000001014941014211180201100991001008000080000100160000329945016000200216000223200051091171110037480000160000320000801001001959832897659101701101323
48020410174878200000041120040349100154161620326320256010428010036161016000080100320000160000475632470202156117510101928100785100170222453214445601002001600003200002004000008000001002261015571180201100991001008000080000100160000321004001600021051600022320005109116111011618000016000032000080100101816101262101102101423100872
4802041003597910000004238004357410114916019886513256002818010035937716000080100320000160000475933471308555672030101987101170102116203823220465601002001600003200002004000008000001023301003361180201100991001008000080000100160000321061201600020081600022320005109116111017148000016000032000080100101316101109100530100746102063
4802041003587830000005552014245710203716019396558256014348010036380216000080100320000160000475020472310256494270101713102178102077206373216585601002001600003200002004000008000001009301003451180201100991001008000080000100160000321146301600020051600022320005109117111008538000016000032000080100101828100591101859102172100327

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.2659

retire uop (01)cycle (02)03l1d tlb fill (05)mmu table walk data (08)09l2 tlb miss data (0b)0f18191e1f222324373a3f46494e4f51schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)6067696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd store (99)inst ldst (9b)9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache miss st (a2)a4ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acafbcl1d cache miss st nonspec (c0)c2branch mispred nonspec (cb)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)ea? ldst retires (ed)? simd retires (ee)? int retires (ef)f5f6f7f8fd
4800271007947550000000020004202511005651616254166772560296780010361883160000800103200001600004752344680479552697300100298101852101711214513217415600102016000032000020400000800000100233103276118002110910108000080000101600000321025901600021051600020320050213175510289180000016000032000080010100830102772100367102282100242
48002410115780300000001221004152111012501616207069402559951480010360472160000800103200001600004752394579454568395600101708100883101999212363215105600102016000032000020400000800000101459100966118002110910108000080000101600000321041001600001021600002320050214174310037380000016000032000080010100916101647100069101666100847
4800241003418150000000020004211011017470162277646825600300800103623601600008001032000016000047491947345005573700001019799939910029321090321244560010201600003200002040000080000010237210097811800211091010800008000010160000032108680160002105160002238005022516559951080000016000032000080010100840101150101051101070102375
4800241015368160000000000004255311007921602069650725597622800103624461600008001032000016000047551246891365622385001018441014931017722129532158556001020160000320000204000008000001007001002081180021109101080000800001016000000924701600020031600002320050214174610182080000016000032000080010102758101565100883101530101283
480024100837812000000012800041877110133901623596725256025788001036174816000080010320000160000474631471262157105400010148810182710267822183319481560010201600003200002040000080000010085210099111800211091010800008000010160000032101020160002002160002234005022317451028518000001600003200008001010192110206399631101797101772
4800241025138140000000000004269911004231616165263482559805080010363029160000800103200001600004760564699484575887200101722102722100500200423207985600102016000032000020400000800000101828102041118002110910108000080000101600000010908016000200816000000005022517451007558000001600003200008001010123710164710124310160399799
4800241015788140000000001003977311011741616215272622560230580010359415160000800103200001600004748514696364563435500101377102053101930213183206315600102016000032000020400000800000100853101698118002110910108000080000101600000321008001600000021600002320050215175510094280000016000032000080010100362101474100013101069101746
480024101979813000000000000441011101007161619836501256044438001036046816000080010320000160000474576467737656735670010210299931102059209853205895600102016000032000020400000800000101735100149118002110910108000080000101600000321120501600021081600022320050214164410132080000016000032000080010100680100670100944102123100995
480024100904813000000012210040998110216016162307502825600736800103568621600008001032000016000047493047451495633536001019581018521019932031032009556001020160000320000204000008000009998610048111800211091010800008000010160000044102030160002103160002200050215175510193780000016000032000080010102680101799101336100296100236
480024102913806000000007000391841102013160192368212560225980010361213160000800103200001600004746134697539576773100100791101991101139218963201245600102016000032000020400000800000103014100144118002110910108000080000101600000321064201600021021600022320050215174410103880000016000032000080010102586101709100092101153102379