Firestorm: ST4 (multiple, post-index, 8H) measurements

Code:

  st4 { v0.8h, v1.8h, v2.8h, v3.8h }, [x6], x8
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 0
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 12.000

Issues: 13.000

Integer unit issues: 1.000

Load/store unit issues: 4.000

SIMD/FP unit issues: 8.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	1f	22	23	24	37	3a	3f	46	49	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	5f	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd store (99)	inst ldst (9b)	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	c9	cf	d0	d2	l1i cache miss demand (d3)	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
72007	29583	237	1	0	12	0	0	9	0	0	0	0	0	0	0	0	0	4721	29276	0	1	15199	13000	1000	8008	4000	1000	8000	4000	5000	51904	71620	5	24644	29226	29553	3	10	13000	4000	8000	9000	20000	29359	29446	1	1	61001	1000	1000	4000	0	12	0	4000	0	0	0	4000	1	8	0	0	0	13071	9462	7003	3128	2	53	19372	3331	3832	16	54	54	28855	1000	16346	12846	12960	4000	8000	1000	29514	29387	29488	29355	29350
72004	29425	236	0	0	8	0	1	10	0	1	0	12	5	0	0	0	0	4689	29224	1	1	15245	13000	1000	8000	4000	1000	8000	4000	5000	51910	71589	4	24738	29417	29520	3	10	13000	4004	8000	9000	20000	29455	29398	1	1	61001	1000	1000	4000	0	0	0	4000	0	0	0	4000	4	12	4	1	293	13244	9284	6979	3205	6	53	19336	3360	3827	20	44	49	28786	1000	16223	12763	12971	4000	8000	1000	29383	29264	29361	29350	29516
72004	29489	237	0	1	8	0	0	5	0	0	0	132	1	0	0	0	0	4697	29380	4	0	15206	13000	1001	8000	4000	1000	8000	4004	5000	51911	71601	6	24735	29229	29509	11	10	13000	4000	8000	9000	20000	29386	29468	1	1	61001	1000	1000	4004	5	0	3	4008	0	3	4	4000	1	12	0	2	869	13109	9246	6879	3058	3	44	19740	3339	3817	17	53	48	29034	1001	16292	12853	13149	4000	8000	1000	29563	29916	29845	29517	29455
72004	29790	238	0	0	6	0	1	6	0	1	0	141	5	1	0	0	0	4674	29488	1	0	15113	13000	1001	8000	4000	1001	8000	4008	5000	51901	71614	6	24680	29256	29477	7	10	13013	4000	8000	9000	20000	29454	29443	1	1	61001	1000	1000	4000	0	0	3	4000	0	0	475	4000	0	12	0	0	657	12980	9158	6900	3072	2	46	20133	3365	3825	29	51	47	29451	1001	16299	12880	13048	4000	8000	1000	29548	29484	29475	29363	29445
72004	29377	237	1	0	6	0	2	7	0	0	0	264	1	0	0	0	0	4675	29447	4	4	15251	13000	1000	8008	4004	1000	8006	4000	5005	51889	71602	2	24674	29275	29378	3	10	13000	4000	8000	9004	20000	29416	29344	2	1	61001	1000	1000	4002	0	12	0	4006	0	0	450	4000	0	12	0	0	0	12874	9193	6942	3161	3	51	19340	3278	3828	15	48	47	28703	1001	16053	12905	13148	4000	8000	1000	29451	29432	29397	29433	29476
72004	29490	237	0	0	4	0	1	9	0	0	0	0	0	0	0	1	0	4710	29373	0	0	15097	13001	1000	8000	4000	1000	8000	4000	5000	51898	71612	9	24682	29225	29379	3	10	13000	4000	8000	9000	20000	29353	29456	1	1	61001	1000	1000	4000	0	12	0	4000	0	1	1	4000	0	12	0	0	0	13196	9292	6937	3123	3	48	19343	3237	3830	19	47	50	28694	1000	16118	12828	13008	4000	8000	1000	29614	29661	29691	29533	29553
72004	29453	237	0	0	5	0	0	3	0	0	0	0	0	0	0	0	0	4756	29194	0	0	15156	13000	1000	8000	4000	1000	8000	4000	5000	51901	71613	2	24661	29185	29352	3	10	13000	4000	8000	9000	20000	29349	29319	1	1	61001	1000	1000	4000	0	12	0	4000	0	0	0	4000	0	12	0	0	0	13270	9506	6953	3115	2	46	19404	3271	3822	19	53	47	28722	1000	16028	12935	13019	4000	8000	1000	29331	29395	29459	29449	29385
72004	29559	236	1	0	5	0	0	4	0	0	0	12	0	0	0	0	1	4760	29323	0	4	15102	13000	1000	8000	4000	1000	8000	4000	5000	51896	71639	4	24751	29275	29538	3	10	13000	4000	8000	9000	20000	29372	29390	1	1	61001	1000	1000	4000	0	12	0	4000	0	0	3	4000	0	12	0	0	0	13118	9446	6913	3164	2	54	19320	3232	3822	17	44	47	28722	1000	16143	12830	13058	4000	8000	1000	29406	29448	29506	29451	29344
72004	29366	237	0	0	8	0	0	7	0	0	0	0	1	0	0	0	0	4756	29288	0	4	15182	13000	1000	8000	4000	1000	8000	4000	5000	51890	71622	8	24711	29218	29497	3	10	13000	4000	8000	9000	20000	29254	29392	1	1	61001	1000	1000	4000	0	12	0	4000	0	0	0	4000	0	12	0	0	0	13173	9340	6994	3165	3	49	19402	3340	3829	9	47	49	28778	1000	16206	12764	12923	4000	8000	1000	29373	29433	29481	29362	29390
72004	29446	236	0	0	5	0	0	4	0	0	0	0	1	0	0	0	0	4702	29346	3	4	15244	13000	1000	8000	4000	1000	8000	4000	5000	51896	71611	4	24653	29545	29744	22	10	13000	4000	8000	9000	20000	29341	29331	2	1	61001	1000	1000	4000	0	8	0	4001	0	0	3	4000	4	0	4	1	0	13079	9370	7010	3162	3	53	18804	3224	3833	23	46	48	28344	1000	15540	11996	12398	4000	8000	1000	29030	29053	28821	28826	29063

Count: 8

Code:

  st4 { v0.8h, v1.8h, v2.8h, v3.8h }, [x6], x8
  st4 { v0.8h, v1.8h, v2.8h, v3.8h }, [x6], x8
  st4 { v0.8h, v1.8h, v2.8h, v3.8h }, [x6], x8
  st4 { v0.8h, v1.8h, v2.8h, v3.8h }, [x6], x8
  st4 { v0.8h, v1.8h, v2.8h, v3.8h }, [x6], x8
  st4 { v0.8h, v1.8h, v2.8h, v3.8h }, [x6], x8
  st4 { v0.8h, v1.8h, v2.8h, v3.8h }, [x6], x8
  st4 { v0.8h, v1.8h, v2.8h, v3.8h }, [x6], x8

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 2.5010

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	22	23	24	37	3a	3f	46	49	4e	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	67	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd store (99)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	cf	d0	d2	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
960207	201549	1364	0	1	0	0	0	0	0	2	0	0	0	82564	0	200240	16	16	1552	16778	25	1122751	80102	725151	320000	80104	640030	320007	401093	9230392	10756719	0	0	201869	200444	200929	38024	6	40368	1040143	200	320016	640262	200	720031	1600080	199549	199034	2	1	80201	100	99	100	100	80000	80000	100	320000	0	36	26805	0	320002	0	0	2	320002	2	34	0	0	5110	0	0	2	26	1	2	198115	80000	320000	640000	80100	200238	199762	200326	200033	199976
960204	201330	1613	0	0	0	0	0	0	3	2	0	0	0	82342	0	200081	16	16	1366	16688	25	1125269	80100	722274	320000	80100	640000	320000	400500	9285318	10739191	0	0	199658	201311	199882	39668	3	41458	1040100	200	320000	640000	200	720000	1600000	198127	199739	1	1	80201	100	99	100	100	80000	80000	100	320000	0	34	26163	0	320002	1	0	8	320002	2	34	0	0	5109	0	0	1	16	2	1	201555	80000	320000	640000	80100	201070	200277	201837	200232	197738
960204	197773	1608	0	0	0	0	1	0	12	2	0	0	0	84240	0	199352	16	16	1416	15500	25	1131163	80100	722872	320000	80100	640000	320108	400500	9225947	10752437	0	0	200335	197350	201936	38013	3	40578	1040100	200	320000	640000	200	720000	1600000	200931	198500	1	1	80201	100	99	100	100	80000	80000	100	320000	0	0	9	0	320008	0	0	12	320002	2	34	0	0	5109	0	0	1	16	2	2	201373	80002	320000	640000	80100	199579	198576	199801	199893	198706
960204	200655	1628	0	0	0	0	0	1	60	8	0	0	1	86943	0	200879	16	16	1538	16575	25	1127927	80100	726922	320000	80100	640000	320000	400500	9290707	10748718	1	0	199965	199764	200554	38932	3	40984	1040100	200	320000	640000	200	720270	1600000	199424	197991	1	1	80201	100	99	100	100	80000	80000	100	320000	0	34	24421	0	320002	0	0	240	320002	2	34	0	0	5110	0	0	1	17	1	1	202354	80001	320000	640000	80100	198782	200187	200954	200933	198807
960204	201065	1612	0	0	0	0	0	0	3	2	0	1	0	82439	0	198004	16	16	1313	15818	25	1125190	80100	727584	320000	80100	640000	320000	400509	9293003	10702985	0	0	198673	200039	198941	39182	3	39361	1040100	200	320000	640000	200	720000	1600000	201254	199993	1	1	80201	100	99	100	100	80000	80000	100	320000	0	34	25227	0	320002	0	0	128	320002	2	34	0	0	5109	0	0	1	17	2	2	202979	80000	320000	640000	80100	199154	201035	201264	201085	202545
960204	203117	1621	0	0	0	0	0	0	27	2	0	0	0	90784	0	201279	0	16	1388	16892	25	1131265	80101	727393	320000	80216	640000	320000	400504	9110561	10773371	0	0	199414	200121	200821	39407	3	40154	1040100	200	320000	640000	200	720000	1600000	201078	196368	1	1	80201	100	99	100	100	80000	80000	100	320000	0	0	26181	0	320002	0	0	11	320002	2	34	0	0	5109	0	0	1	16	1	1	203928	80000	320000	640000	80100	202482	198337	197871	198017	198599
960204	199483	1612	0	0	0	0	0	0	3	5	0	0	0	90753	0	201454	16	16	1659	16009	25	1134311	80100	724958	320000	80129	640000	320000	400500	9335664	10770882	0	0	200256	201401	200373	41716	3	41989	1040100	200	320000	640000	200	720000	1600000	199831	201509	1	1	80201	100	99	100	100	80000	80000	100	320000	0	34	25098	0	320002	0	0	32	320062	2	34	0	0	5109	0	0	1	17	1	1	201264	80029	320000	640000	80100	200182	199719	202367	197128	203269
960204	200082	1611	0	0	1	0	2	4	396	178	0	1	0	86546	0	202067	16	16	1665	20418	1139	1140087	81088	725822	320240	80187	640952	320324	401090	9334708	10807806	0	1	201370	198547	197479	39591	22	40302	1041600	200	320360	640960	202	720810	1601800	199737	202038	4	1	80201	100	99	100	100	80000	80000	100	320000	0	34	26319	0	320002	1	0	17	320002	2	34	0	0	5109	0	0	1	17	1	1	197952	80000	320000	640000	80100	200622	197599	198617	199818	199392
960204	201244	1627	0	0	0	0	0	0	3	0	0	0	0	90559	0	201304	16	16	1408	16761	25	1125148	80100	726005	320000	80100	640000	320108	400500	9225726	10834241	0	0	200425	197915	199125	40221	3	40899	1040100	200	320000	640000	200	720000	1600000	201669	200416	1	1	80201	100	99	100	100	80000	80000	100	320000	0	34	24890	0	320002	0	0	44	320002	0	34	0	0	5110	0	0	1	17	1	1	198410	80000	320000	640000	80100	200272	201374	200724	200648	199852
960204	200070	1606	0	0	0	0	0	0	3	2	0	0	0	90455	0	200491	16	16	1699	15198	25	1130323	80100	723481	320000	80100	640000	320000	400500	9249220	10669220	0	0	199164	200787	200476	39862	3	39113	1040100	200	320000	640000	200	720000	1600000	200073	198052	1	1	80201	100	99	100	100	80000	80000	100	320000	0	0	25128	0	320002	1	0	197	320002	2	34	0	0	5109	0	0	1	17	2	1	199959	80000	320000	640000	80100	200649	200534	200744	201483	197874

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 2.5038

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	22	23	24	37	3a	3f	46	49	4e	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	66	67	69	6b	6d	6e	map stall dispatch (70)	int prf full (71)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd store (99)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ab	ac	af	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
960027	197329	1556	0	0	0	0	0	0	0	15	3	0	0	0	79248	1	199942	16	16	1485	15752	25	1132678	80010	725392	320000	80010	640000	320000	400050	9330632	10738106	0	0	0	200631	0	201232	198225	40602	0	3	41141	1040010	20	320000	640000	20	720000	1600000	200262	199108	1	1	80021	10	9	10	10	80000	80000	10	320014	15	44	25722	0	320016	0	1	0	18	320002	16	44	14	0	0	0	5019	2	16	2	2	201594	80000	2	320000	640000	80010	200477	199969	200893	199389	199490
960024	200232	1546	1	0	0	0	0	0	1	132	103	0	0	0	84567	1	200742	16	16	1715	17364	165	1126983	80155	728001	320240	80097	640952	320324	400485	9295826	10876904	0	0	1	199163	0	201808	199960	43552	0	42	38588	1041135	20	320480	640960	20	721080	1602400	201554	199933	5	1	80021	10	9	10	10	80000	80000	10	320197	17	44	24013	3	320016	1	2	0	16	320002	16	0	14	1	0	0	5019	2	16	2	2	200898	80001	0	320000	640000	80010	199252	200004	198452	196563	199695
960024	201954	1616	1	0	1	0	0	0	0	24	14	0	0	0	83370	1	200204	16	16	1731	17220	25	1123262	80011	727452	320000	80010	640000	320000	400050	9347634	10771598	0	0	0	200275	0	201203	202636	40827	0	3	41253	1040010	20	320000	640000	20	720000	1600000	200326	201138	1	1	80021	10	9	10	10	80000	80000	10	320014	14	44	26065	1	320016	0	1	0	26	320002	16	46	14	0	0	0	5019	2	17	2	2	197763	80000	0	320000	640000	80010	199785	199888	199201	198915	199684
960024	200857	1606	1	0	0	0	0	0	0	42	17	0	0	0	87905	1	200447	16	15	1898	16550	25	1124545	80010	723529	320000	80010	640000	320000	400050	9274885	10888360	0	0	1	201598	0	200539	202077	41366	0	3	38083	1040010	20	320000	640000	20	720000	1600000	203288	200608	1	1	80021	10	9	10	10	80000	80000	10	320015	14	44	26057	0	320016	0	1	0	28	320002	16	42	14	1	0	0	5020	2	16	2	2	198848	80000	0	320000	640000	80010	202125	201522	198547	198529	200817
960024	199388	1593	1	0	1	0	0	0	0	12	17	0	0	0	86663	1	199337	15	16	1320	16627	25	1122961	80011	728350	320000	80010	640000	320000	400050	9208455	10690081	0	0	0	199146	0	198749	200539	42072	0	3	38954	1040010	20	320000	640000	20	720000	1600000	200886	199837	1	1	80021	10	9	10	10	80000	80000	10	320015	15	43	25963	1	320016	1	2	0	20	320002	16	44	14	0	0	0	5019	2	16	2	2	198555	80000	0	320000	640000	80010	200667	199935	199220	200453	200729
960024	200485	1622	1	0	1	0	0	0	0	0	19	0	0	0	96173	1	201355	16	16	1410	16301	25	1126880	80010	727126	320000	80010	640000	320000	400054	9324673	10760901	0	0	0	201599	0	200960	201998	40426	0	3	41198	1040010	20	320000	640000	20	720810	1603600	201048	200084	2	1	80021	10	9	10	10	80000	80000	10	320015	14	44	25917	0	320016	1	1	0	16	320002	16	43	14	0	0	0	5019	2	17	2	2	196659	80000	0	320000	640000	80010	199106	200945	199006	200394	200625
960024	197536	1602	1	0	0	0	0	0	0	132	17	0	0	0	85603	1	199097	16	16	1458	15773	25	1128994	80011	729580	320000	80039	640000	320000	400050	9315054	10694642	0	0	0	200176	0	199096	198599	41758	0	3	41038	1040010	20	320000	640000	20	720000	1600000	201797	200606	1	1	80021	10	9	10	10	80000	80000	10	320014	15	44	26009	0	320016	0	0	0	17	320002	16	44	14	3	0	0	5055	5	44	3	4	200643	81218	0	320000	640000	80010	200459	198679	200147	199331	199444
960024	202048	1625	1	1	0	0	0	4	3	528	281	0	0	0	83665	2	200430	16	16	1469	15896	25	1124093	80011	722727	320000	80010	640000	320000	400050	9323716	10756312	0	0	0	201166	0	200261	200507	39979	0	3	42358	1040010	20	320000	640000	20	720000	1600000	199212	199733	1	1	80021	10	9	10	10	80000	80000	10	320142	17	44	25316	0	320016	1	1	0	17	320002	16	44	14	0	1	0	5019	2	16	2	2	216458	80000	0	320000	640000	80010	200515	198372	200969	198517	202149
960024	200650	1599	1	0	1	0	1	0	0	0	19	0	0	0	94774	1	199061	16	16	1638	17628	25	1122972	80011	721637	320060	80010	640000	320000	400050	9248577	10804034	0	0	0	196806	0	201925	199936	41061	0	3	39690	1040010	20	320000	640000	20	720000	1600000	199984	200374	1	1	80021	10	9	10	10	80000	80000	10	320014	17	44	25840	0	320016	1	0	0	16	320002	16	44	14	3	0	0	5019	2	16	2	2	200844	80000	0	320000	640000	80010	200190	219060	199134	199846	197415
960024	200907	1597	1	0	0	0	1	0	0	0	17	0	0	0	79215	1	199216	16	16	1542	17184	25	1129079	80010	715272	320000	80010	640000	320000	400050	9276871	10862874	0	0	0	201872	0	199585	199492	38885	0	3	39448	1040010	20	320000	640000	20	720000	1600000	196042	201248	1	1	80021	10	9	10	10	80000	80000	10	320014	15	44	24914	0	320016	0	1	0	18	320002	16	44	14	1	0	0	5019	2	17	21	27	201171	80002	0	320000	640000	80010	200879	201225	202564	203238	198917

ST4 (multiple, post-index, 8H)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations