Firestorm: ST4 (single, B) measurements

Code:

  st4 { v0.b, v1.b, v2.b, v3.b }[1], [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 3.000

Issues: 3.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 2.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	mmu table walk instruction (07)	09	l2 tlb miss instruction (0a)	18	1e	1f	22	23	3a	3f	40	46	49	51	schedule uop (52)	schedule simd uop (54)	schedule ldst uop (55)	dispatch simd uop (57)	dispatch ldst uop (58)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	5f	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd store (99)	inst ldst (9b)	l1d tlb access (a0)	l1d cache miss st (a2)	st unit uop (a7)	l1d cache writeback (a8)	ac	af	bc	l1d cache miss st nonspec (c0)	cf	d0	d2	l1i cache miss demand (d3)	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	f5	f6	f7	f8	fd
63007	29649	238	1	30	0	33	0	0	1	0	0	4570	28621	0	0	0	15664	3000	2000	1001	2000	1000	12804	17906	20	23498	28604	28683	3	10	3000	1000	2000	2000	5000	28720	28655	1	1	61001	1000	1000	1000	3	1001	0	1	1000	1	3	13188	10008	6922	3194	17	60	20438	3141	3811	20	58	59	28172	15629	12861	13919	1000	2000	28939	28813	28866	28940	28759
63004	28704	223	0	27	0	26	0	0	0	0	0	4805	28658	0	1	1	15858	3000	2000	1000	2000	1000	12803	17908	8	23558	28531	28673	3	10	3000	1000	2000	2000	5000	28751	28832	1	1	61001	1000	1000	1000	3	1000	0	4	1001	0	3	13156	9460	6962	3134	12	61	20118	3296	3813	17	59	62	28160	15395	12976	13769	1000	2000	28736	28612	28801	28711	28852
63004	28873	224	0	31	0	26	0	18	1	0	0	4731	29142	27	0	1	15864	3000	2000	1000	2000	1000	12804	17905	3	23476	28552	28669	3	10	3000	1000	2000	2000	5000	28706	28604	1	1	61001	1000	1000	1000	0	1000	0	3	1001	0	3	13112	9306	6860	3163	12	56	20282	3205	3816	20	62	57	28430	15940	12912	14085	1000	2000	29057	28984	28938	29008	28857
63004	28972	232	0	36	0	29	0	0	0	0	0	4668	28898	0	1	0	15924	3000	2000	1000	2000	1000	12812	17899	4	23624	28655	28896	3	10	3000	1000	2000	2002	5000	28889	28977	1	1	61001	1000	1000	1000	3	1001	0	1	1000	1	3	13040	9326	6862	3079	12	60	20295	3203	3812	15	57	64	28600	15814	13052	14049	1000	2000	29074	29310	28889	28912	29005
63004	29224	233	0	34	1	25	0	0	0	0	0	4752	28813	0	0	0	15904	3000	2000	1000	2000	1000	12810	17906	5	23495	28689	28944	3	10	3000	1000	2002	2000	5000	28831	28819	1	1	61001	1000	1000	1000	2	1001	0	0	1000	1	0	13171	9371	6957	3116	15	62	20091	3198	3812	21	52	56	28240	15613	12953	13828	1000	2000	28904	28839	28852	28946	28920
63004	28686	224	0	24	0	26	0	0	1	0	0	4660	28807	0	0	0	15847	3000	2000	1000	2000	1000	12810	17911	5	23472	28558	28705	3	31	3000	1000	2000	2000	5000	28907	28760	1	1	61001	1000	1000	1000	2	1000	0	0	1000	0	2	13022	9351	6936	3129	11	50	20238	3228	3821	16	56	61	28331	15809	12967	13656	1000	2000	28928	28804	28917	28802	28979
63004	28826	224	0	21	0	28	0	0	0	0	0	4454	28744	0	1	0	15753	3000	2000	1000	2000	1000	12811	17907	6	23536	28662	28838	3	10	3000	1000	2000	2000	5000	28779	28781	1	1	61001	1000	1000	1000	3	1000	0	0	1001	0	2	13038	9455	6856	3085	13	57	20207	3209	3816	20	57	52	28189	15684	13223	13962	1000	2000	28934	28915	28848	28725	28897
63004	29036	223	0	30	0	26	1	0	0	0	0	4706	28726	0	1	0	15823	3000	2000	1000	2000	1000	12806	17906	5	23567	28689	28859	3	10	3000	1001	2000	2000	5000	28858	28807	1	1	61001	1000	1000	1000	2	1000	0	1	1000	0	3	13002	9357	6841	3095	13	56	20208	3194	3818	7	59	55	28237	15669	12519	14017	1000	2000	28903	28996	29254	28938	28764
63004	28936	224	0	31	0	27	0	0	1	0	0	4622	28633	0	0	0	16003	3000	2000	1000	2000	1000	12804	17903	5	23521	28698	28785	3	10	3000	1000	2000	2000	5000	28758	28725	1	1	61001	1000	1000	1000	2	1000	1	0	1000	0	2	13066	9301	6936	3077	12	66	20247	3200	3816	25	57	61	28160	15444	13127	13829	1000	2000	28930	28815	28916	28854	28913
63004	28833	223	0	25	1	27	0	0	1	0	0	4621	28740	0	0	1	15797	3000	2000	1000	2000	1000	12805	17903	7	23516	28619	28983	3	10	3000	1000	2000	2000	5000	28880	28729	1	1	61001	1000	1000	1000	0	1000	0	0	1000	0	3	13070	9518	6987	3147	14	61	20169	3217	3817	20	56	55	28315	15619	12985	13871	1000	2000	28854	28811	28747	28906	28797

Count: 8

Code:

  st4 { v0.b, v1.b, v2.b, v3.b }[1], [x6]
  st4 { v0.b, v1.b, v2.b, v3.b }[1], [x6]
  st4 { v0.b, v1.b, v2.b, v3.b }[1], [x6]
  st4 { v0.b, v1.b, v2.b, v3.b }[1], [x6]
  st4 { v0.b, v1.b, v2.b, v3.b }[1], [x6]
  st4 { v0.b, v1.b, v2.b, v3.b }[1], [x6]
  st4 { v0.b, v1.b, v2.b, v3.b }[1], [x6]
  st4 { v0.b, v1.b, v2.b, v3.b }[1], [x6]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5643

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	22	24	37	3a	3f	46	49	4e	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	rob full (74)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd store (99)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
240207	45330	350	0	0	0	0	0	0	0	0	0	13022	0	45337	0	0	17	854	25	251998	100	172675	80000	100	160000	80000	500	2084148	3297594	1	45305	45077	45396	15029	0	3	14938	240100	200	80000	160000	200	160000	400000	45181	45427	1	1	80201	100	99	100	100	80000	80000	100	80000	0	34	2431	0	80002	1	0	2	80000	2	34	0	0	5110	0	1	16	1	1	44949	0	0	0	80000	160000	100	45212	44795	45369	45415	45295
240204	46279	375	1	0	1	0	0	12	19	0	0	12136	1	45449	16	16	2	1003	25	252718	100	172117	80060	100	160000	80000	500	2088820	3295098	0	44754	45259	45369	14493	0	3	14942	240100	200	80000	160240	200	160000	400000	45170	44851	1	1	80201	100	99	100	100	80000	80000	100	80014	14	36	2217	0	80016	0	1	17	80002	16	36	14	0	5110	0	1	16	1	1	45350	0	0	0	80000	160000	100	44794	45062	45270	45542	44932
240204	45213	354	1	1	0	0	0	0	19	0	0	12133	1	44673	16	16	3	1032	25	251872	100	172281	80000	100	160000	80000	500	2079824	3319518	0	44965	45095	45154	15219	0	3	14598	240100	200	80000	160000	200	160000	400000	45229	45114	1	1	80201	100	99	100	100	80000	80000	100	80015	14	0	2118	0	80016	0	1	20	80002	16	36	14	0	5110	0	1	16	2	1	45291	0	0	0	80000	160000	100	45559	45438	45299	45117	45031
240204	45083	350	1	1	1	0	0	0	21	0	0	11823	1	45076	15	16	16	761	25	252130	100	172968	80000	100	160000	80000	500	2088291	3323323	0	45293	45314	45119	15065	0	3	14921	240100	200	80000	160000	200	160000	400000	45031	44762	1	1	80201	100	99	100	100	80000	80000	100	80015	14	36	2489	0	80016	0	1	18	80000	16	0	14	2	5110	0	1	16	1	1	45409	0	0	0	80000	160000	100	44875	45316	45203	45089	45362
240204	45218	350	1	1	1	0	0	6	19	0	0	11930	1	45155	16	16	8	797	25	252967	100	172865	80000	100	160000	80000	500	2064644	3295186	0	45297	45212	45165	15053	0	3	14706	240100	200	80000	160000	200	160000	400000	44736	45561	1	1	80201	100	99	100	100	80000	80000	100	80015	14	35	2335	0	80016	0	0	14	80002	2	34	0	0	5110	0	1	16	1	1	45013	0	0	0	80000	160000	100	44905	44588	44976	44855	44976
240204	45276	350	0	0	0	0	0	0	2	0	0	12590	0	44964	0	16	14	834	25	251585	100	172379	80000	100	160000	80000	500	2083884	3319443	0	45208	45187	45226	15151	0	3	15168	240100	200	80000	160000	200	160000	400000	45066	45349	1	1	80201	100	99	100	100	80000	80000	100	80015	14	36	2316	1	80016	1	0	21	80002	14	36	14	1	5110	0	1	16	1	1	44952	0	0	0	80000	160000	100	44803	45072	45394	45260	45246
240204	45220	350	1	0	1	0	0	0	17	0	0	12235	1	44882	16	16	8	679	25	252252	100	171856	80000	100	160000	80000	500	2070093	3290265	0	44719	44941	44917	14810	0	3	14953	240100	200	80000	160000	200	160000	400000	45229	44823	1	1	80201	100	99	100	100	80000	80000	100	80015	14	36	2148	0	80016	0	1	20	80002	16	36	14	0	5110	0	1	16	1	1	45187	0	4	0	80000	160000	100	45633	44903	45233	45224	45000
240204	45071	349	1	1	1	0	0	0	14	0	0	12274	1	45023	16	16	6	866	25	256141	100	173084	80000	100	160000	80000	500	2075545	3319144	0	45020	44956	45478	14878	0	3	15522	240100	200	80000	160000	200	160000	400000	45131	45207	1	1	80201	100	99	100	100	80000	80000	100	80014	15	36	2506	0	80014	0	0	15	80000	16	36	14	0	5110	0	1	16	1	1	45466	0	0	1	80000	160000	100	45256	44760	44850	48985	45098
240204	45036	348	1	1	1	0	0	0	18	0	0	12425	1	45236	0	16	16	930	25	252157	100	171621	80000	100	160000	80000	500	2088785	3328688	0	45146	44798	44896	14761	0	3	15281	240100	200	80000	160000	200	160000	400000	45383	45199	1	1	80201	100	99	100	100	80000	80000	100	80014	15	36	2468	0	80016	0	0	14	80002	16	36	14	1	5110	0	1	16	1	1	44978	0	0	0	80000	160000	100	45307	45054	44871	45193	45612
240204	45060	347	1	1	0	0	0	0	19	1	0	11895	1	45235	0	16	13	923	25	251491	100	172839	80000	100	160000	80000	500	2076595	3340771	0	45183	44942	45359	15232	0	3	15317	240100	200	80000	160000	200	160000	400000	44791	45439	1	1	80201	100	99	100	100	80000	80000	100	80015	15	36	2091	0	80016	0	1	17	80000	16	36	14	0	5110	0	1	16	1	1	45380	0	0	0	80000	160000	100	45277	45544	45130	45322	44987

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5648

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	l2 tlb miss instruction (0a)	19	1e	1f	22	23	24	37	3a	3f	46	49	4e	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	rob full (74)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd store (99)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d cache miss st (a2)	a4	st unit uop (a7)	l1d cache writeback (a8)	ac	af	bc	l1d cache miss st nonspec (c0)	cf	d2	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
240027	44806	362	0	0	0	0	3	0	0	0	11804	1	44980	16	16	69	736	25	252889	10	172076	80060	10	160000	80000	50	2066633	3272874	0	44861	45039	44885	14881	0	3	15056	240010	20	80000	160000	20	160000	400602	43057	44859	1	1	80021	10	9	10	10	80000	80000	10	80000	42	2361	80002	0	2	80002	2	42	5020	0	2	16	1	1	45117	80000	160000	10	45181	44618	44665	45166	44669
240024	45037	348	0	0	0	0	3	0	0	0	13405	1	44792	16	0	20	906	25	251771	10	172868	80000	10	160000	80000	50	2089436	3333925	0	45073	45096	45511	14855	0	3	15015	240010	20	80000	160000	20	160000	400000	45019	45134	1	1	80021	10	9	10	10	80000	80000	10	80000	42	2201	80000	0	2	80002	2	42	5020	0	1	16	2	1	45239	80000	160000	10	45247	45205	45093	45312	45115
240024	45329	348	0	0	0	0	3	0	0	0	13018	0	45180	16	16	13	876	25	252527	10	172718	80000	10	160000	80000	50	2082861	3283296	0	44988	45259	45163	15057	0	3	15417	240010	20	80000	160000	20	160000	400000	44853	45213	1	1	80021	10	9	10	10	80000	80000	10	80000	42	2371	80002	0	3	80002	2	42	5022	0	2	16	2	1	44998	80000	160000	10	45142	45218	44895	45050	44944
240024	45194	349	0	0	0	0	3	1	0	0	12566	0	45257	16	16	1	1014	25	252374	10	172977	80000	10	160000	80000	50	2095859	3286658	0	45109	44771	44630	14703	0	3	15616	240010	20	80000	160000	20	160000	400000	45161	45240	1	1	80021	10	9	10	10	80000	80000	10	80000	42	2206	80002	0	2	80002	2	42	5022	0	2	16	1	1	45393	80000	160000	10	45044	45332	45517	45183	45158
240024	44839	362	0	0	0	0	0	1	0	0	12077	0	44865	16	16	24	849	25	250730	10	172133	80000	10	160000	80000	50	2090804	3316105	0	44881	45173	44945	14846	0	3	15058	240010	20	80000	160000	20	160000	400000	45268	45192	1	1	80021	10	9	10	10	80000	80000	10	80000	34	2298	80002	0	5	80002	2	34	5020	0	2	16	2	1	45092	80000	160000	10	45466	45053	44927	45193	44741
240024	45453	350	0	0	0	0	0	0	0	0	12092	0	45384	16	16	12	856	25	251778	10	172471	80000	10	160000	80000	50	2084201	3329796	0	44866	45329	45299	14831	0	3	14699	240010	20	80000	160000	20	160000	400000	44768	44683	4	1	80021	10	9	10	10	80000	80000	10	80000	34	2337	80002	0	2	80002	2	34	5020	0	2	16	2	1	45448	80000	160000	10	45113	44823	44841	45347	45496
240024	45093	351	0	0	0	0	0	0	0	0	11774	0	45394	16	16	11	857	25	252176	10	172197	80000	10	160000	80000	50	2076776	3330597	0	44995	44973	44704	15192	0	3	15054	240010	20	80000	160000	20	160000	400000	45134	45187	1	1	80021	10	9	10	10	80000	80000	10	80000	34	2481	80002	0	2	80000	0	34	5020	0	1	16	1	1	44869	80000	160000	10	45216	44808	45152	45337	45037
240024	44704	349	0	0	0	0	2	0	0	0	12086	1	45218	16	16	18	911	25	250855	10	173103	80000	10	160000	80000	50	2074509	3292333	0	45094	45200	45023	14974	0	3	15192	240010	20	80000	160000	20	160000	400000	44846	45263	1	1	80021	10	9	10	10	80000	80000	10	80000	34	2224	80000	0	0	80000	0	0	5020	0	2	16	2	2	45143	80000	160000	10	44914	45166	44960	45373	44902
240024	45040	351	0	0	0	0	2	0	0	0	12345	0	44918	16	16	2	873	25	252896	10	171771	80000	10	160000	80000	50	2087502	3290581	0	45161	45063	45045	14884	0	3	14644	240010	20	80000	160000	20	160000	400000	45124	45010	1	1	80021	10	9	10	10	80000	80000	10	80000	34	2237	80000	0	5	80002	2	34	5020	0	1	16	1	2	44956	80000	160000	10	44962	45089	45067	45272	45028
240024	45098	352	0	0	0	0	5	0	0	0	12093	0	45033	16	16	4	841	25	251432	10	171966	80000	10	160000	80000	50	2076718	3348753	0	45181	44941	45653	14646	0	3	14992	240010	20	80000	160000	20	160000	400000	44916	44681	1	1	80021	10	9	10	10	80000	80000	10	80000	34	2168	80002	0	0	80002	2	34	5022	0	2	16	2	1	45235	80000	160000	10	44931	45209	45530	45106	45038

ST4 (single, B)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations