Firestorm: ST4 (single, D) measurements

Code:

  st4 { v0.d, v1.d, v2.d, v3.d }[1], [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 4.000

Issues: 4.000

Integer unit issues: 0.000

Load/store unit issues: 2.000

SIMD/FP unit issues: 2.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss instruction (0a)	19	1e	1f	22	24	3a	3f	46	49	51	schedule uop (52)	schedule simd uop (54)	schedule ldst uop (55)	dispatch simd uop (57)	dispatch ldst uop (58)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	5f	60	61	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd store (99)	inst ldst (9b)	l1d tlb access (a0)	l1d cache miss st (a2)	st unit uop (a7)	l1d cache writeback (a8)	ac	af	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	cf	d0	d2	l1i cache miss demand (d3)	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	f5	f6	f7	f8	fd
64007	29068	233	7	0	5	0	9	3	0	0	5004	28345	2	2	17143	4000	2000	2000	2000	2000	21617	16000	23	0	0	21803	28133	28468	3	10	4000	2002	2000	4000	4000	28278	28191	1	1	61001	1000	1000	2000	0	2002	0	2	2000	0	4	0	13696	9799	7250	3304	0	45	19418	3246	3809	25	48	53	27935	14747	12402	13401	2000	2000	28367	28383	28487	28475	28482
64004	28436	214	1	0	2	0	9	0	0	0	4878	28474	2	2	17344	4000	2000	2000	2000	2000	21617	16000	19	0	0	21779	28248	28514	3	10	4000	2000	2000	4000	4000	28427	28462	1	1	61001	1000	1000	2000	6	2002	0	2	2000	2	6	0	13759	9892	7189	3410	1	45	19502	3281	3810	27	46	50	27981	14823	12319	13654	2000	2000	28485	28520	28372	28426	28476
64004	28438	213	2	0	2	0	0	0	0	0	4916	28639	0	0	17400	4000	2000	2000	2000	2000	21635	16000	14	0	0	21802	28229	28638	3	10	4000	2000	2000	4000	4000	28443	28255	1	1	61001	1000	1000	2000	0	2002	0	2	2000	0	6	0	13543	10013	7151	3432	0	48	19504	3229	3807	21	46	47	27972	14183	12103	13120	2000	2000	28334	28436	28327	28520	28484
64004	28642	213	1	0	2	0	0	3	0	0	4960	28174	0	2	17495	4000	2000	2000	2000	2000	21615	16000	13	0	0	21796	28153	28534	3	10	4000	2000	2000	4000	4000	28298	28408	1	1	61001	1000	1000	2000	6	2002	0	2	2002	2	6	0	13640	10118	7135	3320	1	46	19538	3323	3808	28	51	48	27935	14501	12417	13619	2000	2000	28263	28312	28580	28329	28251
64004	28234	213	1	0	2	0	0	3	0	1	5076	28171	0	2	17344	4000	2000	2000	2000	2000	21631	16000	14	0	0	21829	28255	28368	3	10	4000	2000	2000	4000	4000	28315	28295	1	1	61001	1000	1000	2000	0	2002	0	2	2000	2	6	0	13619	10109	7155	3257	0	45	19366	3315	3812	24	53	46	27973	14016	11986	13861	2000	2000	28283	28460	28602	28372	28200
64004	28317	213	1	0	1	0	30	3	0	0	5108	28164	2	2	17329	4000	2000	2000	2000	2000	21618	16000	19	0	0	21800	28581	28959	3	10	4000	2000	2000	4000	4000	28838	29023	1	1	61001	1000	1000	2000	6	2002	0	50	2002	2	6	0	13455	9896	7080	3367	1	52	19544	3368	3803	23	51	54	27973	14993	12477	13455	2000	2000	28586	28362	28847	28644	28703
64004	27946	212	0	0	1	0	39	3	0	0	5050	28306	2	2	17338	4000	2000	2000	2000	2000	21613	16000	11	0	0	21861	28379	28352	3	10	4000	2000	2000	4000	4000	28453	28582	1	1	61001	1000	1000	2000	6	2000	0	2	2002	0	6	0	13699	10085	7157	3483	0	46	19269	3322	3809	25	52	47	27984	14285	12437	13678	2000	2000	28168	28503	28323	28277	28590
64004	28417	211	2	0	3	0	48	3	0	0	4969	28344	2	0	17592	4000	2000	2000	2000	2000	21613	16000	18	0	0	21790	28251	28332	3	10	4000	2000	2000	4000	4000	28347	28364	1	1	61001	1000	1000	2000	6	2002	0	0	2000	2	6	0	13555	9859	7086	3371	0	45	19426	3302	3802	24	46	46	27910	14495	11977	13153	2000	2000	28339	28405	28198	28426	28522
64004	28515	220	3	0	1	0	12	3	0	1	5064	28045	0	2	17438	4000	2000	2000	2000	2000	21607	16000	12	0	0	21816	28220	28434	3	10	4000	2000	2000	4000	4000	28285	28300	1	1	61001	1000	1000	2000	6	2002	0	2	2002	2	6	0	13522	10378	7083	3360	0	45	19275	3135	3812	29	52	55	27997	14640	12192	13515	2000	2000	28551	28597	28532	28468	28386
64004	28381	213	4	0	4	0	12	3	0	0	4783	28316	0	2	17131	4000	2000	2000	2000	2000	21627	16000	12	0	0	21780	28275	28366	3	10	4000	2000	2000	4000	4000	28259	28416	1	1	61001	1000	1000	2000	6	2000	0	2	2000	2	6	2	13807	10028	7139	3353	1	48	19573	3232	3806	24	47	46	28072	15042	12149	13418	2000	2000	28429	28249	28566	28400	28529

Count: 8

Code:

  st4 { v0.d, v1.d, v2.d, v3.d }[1], [x6]
  st4 { v0.d, v1.d, v2.d, v3.d }[1], [x6]
  st4 { v0.d, v1.d, v2.d, v3.d }[1], [x6]
  st4 { v0.d, v1.d, v2.d, v3.d }[1], [x6]
  st4 { v0.d, v1.d, v2.d, v3.d }[1], [x6]
  st4 { v0.d, v1.d, v2.d, v3.d }[1], [x6]
  st4 { v0.d, v1.d, v2.d, v3.d }[1], [x6]
  st4 { v0.d, v1.d, v2.d, v3.d }[1], [x6]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0006

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	1f	23	24	37	3a	3f	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd store (99)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
320207	80070	620	0	1	0	0	2	0	0	0	0	0	0	0	6098	1	80030	16	16	0	25	327409	100	163774	160060	100	160000	160000	500	2225760	1297546	0	80024	80219	80045	0	3	27	320100	200	160000	160000	200	320000	320000	80045	80045	1	1	80201	100	99	100	100	80000	80000	100	160062	0	0	0	0	160002	0	0	8	160002	2	0	0	0	0	5112	5	17	4	5	80042	160000	160000	100	80046	80046	80046	80050	80050
320204	80045	620	0	1	0	0	1	0	0	1	12	9	0	0	3701	1	80030	16	16	0	25	324478	100	165035	160000	100	160000	160000	500	2559868	1284211	0	80025	80058	80051	0	3	31	320100	200	160000	160000	200	320000	320000	80050	80050	1	1	80201	100	99	100	100	80000	80000	100	160015	14	34	0	1	160016	0	1	16	160002	16	36	14	1	0	5111	3	17	5	3	80047	160000	160000	100	80046	80049	80046	80046	80046
320204	80052	620	0	1	0	0	1	0	0	0	0	3	0	0	6612	1	80030	16	16	0	25	326743	100	160350	160000	100	160000	160000	500	2266562	1296479	0	80024	80049	80046	0	3	27	320100	200	160000	160000	200	320000	320000	80045	80045	1	1	80201	100	99	100	100	80000	80000	100	160000	0	34	0	0	160002	0	0	11	160002	2	34	0	0	0	5112	3	17	5	5	80042	160000	160000	100	80046	80045	80046	80050	80046
320204	80122	621	0	1	0	0	1	0	0	0	3	3	0	0	4646	1	80030	16	16	0	25	323034	100	164196	160000	100	160000	160000	500	2225760	1293267	0	80024	80045	80045	0	3	26	320100	200	160000	160000	200	320000	320000	80045	80045	1	1	80201	100	99	100	100	80000	80000	100	160000	0	34	0	0	160002	0	0	2	160002	2	34	0	0	0	5112	5	17	3	5	80046	160000	160000	100	80049	80046	80050	80046	80046
320204	80045	620	0	1	0	0	1	0	0	0	0	0	0	0	6560	1	80034	16	16	0	25	325706	100	166129	160000	100	160000	160000	500	2302475	1292786	0	80025	80045	80045	0	3	31	320100	200	160000	160000	200	320000	320000	80045	80045	1	1	80201	100	99	100	100	80000	80000	100	160000	0	34	0	0	160002	0	0	0	160002	2	34	0	0	0	5112	4	17	4	5	80046	160000	160000	100	80046	80046	80050	80046	80046
320204	80045	620	0	1	0	0	1	0	0	0	12	3	0	0	4933	1	80030	16	16	0	25	324292	100	163906	160000	100	160000	160000	500	2202347	1296929	0	80024	80045	80045	0	3	27	320100	200	160000	160000	200	320000	320000	80045	80045	1	1	80201	100	99	100	100	80000	80000	100	160242	0	0	0	0	160002	0	0	2	160000	0	34	0	0	0	5111	5	17	4	5	80042	160000	160000	100	80062	80053	80051	80059	80059
320204	80052	620	1	1	0	1	1	0	0	0	0	19	0	0	4539	2	80043	16	16	0	25	327147	100	160491	160000	100	160000	160000	500	3599397	1299377	0	80033	80051	80049	0	3	40	320100	200	160000	160000	200	320000	320000	80059	80059	1	1	80201	100	99	100	100	80000	80000	100	160014	14	36	3	1	160016	0	1	17	160002	16	37	14	0	0	5112	5	17	5	5	80055	160000	160000	100	80061	80051	80059	80058	80059
320204	80050	620	1	1	1	1	1	1	0	0	0	14	0	0	4711	2	80045	16	16	2	25	325621	100	165616	160000	100	160000	160000	500	2399920	1301846	0	80025	80058	80058	0	3	32	320100	200	160000	160000	200	320000	320000	80058	80058	1	1	80201	100	99	100	100	80000	80000	100	160000	0	36	0	0	160002	1	0	2	160002	2	34	0	0	0	5113	3	17	5	5	80042	160000	160000	100	80046	80046	80047	80046	80045
320204	80049	620	0	1	0	0	1	0	0	0	0	3	1	0	3886	1	80034	16	16	0	25	325960	100	167111	160000	100	160000	160000	500	2239633	1303069	0	80025	80045	80045	0	3	31	320100	200	160000	160000	200	320000	320000	80045	80045	1	1	80201	100	99	100	100	80000	80000	100	160000	0	34	0	0	160000	0	0	2	160002	2	34	0	0	0	5112	3	17	5	5	80042	160000	160000	100	80053	80046	80046	80046	80046
320204	80045	620	0	1	0	0	1	0	0	0	15	3	0	0	5028	1	80030	16	16	0	25	322293	100	165796	160000	100	160000	160000	500	2559886	1295427	0	80026	80058	80050	0	3	32	320100	200	160000	160000	200	320000	320000	80050	80050	1	1	80201	100	99	100	100	80000	80000	100	160015	14	36	0	1	160014	1	1	21	160002	16	36	14	0	0	5112	5	17	5	5	80047	160000	160000	100	80046	80046	80050	80046	80046

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0006

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	22	37	3a	3f	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	61	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	91	inst branch cond (94)	inst int alu (97)	inst simd store (99)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	branch cond mispred nonspec (c5)	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
320027	80058	621	0	0	0	0	0	0	12	0	0	5341	0	80030	16	16	0	25	324492	10	164176	160000	10	160000	160000	50	2233147	1280036	0	80034	0	80050	80045	0	3	30	320010	20	160000	160000	20	320000	320000	80045	80045	1	1	80021	10	9	0	10	10	80000	80000	10	160000	0	34	0	0	160002	0	0	0	160000	2	34	0	0	0	5019	0	3	17	4	4	80042	160000	160000	10	80046	80046	80046	80046	80046
320024	80048	621	0	0	0	0	0	0	12	3	1	4877	0	80034	16	16	0	25	325211	10	165354	160000	10	160000	160000	50	2236929	1297148	0	80024	0	80045	80045	0	3	27	320010	20	160000	160000	20	320000	320000	80062	80045	1	1	80021	10	9	0	10	10	80000	80000	10	160000	0	34	0	0	160002	0	0	2	160002	2	34	0	0	0	5019	0	3	17	4	4	80042	160000	160000	10	80045	80046	80046	80046	80050
320024	80052	620	0	0	0	0	0	0	0	3	0	5628	0	80030	0	16	0	25	325716	10	165508	160000	10	160000	160000	50	2153660	1297236	0	80024	0	80046	80046	0	3	27	320010	20	160000	160000	20	320000	320000	80045	80122	4	1	80021	10	9	0	10	10	80000	80000	10	160000	0	34	0	0	160000	0	0	974	160002	2	34	0	0	0	5019	0	3	17	5	3	80042	160000	160000	10	80046	80050	80046	80046	80049
320024	80049	621	0	0	0	0	0	0	0	3	0	4394	0	80030	16	16	0	25	325334	10	165219	160000	10	160000	160000	50	2156661	1301570	0	80023	0	80049	80045	0	3	32	320010	20	160000	160000	20	320000	320000	80049	80045	1	1	80021	10	9	0	10	10	80000	80000	10	160000	0	34	0	0	160002	0	0	20	160002	2	34	0	0	0	5019	0	3	17	3	4	80042	160000	160000	10	80046	80045	80046	80049	80046
320024	80045	620	0	0	0	0	0	0	12	3	0	5017	0	80030	16	16	0	25	328317	10	165286	160000	10	160000	160000	50	2239734	1300850	0	80025	0	80058	80045	0	3	34	320010	20	160000	160000	20	320000	320000	80045	80045	1	1	80021	10	9	0	10	10	80000	80000	10	160000	0	0	0	0	160000	0	0	2	160002	2	34	0	0	0	5019	0	4	17	4	4	80042	160000	160000	10	80046	80046	80046	80047	80046
320024	80049	620	0	0	0	0	0	0	0	6	0	5613	0	80036	16	16	0	25	325114	10	164119	160000	10	160000	160000	50	2229065	1301755	0	80024	0	80045	80045	0	3	27	320010	20	160000	160000	20	320000	320000	80045	80045	1	1	80021	10	9	0	10	10	80000	80000	10	160000	0	34	0	0	160002	1	0	0	160002	2	34	0	0	0	5019	0	4	17	4	4	80042	160000	160000	10	80050	80046	80046	80050	80046
320024	80045	620	0	0	0	0	0	0	0	9	0	4654	0	80030	16	16	0	25	325310	10	165396	160000	10	160000	160000	50	2212372	1295524	0	80024	0	80045	80045	0	3	27	320010	20	160000	160000	20	320000	320000	80045	80045	1	1	80021	10	9	0	10	10	80000	80000	10	160000	0	34	0	0	160000	0	0	5	160000	0	34	0	0	0	5019	0	3	17	3	3	80042	160000	160000	10	80046	80045	80050	80047	80047
320024	80045	620	0	0	0	0	0	0	12	3	0	3953	0	80034	16	16	0	25	326407	10	164232	160000	10	160000	160000	50	2128584	1301529	0	80024	0	80049	80048	0	3	27	320010	20	160000	160000	20	320000	320000	80045	80704	1	1	80021	10	9	0	10	10	80000	80000	10	160000	0	34	0	0	160002	0	0	3	160002	2	34	0	0	0	5019	0	4	212	3	4	80041	160000	160000	10	80050	80046	80046	80050	80046
320024	80045	621	0	0	0	0	0	0	0	3	0	5286	0	80030	16	16	0	25	325214	10	164210	160000	10	160000	160000	50	2237209	1293767	0	80025	0	80045	80045	0	3	27	320010	20	160000	160000	20	320000	320000	80049	80064	1	1	80021	10	9	0	10	10	80000	80000	10	160000	0	0	0	0	160002	0	0	5	160000	0	34	0	0	0	5019	0	4	17	5	3	80042	160000	160000	10	80046	80046	80049	80046	80046
320024	80045	620	0	0	0	0	0	0	45	3	0	4942	0	80030	16	16	0	25	325301	10	164433	160000	10	160000	160000	50	2204658	1297774	0	80025	0	80045	80045	0	3	27	320010	20	160000	160000	20	320000	320000	80045	80045	1	1	80021	10	9	0	10	10	80000	80000	10	160000	0	0	0	0	160002	1	0	5	160002	2	34	0	0	0	5019	0	4	17	3	3	80041	160000	160000	10	80045	80046	80046	80046	80046

ST4 (single, D)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations