Firestorm: ST4 (single, H) measurements

Code:

  st4 { v0.h, v1.h, v2.h, v3.h }[1], [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 3.000

Issues: 3.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 2.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	mmu table walk instruction (07)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	1f	22	23	24	3a	3f	46	49	51	schedule uop (52)	schedule simd uop (54)	schedule ldst uop (55)	dispatch simd uop (57)	dispatch ldst uop (58)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	5f	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd store (99)	inst ldst (9b)	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	c2	c9	cf	d0	d2	l1i cache miss demand (d3)	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	f5	f6	f7	f8	fd
63007	29504	236	3	2	0	5	0	0	0	3	0	0	0	0	4827	29317	0	1	16474	3000	2000	1000	2000	1000	12810	17898	7	23587	29145	29365	3	10	3000	1000	2000	2000	5000	29400	29447	1	1	61001	1000	1000	1000	0	2	0	1000	1	0	0	1000	0	0	0	0	13386	9466	6919	3133	2	50	20780	3316	3817	13	47	47	28706	16075	13844	14391	1000	2000	29468	29490	29481	29446	29362
63004	29444	236	0	4	0	1	0	0	0	18	0	0	0	0	4631	29506	0	0	16536	3000	2000	1000	2000	1000	12798	17903	6	23577	29260	29549	3	10	3000	1000	2000	2000	5000	29455	29395	1	1	61001	1000	1000	1000	0	0	0	1000	1	0	0	1000	0	3	0	0	13125	9511	7006	3133	1	51	20796	3320	3821	9	51	52	28803	16233	13446	14469	1000	2000	29474	29492	29485	29416	29565
63004	29513	237	0	2	0	3	0	0	0	120	0	0	0	0	4616	29425	0	0	16608	3000	2000	1000	2000	1000	12797	17910	5	23558	29306	29641	3	66	3000	1000	2000	2000	5000	29393	29510	1	1	61001	1000	1000	1000	0	3	5	1000	1	0	0	1000	0	3	0	0	13391	9476	6920	3149	0	52	20888	3274	3812	14	53	47	28793	16337	13664	14441	1000	2000	29573	29462	29516	29693	29485
63004	29533	237	0	2	0	2	0	0	0	111	0	0	0	0	4551	29406	0	0	16612	3000	2000	1000	2000	1000	12800	17898	6	23612	29389	29559	3	10	3000	1000	2000	2000	5000	29544	29411	1	1	61001	1000	1000	1000	0	2	0	1000	0	0	3	1000	0	3	0	0	13198	9490	6942	3153	2	48	20942	3365	3812	14	51	46	28830	16402	13757	14260	1000	2000	29684	29463	29646	29567	29578
63004	29640	238	0	1	0	4	0	0	0	99	0	1	0	0	4647	29700	1	1	16574	3006	2000	1000	2000	1001	12903	17919	4	23575	29457	29980	3	10	3000	1000	2000	2000	5000	29562	29638	4	1	61001	1000	1000	1000	2	3	0	1000	1	0	395	1000	0	3	0	114	13226	9390	6991	3134	1	44	20952	3241	3816	11	44	44	28857	16312	13607	14607	1000	2000	29527	29523	29610	29537	29717
63004	29508	236	0	4	0	3	0	1	0	354	1	0	0	0	4659	29598	0	0	16729	3003	2000	1000	2000	1000	12805	17921	6	23586	29428	29575	7	44	3000	1000	2002	2002	5000	29671	29560	5	1	61001	1000	1000	1003	2	0	3	1000	0	2	393	1002	0	2	0	0	13282	9372	6900	3119	1	44	20882	3352	3811	17	45	44	28804	16269	13579	14416	1000	2000	29549	29591	29529	29523	29582
63004	29664	236	0	2	0	0	0	0	0	702	1	0	0	0	4630	29564	0	0	16848	3000	2000	1000	2000	1000	12817	17900	0	23535	29187	29423	3	10	3000	1000	2000	2000	5000	29285	29468	1	1	61001	1000	1000	1000	0	2	0	1000	1	0	0	1000	0	0	0	0	12952	9185	6832	3081	1	42	21092	3157	3808	52	52	45	29426	16382	13735	14620	1000	2000	30228	30231	30301	30303	30371
63004	30318	243	0	3	0	2	0	1	0	33	0	0	0	0	4667	29479	1	1	16359	3000	2000	1000	2000	1000	12801	17907	5	23554	29200	29292	26	10	3003	1000	2000	2000	5000	29553	29660	1	1	61001	1000	1000	1002	0	0	0	1000	1	0	3	1000	0	2	0	0	13143	9445	6960	3122	1	42	20741	3221	3811	12	46	45	28540	16104	13577	14236	1000	2000	29405	29479	29331	29279	29340
63004	29436	227	0	2	0	2	0	0	0	138	0	0	0	0	4769	29335	0	1	16311	3000	2000	1000	2000	1000	12798	17897	2	23505	29385	29494	3	10	3000	1000	2000	2000	5000	29439	29406	1	1	61001	1000	1000	1000	0	2	0	1000	0	0	3	1000	0	3	0	0	13383	9334	6904	3193	2	44	20818	3259	3806	8	43	44	28560	15952	13497	14289	1000	2000	29475	29333	29311	29441	29334
63004	29335	227	0	4	0	2	0	0	1	24	1	0	0	0	4735	29363	1	0	16441	3000	2000	1000	2000	1000	12806	17899	5	23503	29167	29326	3	10	3000	1000	2000	2000	5000	29358	29375	1	1	61001	1000	1000	1002	0	2	0	1000	0	0	3	1000	0	3	0	980	13187	9477	6989	3218	1	49	20806	3387	3814	12	47	49	28745	16144	13906	14484	1000	2000	29475	29362	29567	29704	28780

Count: 8

Code:

  st4 { v0.h, v1.h, v2.h, v3.h }[1], [x6]
  st4 { v0.h, v1.h, v2.h, v3.h }[1], [x6]
  st4 { v0.h, v1.h, v2.h, v3.h }[1], [x6]
  st4 { v0.h, v1.h, v2.h, v3.h }[1], [x6]
  st4 { v0.h, v1.h, v2.h, v3.h }[1], [x6]
  st4 { v0.h, v1.h, v2.h, v3.h }[1], [x6]
  st4 { v0.h, v1.h, v2.h, v3.h }[1], [x6]
  st4 { v0.h, v1.h, v2.h, v3.h }[1], [x6]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5639

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	1f	22	23	24	37	3a	3f	46	49	4e	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	rob full (74)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst simd store (99)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	ac	af	bc	l1d cache miss st nonspec (c0)	c2	cd	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
240207	45091	350	0	0	0	0	0	12	3	0	0	0	11792	0	45448	0	16	13	729	25	252657	100	171479	80000	100	160000	80000	500	2085968	3320578	0	44794	45184	45221	15244	0	3	15362	240100	200	80000	160000	200	160000	400000	44926	45231	1	1	80201	100	99	100	100	0	80000	80000	100	80000	0	42	2437	0	80002	0	78	80002	2	42	0	0	5110	0	14	16	13	13	45314	0	0	80000	160000	100	45231	45103	45067	45221	45321
240204	45109	351	0	0	0	0	0	9	3	0	0	0	12037	0	45313	16	16	14	896	25	251695	100	172389	80000	100	160000	80000	500	2072633	3291957	0	44840	45158	49550	15003	0	3	15223	240100	200	80000	160000	200	160000	400000	45293	44969	1	1	80201	100	99	100	100	0	80000	80000	100	80000	0	42	2406	0	80002	0	24	80002	2	42	0	0	5110	0	14	16	13	13	45378	0	0	80000	160000	100	44832	44910	45337	45001	45267
240204	44875	363	0	0	0	0	0	12	3	0	0	0	12413	0	45402	16	16	24	739	25	253214	100	172100	80000	100	160000	80000	500	2093583	3313774	0	45014	45396	45371	15254	0	3	14843	240100	200	80000	160000	200	160000	400000	45285	44852	1	1	80201	100	99	100	100	0	80000	80000	100	80000	0	42	2229	0	80002	0	23	80002	2	42	0	0	5110	0	14	16	13	11	45194	0	0	80000	160000	100	45005	45119	44914	45350	44887
240204	44794	363	0	0	0	0	0	0	3	0	0	0	12418	0	45216	16	16	20	802	25	251969	100	174773	80000	100	160000	80000	576	2075574	3345169	0	45004	45159	45067	14889	0	3	14760	240100	200	80000	160000	200	160000	400000	45370	44963	1	1	80201	100	99	100	100	0	80000	80000	100	80000	0	42	2229	0	80002	0	176	80002	2	42	0	0	5110	0	8	16	13	13	45230	0	0	80000	160000	100	45188	44966	45356	45009	45292
240204	44811	367	0	0	0	0	0	0	3	0	0	0	12083	0	45143	16	0	0	816	25	251369	100	173050	80000	100	160000	80000	500	2071517	3311290	0	45190	45121	44795	15218	0	3	14935	240100	200	80000	160000	200	160000	400000	45040	45105	1	1	80201	100	99	100	100	0	80000	80000	100	80000	0	42	2362	0	80002	0	27	80000	0	42	0	0	5110	0	13	16	11	13	45458	0	0	80000	160000	100	45105	45070	44837	45039	45565
240204	45372	361	0	0	0	0	0	0	3	0	0	0	12294	0	45046	16	16	35	905	25	252418	100	172004	80000	100	160000	80000	500	2048428	3330218	0	45062	44973	45108	15136	0	3	15170	240100	200	80000	160000	200	160000	400000	45440	45337	1	1	80201	100	99	100	100	0	80000	80000	100	80000	0	42	2145	0	80002	1	20	80002	2	0	0	0	5110	0	11	16	14	15	45231	0	0	80000	160000	100	45127	45052	44952	45019	45165
240204	45140	359	0	0	0	0	0	9	3	0	0	0	13267	0	44937	16	16	19	838	25	252088	100	172442	80000	100	160000	80000	500	2086123	3340853	0	45229	45225	44830	15132	0	3	15194	240100	200	80000	160000	200	160000	400000	44862	44975	1	1	80201	100	99	100	100	0	80000	80000	100	80000	0	0	2378	0	80000	0	29	80002	2	42	0	0	5110	0	13	16	13	6	44985	0	0	80000	160000	100	45315	44592	45415	45449	45055
240204	45379	364	0	0	0	0	0	0	3	1	0	0	12137	0	44676	16	16	18	839	25	252438	100	173143	80000	100	160000	80000	500	2097698	3332220	1	45298	45155	45161	15000	0	3	15281	240100	200	80000	160000	200	160000	400000	44991	45192	1	1	80201	100	99	100	100	0	80000	80000	100	80000	0	0	2504	0	80002	0	14	80002	2	42	0	0	5110	0	13	16	12	6	44578	0	0	80000	160000	100	45501	44813	49601	44981	44982
240204	45905	365	0	0	0	0	0	12	3	0	0	0	11620	0	45311	16	16	19	892	25	251293	100	172848	80000	100	160000	80000	500	2097589	3297511	0	45208	45036	45138	14808	0	3	15102	240100	200	80000	160000	200	160000	400000	45014	45556	1	1	80201	100	99	100	100	0	80000	80000	100	80000	0	0	2593	0	80000	0	143	80002	2	0	0	0	5110	0	13	16	12	12	44976	0	0	80000	160000	100	45117	44822	45162	45274	44931
240204	45480	363	0	0	0	0	0	12	0	0	0	0	12188	0	45294	16	16	15	798	25	253193	100	172355	80000	100	160000	80000	500	2071907	3359707	0	44687	45301	44725	15035	0	3	14860	240100	200	80000	160000	200	160000	400000	45032	45303	1	1	80201	100	99	100	100	0	80000	80000	100	80000	0	42	2457	0	80002	0	107	80002	0	42	0	0	5110	0	12	16	13	13	45066	0	0	80000	160000	100	45221	45308	45077	45236	45144

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5641

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	18	19	1e	1f	22	37	3f	46	49	4e	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	rob full (74)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd store (99)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
240027	45033	350	0	0	0	0	0	2	0	13039	45197	16	16	25	958	25	252253	10	170984	80000	10	160000	80000	50	2062699	3293629	45362	44972	45149	14664	0	3	14843	240010	20	80000	160000	20	160000	400000	44892	45606	1	1	80021	10	9	10	10	80000	80000	10	80000	0	34	2189	0	80000	0	0	5	80002	2	34	0	5038	5	16	4	5	45452	0	80000	160000	10	44976	44823	45524	45108	45337
240024	49644	350	0	0	0	0	0	0	0	11435	45382	16	16	26	946	25	252365	10	171925	80000	10	160000	80000	50	2082154	3296014	45113	45389	45328	14986	0	3	15064	240353	20	80120	160000	20	160000	400000	44695	44831	1	1	80021	10	9	10	10	80000	80000	10	80000	0	34	2169	0	80002	1	0	2	80000	2	34	0	5020	5	16	5	5	45009	0	80000	160000	10	44885	45210	45100	45164	45539
240024	45179	349	0	0	0	0	0	8	0	12250	44642	16	16	13	908	25	252303	10	172909	80000	10	160000	80000	50	2072129	3318498	45055	45080	45259	15043	0	3	14755	240010	20	80000	160000	20	160000	400000	45248	45099	1	1	80021	10	9	10	10	80000	80000	10	80000	0	0	2029	0	80002	0	0	2	80002	2	34	0	5020	5	16	4	4	45327	0	80000	160000	10	45130	45483	44900	45278	45000
240024	45010	350	0	0	0	0	0	2	0	11336	45277	0	16	38	944	25	252253	10	172335	80000	10	160000	80000	50	2072820	3371785	44759	45107	45009	14540	0	3	14854	240010	20	80000	160000	20	160000	400000	45126	45123	1	1	80021	10	9	10	10	80000	80000	10	80000	0	34	2492	0	80002	1	0	2	80002	2	34	0	5020	5	16	5	5	45317	0	80000	160000	10	45531	45327	45147	44540	45223
240024	45432	347	0	0	0	0	0	8	0	12742	45080	0	0	37	936	25	253081	10	171658	80000	10	160000	80000	50	2087547	3305196	45128	45394	44928	15382	0	3	14956	240010	20	80000	160000	20	160000	400000	45502	44993	1	1	80021	10	9	10	10	80000	80000	10	80000	0	34	1951	0	80002	0	0	8	80002	2	34	0	5020	4	16	3	4	45576	0	80000	160000	10	45378	45126	44880	44970	45459
240024	44768	347	0	0	0	0	0	2	0	11368	45734	16	16	19	1227	112	253877	10	173071	80240	10	160704	80540	56	2100722	3295187	44531	45534	45869	15359	59	3	14913	240698	20	80120	160963	20	160240	402409	45422	45004	2	1	80021	10	9	10	10	80000	80000	10	80060	2	34	2752	2	80182	0	2	16442	80002	0	34	0	5040	5	25	5	6	45320	0	80000	160000	10	45716	45604	49637	44857	45312
240024	45772	353	0	1	4	3	528	90	0	12758	45306	16	16	7	769	25	252733	10	172848	80000	10	160000	80000	50	2092120	3323407	45637	44995	45062	14851	0	3	15164	240010	20	80120	160000	20	160000	400000	45074	45033	1	1	80021	10	9	10	10	80000	80000	10	80000	0	34	2185	0	80002	1	0	2	80002	2	34	0	5020	4	16	5	4	45186	0	80000	160000	10	50002	50183	48652	50499	50039
240024	50073	382	2	0	33	27	0	0	1	13052	45217	16	16	28	926	25	251930	10	171856	80000	10	160000	80000	50	2094323	3356406	45045	44810	49155	15543	0	3	14441	240010	20	80000	160000	20	160000	400000	45140	44981	2	1	80021	10	9	10	10	80000	80000	10	80000	0	34	2299	0	80002	0	0	8	80000	2	34	1	5020	5	16	4	4	45416	0	80000	160000	10	45127	45006	44868	45174	45243
240024	45027	338	0	0	0	0	0	2	0	10824	44893	16	16	13	826	25	252356	10	172029	80000	10	160000	80000	50	2083025	3321625	45095	44932	45055	14710	0	3	15327	240010	20	80000	160000	20	160000	400000	45047	45220	1	1	80021	10	9	10	10	80000	80000	10	80000	0	34	2401	0	80002	0	0	2	80000	2	0	0	5020	5	16	4	3	45138	0	80000	160000	10	45194	44873	45291	45222	45073
240024	45090	338	0	0	0	0	0	2	0	11694	44991	16	16	20	856	25	252162	10	172709	80000	10	160000	80000	50	2083126	3311614	44833	45208	45258	15203	0	3	14731	240010	20	80000	160000	20	160000	400000	45267	45092	1	1	80021	10	9	10	10	80000	80000	10	80000	0	34	2119	0	80000	0	0	3	80000	2	34	0	5020	5	16	6	4	45231	0	80000	160000	10	44526	44601	45276	45317	44728

ST4 (single, H)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations