Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

ST4 (single, post-index, B)

Test 1: uops

Code:

  st4 { v0.b, v1.b, v2.b, v3.b }[1], [x6], x8
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop
  mov x0, 0
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 3.000

Issues: 4.000

Integer unit issues: 1.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 2.000

retire uop (01)cycle (02)03l1i tlb fill (04)l1d tlb fill (05)mmu table walk instruction (07)mmu table walk data (08)09l2 tlb miss instruction (0a)l2 tlb miss data (0b)18191e1f22243a3f464951schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)5e5f696d6emap rewind (75)map stall (76)dispatch uop (78)map ldst uop (7d)map simd uop (7e)map ldst uop inputs (80)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd store (99)inst ldst (9b)l1d tlb access (a0)l1d tlb miss (a1)l1d cache miss st (a2)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acafbcl1d cache miss st nonspec (c0)c2c9cfd0d2l1i cache miss demand (d3)l1i tlb miss demand (d4)d5map dispatch bubble (d6)d9dadbddfetch restart (de)e0? int output thing (e9)eaebec? ldst retires (ed)? simd retires (ee)? int retires (ef)f5f6f7f8fd
6300729604237510001000001047302930911164814000100020001000100020001000500012808179100123572292562949131040001000200030005000293442945411610011000100010000001000000100003001316293856938315024920939326238171646542870810001629613583140111000200010002941029561295212944629503
63004295192370110000000010481829381001658240001000200010001000200010005000127981790306235452918829427123140041000200230005000294042944021610011000100010000201000106100000001328193836933323115020770327038131281642868410001629613293138831000200010002969229632296412950329578
6300429416237101110111121040046962936300165594000100020021001100020001000500012804179060323577292542955731040001000200030005000294942953711610011000100010000001000000100003001343394896965315205420885336238131856602882110001606513587138951000200010002958529618295342964029510
630042946423810100000060104602293960016561400010002000100010002000100050001280117900042355629366296203104000100020003000500029560294561161001100010001000020100110010000300131779431697731940522094733053818953592876010001643913676139881000200010002949329579296992964529512
6300429579238100000000152104632294730016690400010002000100010002000100050001280517905042358529322295113104000100120023000500529524295103161001100010001005220100110790100003001327895136920316305420967333238192055512879910011631513643140181000200010002945329715295222964029567
630042959823610000111113201047412942900166384000100020021000100020021000500012819179040623549293062972774940001001200230035000296352959221610011000100010001222100402136510010291441336692486863311905020870340838201554502904610021636513853139541000200010002972529659296642975729512
6300429444237100001100001047892957200164144004100020001000100020001000500012804179080123581293542959331040001000200030005000295012953711610011000100010000231000004100002032671313494666925322105320916330938172150532879010001602113689140361000200010002939829401293712949129348
6300429435235100001000901047472940200167264000100020001000100020001000500012800179040123590292962960231040001000200030005000298033020911610011000100010000201000200100102001329892026942312615820810340638132253542887610001630713628140441000200010002957729695299692950329667
630042958824300110100052801047562994900166284000100020001000100120001000500012852179000223565296882964371040001000200030035000300762963511610011000100010000321000103100002230471307092986966314405220831333838131454592872010001640313670140871000200010002952429523296412950029771
630042931823500100102114198013201042742995700171854052101120161007100820221010502012805179090423542295232961931040001000200030005000293672937211610011000100010000001000120100002001320194446899318415320884327938161351442872610001621513554137231000200010002944029357294172937229358

Test 2: throughput

Count: 8

Code:

  st4 { v0.b, v1.b, v2.b, v3.b }[1], [x6], x8
  st4 { v0.b, v1.b, v2.b, v3.b }[1], [x6], x8
  st4 { v0.b, v1.b, v2.b, v3.b }[1], [x6], x8
  st4 { v0.b, v1.b, v2.b, v3.b }[1], [x6], x8
  st4 { v0.b, v1.b, v2.b, v3.b }[1], [x6], x8
  st4 { v0.b, v1.b, v2.b, v3.b }[1], [x6], x8
  st4 { v0.b, v1.b, v2.b, v3.b }[1], [x6], x8
  st4 { v0.b, v1.b, v2.b, v3.b }[1], [x6], x8
  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0005

retire uop (01)cycle (02)03mmu table walk instruction (07)mmu table walk data (08)09l2 tlb miss instruction (0a)l2 tlb miss data (0b)18191e1f2324373f46494f51schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd store (99)inst ldst (9b)9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache miss st (a2)a4ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acafbcl1d cache miss st nonspec (c0)c2branch mispred nonspec (cb)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)ea? ldst retires (ed)? simd retires (ee)? int retires (ef)f5f6f7f8fd
2402078004062100000000200279480025880253236998010016321380000801001600008000044081893758404148977080015800408004049924349998320100200800001600002002400004000008004080040118020110099100100800008000010080000017008000100280001017005110125118003780000080000160000801008004180041800418004180041
240204800406200000000020030238002588025322768801001628538006080100160000800004408189375840514873458001580172800404992434999832010020080000160000200240000400000800408004011802011009910010080000800001008000000008000100480000117005110116118003780000080000160000801008004180041800418004180041
2402048016962000000001220030778002508025323402801001632428000080100160000800004408189375840514853658001580040800404992434999832010020080119160000200240000400000800408004011802011009910010080000800001008000001700800012028000000005110116128003780000080000160000801008004180169800418004180041
2402048004062000000000200304080025880253232198010016316980000801001600008000044081893758405148607680015800408004049924349998320100200800001600002002400004000008004080040118020110099100100800008000010080000017008000100580001117005110116118003780000080000160000801008004180041800418004180041
2402048004062000000000200300080025880253231288010016256380000801001600008000044081893758405148675680015800408004049924349998320100200800001600002002400004000008004080040118020110099100100800008000010080000017008000100580000118005110116118003780000080000160000801008004180041800418004180041
2402048017162000000000200300480025880253232878010016315980000801001602498000044081893758407148784680015800408004049924349998320100200800001600002002400004000008004080040118020110099100100800008000010080000017008000100280001117005110116118003780000080000160000801008004180041800418004180041
2402048004062000001009210295080025880253232998010016280780000801001600008000044081893762244148885480015800408004049924349998320100200800001600002002403844000008004080040118020110099100100800008000010080000017008000100280001017015110116118003780000280000160000801008004180041800418004180041
24020480040620000000024010314180025880253229558010016273880000801001600008000044081893758406148692280015800408004049924349998320100200800001600002002400004000008004080040118020110099100100800008000010080000017008000000280001117005110116118003780000080000160000801008004180041800418004180041
2402048004062000000000200318380025880253232048010016322880000801001600008000044081753758404148784480015800408004049924349998320100200800001600002002400004000008004080040118020110099100100800008000010080000017008000110280001117005110116118003780000080000160000801008004180041800418004180041
2402048004062000000001500031958002580025322641801001630868000080100160000800004408189375840514861888001580040800404992434999832010020080000160000200240000400000800408004011802011009910010080000800001008000000008000200280001017005110116118003780000080000160000801008004180041800418004180041

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0005

retire uop (01)cycle (02)03l1d tlb fill (05)mmu table walk data (08)09l2 tlb miss data (0b)18191e1f2223373a3f46494f51schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd store (99)inst ldst (9b)9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache miss st (a2)a4ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acafbcl1d cache miss st nonspec (c0)l1d tlb miss nonspec (c1)c2branch cond mispred nonspec (c5)cdcfd0l1i cache miss demand (d3)d5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)f5f6f7f8fd
240027800406211101003700306418002511110253229208001016341980000800101600008000044076723758422148968580015080040800404994635002032001020800001600002024144040000080040800401180021109101080000800001080008725008012810880000825700050200131653800378000080000160000800108004180041800418004180041
24002480040620100000090028951800251101253231958001016270280000800101600008000044076723758413148794880015080040800404994635002032001020800001600002024000040000080040800401180021109101080000800001080007925018000801880001825710050200031643800378000080000160000800108004180041800418004180041
24002480040620100000121200268718002511002532308680010162784800008001016000080000440767237584221487434800150800408004049946350020320010208000016000020240000400000800408004011800211091010800008000010800087250280008001180001825700050200031633800378000080000160000800108004180041800418004180041
240024800406211000000710301718002591012532308680010163282800008001016000080000440767237584221486476800150800408004049946350020320010208000016000020240000400000800408004011800211091010800008000010800089250180008201480001825710050200041633800378000080000160000800108004180041800418004180041
240024800406201101000120033321800251111025323140800101628848000080010160000800004407672375842214874918001538004080040499463500203200102080000160000202400004000008004080040118002110910108000080000108000872500800070188000180710050200031653800378000080000160000800108004180041800418004180041
24002480040621100100702900335818002511002532326580010163369800008013416000080000440767237584071490905800150800408004049946350020320010208000016000020240717400000800408004011800211091010800008000010800077001800080188000181710150200061633800378000080000160000800108004180041800418004180041
24002480040621110100249002769180025111112532341280010163412800008012716047180000440767237584181488827800150800408004049946350020320010208000016000020240000400000800408004011800211091010800008000010800098250080008001780000825700050200041653800378000080000160000800108004180175800418004180041
24002480040620100000129003009180025011125322993800101632578000080010160000800004407672375841114876298001508004080040499463500203200102080000160000202400004000008004080040118002110910108000080000108000770008000800108000080700050200041644800378000080000160000800108004180041800418004180041
24002480040643100000129003089180025111112532313280010162914800008001016000080000440767237584131487063800150800408004049946350020320010208000016024220240000400000800408004011800211091010800008000010800088250080008001180001825700050200041634800378000080000160000800108004180041800418004180041
2400248004062010000009002910180025011025323019800101628328000080010160000800004407672375842214874348001508004080040499463500203204922080240160000202400004000008015480040118002110910108000080000108000770008000800880000825700050200131633800378000080000160000800108015780041800418004180041