Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

ST4 (single, post-index, D)

Test 1: uops

Code:

  st4 { v0.d, v1.d, v2.d, v3.d }[1], [x6], x8
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop
  mov x0, 0
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 4.000

Issues: 5.000

Integer unit issues: 1.000

Load/store unit issues: 2.000

SIMD/FP unit issues: 2.000

retire uop (01)cycle (02)03l1i tlb fill (04)l1d tlb fill (05)mmu table walk instruction (07)mmu table walk data (08)09l2 tlb miss instruction (0a)l2 tlb miss data (0b)18191e1f22243a3f464951schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)5e5f696d6emap rewind (75)map stall (76)dispatch uop (78)map ldst uop (7d)map simd uop (7e)map ldst uop inputs (80)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd store (99)inst ldst (9b)l1d tlb access (a0)l1d tlb miss (a1)l1d cache miss st (a2)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acafbcl1d cache miss st nonspec (c0)l1d tlb miss nonspec (c1)c2c9cfd0d2l1i cache miss demand (d3)l1i tlb miss demand (d4)d5map dispatch bubble (d6)d9dadbddfetch restart (de)e0? int output thing (e9)eaebec? ldst retires (ed)? simd retires (ee)? int retires (ef)f5f6f7f8fd
64007290102311025002400003104655288630017773500010002000200010002000200050002162716000017217982863929010310500020002000500040002876928828116100110001000200004020000002000040001312595126877311486719829324538171859572843710001569812911141562000200010002898228856287622901728939
64004288782330122112610004104722287812217686500010002000200010002000200050002162616000012183828763288793105000200020005005400028828288581161001100010002003341200201320003421013308927968883119155819784320238161861662836110001560812660140692000200010002891828884288522899928885
6400429020233002400210006410464728651001779450001000200020001000200020005000216191600002218552874028930310500020002000500040002883828832116100110001000200004020000002000040001322492576920313196019931316638212060602848310001560712867140842000200010002888028988288162875428962
64004289442320122012510033004795286910017909500010002000200010002000200050002162816000042181728565287963105000200020005000400028896289141161001100010002002341200201220013621013127933568963165145919890325938172360542833110001531412870140642000200010002885828849288082876928871
64004288742330020002100003104683287291117848500010002000200010002000200050002161916000052181428659289063105000200020005000400028891288911161001100010002000040200010620000400013293933369333117155819879320938262760542836810001601612810135892000200010002888828938289462901628810
640042901223200200023000123004632288380017786500010002000200010002000200050002160816000022185128614289293105000200020005000400028930288241161001100010002000040200000020000400013412927370143136165620000321038131856662841910001549412855139052000200010002895628927288572890928952
64004289722320120102300003104735287280017794500010002000200010002000200050002161316000092178428674289623105000200020005000400028809289041161001100010002003362200202220013421013142938068783178156019923317338201960622844710001550312484137372000200010002899928925289562881129009
64004288762320026001900004104606288430117821500010002000200010002000200050002161516000012180228667289623105000200020005000400028884288631161001100010002000040200000020000400013124943169453093116419864320438181670582839610001573412781136652000200010002901128822290382889828950
64004289432320121111810003104753287740017649500010002000200010002000200050002161116000012184428764289063105000200020005000400028799289321161001100010002003242200301320013621013339932668343114126520059322638172659642847210001578912689137162000200010002887728787289312891529001
64004289532330018002600003104705287960117874500010002000200010002000200050002161116000052184128569287433105000200020005000400028829287931161001100010002000040200000620000400013180952369493125146319940321538212268642834110001558412837139332000200010002886528845288122898128933

Test 2: throughput

Count: 8

Code:

  st4 { v0.d, v1.d, v2.d, v3.d }[1], [x6], x8
  st4 { v0.d, v1.d, v2.d, v3.d }[1], [x6], x8
  st4 { v0.d, v1.d, v2.d, v3.d }[1], [x6], x8
  st4 { v0.d, v1.d, v2.d, v3.d }[1], [x6], x8
  st4 { v0.d, v1.d, v2.d, v3.d }[1], [x6], x8
  st4 { v0.d, v1.d, v2.d, v3.d }[1], [x6], x8
  st4 { v0.d, v1.d, v2.d, v3.d }[1], [x6], x8
  st4 { v0.d, v1.d, v2.d, v3.d }[1], [x6], x8
  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0007

retire uop (01)cycle (02)03l1d tlb fill (05)mmu table walk instruction (07)mmu table walk data (08)09l2 tlb miss data (0b)18191e1f2324373a3f46494f51schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd store (99)inst ldst (9b)9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache miss st (a2)a4ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acafbcl1d cache miss st nonspec (c0)l1d tlb miss nonspec (c1)c2cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)f5f6f7f8fd
320207800726201011001121200626328003716037254051808010016553216000080100160000160000480499287728312973990800258005280048033440010020016000016012020040000032000080230801012180201100991001008000080000100160013134600160014001516000012012005109117118004880000160000160000801008005480050800508004680053
32020480057621100000039120058692800381616025404589801001655781600008010016000016000048049922340041303454080023800528005303334001002001600001600002004000003200008005280052118020110099100100800008000010016001212000160002002160002144612005109117118005880000160000160000801008005380054800508005380053
3202048005262010010000160047892800380160254001098010016570916000080100160000160000480499263970912939210800258005080053033440010020016000016000020040000032000080052800511180201100991001008000080000100160013130011600000015160002124612005109117118004980000160000160000801008005280053800538005280053
3202048004862000000210120042072800381616025403235801001644991600008010016000016000048049927197251304401080028800528005303344001002001600001600002004000003200008004980052118020110099100100800008000010016001300011600140020160002144612005109117118004880000160000160000801008005380048800508005280053
32020480046620100000001600488408003716160254053698010016443716000080100160000160000480499279969513005870800268005180052033240010020016000016000020040000032000080052800521180201100991001008000080000100160013134601160014111416000212012305109117118005080000160000160000801008005380052800558004680053
320204800526201001000312004605280035160025405406801001656771600008010016000016000048049924000451300298080028800498004903344001002001600001600002004000003200008021680049118020110099100100800008000010016001200001600140017160002144612005109117118004880000160000160000801008004580049800518005480052
320204800516201010100016005729280038161602540509880100165451160000801001600001600004804992444340129887408002680050800520327400100200160000160000200400000320000800538005211802011009910010080000800001001600121344001600141114160000144812005109117118004880000160000160000801008005080052800528005480046
3202048005362110001000300471928003816160254060318010016560616000080100160000160000480499255983913046150800278004980045033440010020016000016000020040000032000080053800521180201100991001008000080000100160013134600160014032160000144612105109117118004280000160000160000801008005480052800458005080050
3202048005162010110000150046652800381616025404752801001649191600008015916000016000048049927197251297328080028800528022103344001002001600001600002004000003200008004980052118020110099100100800008000010016001213001160002001516000216460005109117118004880000160000160000801008005080053800528005180054
320204800536201010000030026632800381616025405917801001644591600008010016000016000048049925597961298751080027800438005103334001002001600001600002004000003200008005480050118020110099100100800008000010016001212460016001400171600001444121051092277118004280000160000160000801008005280053800518005180049

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0007

retire uop (01)cycle (02)03l1d tlb fill (05)mmu table walk data (08)l2 tlb miss instruction (0a)l2 tlb miss data (0b)18191e1f2224373a3f46494f51schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)5f6061696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd store (99)inst ldst (9b)9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache miss st (a2)a4ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acafbcl1d cache miss st nonspec (c0)l1d tlb miss nonspec (c1)c2cfd2d5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)f5f6f7f8fd
32002780058620100000010400503228004516160254043918006916496216000080010160000160000480049255979412998212108002580049800490334400010201600001600002040000032000080052800531180021109101080000800001016001213466311600140017160002144612150190917998004880000160000160000800108005380054800538005380049
3200248005362110010001610497928003216160254048388001016050416000080010160000160000480049279971913014403108002580049800510932400010201600001600002040000032000080052800521180021109101080000800001016001213500016007210121600021446120501909171098005080000160000160000800108005480051801738005480054
32002480053621120100015004512280035016025404249800101644061600008001016000016000048004926396541302292410801888005380053033440001020160000160000204000003202408005380052118002110910108000080000101600121246001600140114160002144612150190817998020880000160000160000800108005380053800548022380054
320024800526201101000160052792800371600254043388001016541116000080010160000160000480049241249913006873108002780052800530334400010201600001600002040000032000080051800511180021109101080000800001016001212460116001400151600021401205019010179108005080000160000160000800108005380054800528005380053
3200248022262110000112150050262800361616025406266800101657501600008001016000016000048004927997711307415410800288005180051033540001020160000160000204000003200008005380052118002110910108000080000101600131246001600141014160002144612050190817998004980000160000160000800108005380052800548005480052
32002480052621110100121500532928003616160254057348006916502716000080010160000160000480049271957213028104108002780052800520334400010201600001600002040000032000080049802211180021109101080000800001016001313460016001400171600001445121501901017998004980000160000160000800108005280053800538005280053
32002480053621100000615014771280207161604840471680069164942160000800101601181601084800492347707129477351080341802218022193813640058020160120160240204003003204808038880220218002110910108000080000101600721546125316007403944160062140122504709171198020280059160000160000800108022380222802228021880223
3200248022162210022113219100517928020616161017140642480069165270160120800691602361601084804012520599130364851080341803868038893923340029520160120160120204006003202408038780306318002110910108000080000101600121348001600141015160002144612150190917898005080000160000160000800108005480052800548005280051
320024800536201001001216004835280037160025407067800101647191600008001016000016000048004927196741298078510800268005380052033440001020160000160000204000003200008005380053118002110910108000080000101600121246001600141017160002144612050190917998005080000160000160000800108005180054800528005480054
320024800536201001000160056142800361616025404203800101655751600008001016000016000048004925597961305277410800278005380053033340001020160000160000204000003200008005280053118002110910108000080000101600131346001600140214160000140120501901017998004980000160000160000800108005380054800538005480053