Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

ST4 (single, post-index, H)

Test 1: uops

Code:

  st4 { v0.h, v1.h, v2.h, v3.h }[1], [x6], x8
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop
  mov x0, 0
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 3.000

Issues: 4.000

Integer unit issues: 1.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 2.000

retire uop (01)cycle (02)03mmu table walk instruction (07)mmu table walk data (08)09l2 tlb miss instruction (0a)l2 tlb miss data (0b)18191e1f223a3f464951schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)5f696d6emap rewind (75)map stall (76)dispatch uop (78)map ldst uop (7d)map simd uop (7e)map ldst uop inputs (80)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd store (99)inst ldst (9b)l1d tlb access (a0)l1d tlb miss (a1)l1d cache miss st (a2)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acafbcl1d cache miss st nonspec (c0)c2c9cfd0d2l1i cache miss demand (d3)l1i tlb miss demand (d4)d5map dispatch bubble (d6)d9dadbddfetch restart (de)e0? int output thing (e9)eaebec? ldst retires (ed)? simd retires (ee)? int retires (ef)f5f6f7f8fd
6300728994231250021000162104694288500015939400010012000100010002000100050001280417906323507286902902031040001000200030005000290212880211610011000100010000201000000100002001340094996965312497220303320838172159682831910001563813207134891000200010002887629030288692900628970
63004289542332500200003810047622893401159674000100020001000100020001000500012805179030234992883428943310400010002000300050002884929017116100110001000100002010011001000020013174941468673093106120244320138181558622841210001563213152132001000200010002894328971290502892829053
63004290502332400170004050046402891010158584000100020001000100020001000500012808179062235202870128947365400010002000300050002891828997116100110001000100003010001031000030013341947368933054126220368325138171966632836510001555713114135361000200010002892528947290542895728876
63004290122332900230003990047542890810159634000100020001000100020021000500012813179020235572877929070310400010002000300050002894628984116100110001000100002010001011000020013079949468733087126420259320838101856702848910001564512886133221000200010002891828925290792906229144
6300429055233260026000336004641290841115974400010002000100010002000100050001280917908623527288082898631040001000200030005000289732904011610011000100010000201000000100003012313108936369403133116320573322338172558642838010001595913120136001000200010002906729093291802905729143
63004289622342100220003780146092890501160594000100020001000100020001000500012802179025234992880229069310400010002000300050002900528973116100110001000100001010000001000020012980921969193080125920429319938202558602834310001553313012136291000200010002899128895290842891929481
63004291482342200280001051046112900410162604004100020001002100020061001500512798178958235992874829179142940001001200230065000291332916231610011000100010034321000004601001100013052955669353136196320403324938182966582843910001567913250132621000200010002903528993290062898729061
63004290832331711241011051046622907200163334004100020041002100320021002500512811179325235452883229142113040041000200030005000291272904421610011000100010012021000049431001002013298921968563153145920300316438162661622856910021604913146137661000200010002904229008289492913629344
63004295002372600300101020045982892300158114000100020001000100020001000500012811179044235862869028870310400010002000300350002924529016216100110001000100000010001041000000013138941169373108165920138323838141757702838710001567912973135081000200010002898628976289362889328938
630042894023221001600142900469728773111593440001000200010001000200010005000128171790672351729151295453104000100020003000500028916288721161001100010001000020100000121001000285013158938969013132205720129315638184553582886610141621513340136221000200010002992029966296852998029884

Test 2: throughput

Count: 8

Code:

  st4 { v0.h, v1.h, v2.h, v3.h }[1], [x6], x8
  st4 { v0.h, v1.h, v2.h, v3.h }[1], [x6], x8
  st4 { v0.h, v1.h, v2.h, v3.h }[1], [x6], x8
  st4 { v0.h, v1.h, v2.h, v3.h }[1], [x6], x8
  st4 { v0.h, v1.h, v2.h, v3.h }[1], [x6], x8
  st4 { v0.h, v1.h, v2.h, v3.h }[1], [x6], x8
  st4 { v0.h, v1.h, v2.h, v3.h }[1], [x6], x8
  st4 { v0.h, v1.h, v2.h, v3.h }[1], [x6], x8
  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0005

retire uop (01)cycle (02)03l1d tlb fill (05)mmu table walk instruction (07)mmu table walk data (08)l2 tlb miss instruction (0a)l2 tlb miss data (0b)18191e1f22373a3f46494f51schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd store (99)inst ldst (9b)9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache miss st (a2)a4ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acafbcl1d cache miss st nonspec (c0)l1d tlb miss nonspec (c1)c2cfd0d5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)f5f6f7f8fd
24020780040620000000004030670800258802532323980195162833800008010016000080000440818937584081491419800150800408004049924349998320100200800001600002002400004000008004080040118020110099100100800008000010080000021008000100380001121005112021623800378000080000160000801008004180171800418004180041
24020480040621010000004031061801568802532324280100163348800008010016000080000440818937621521488356800150800408004049924349998320100200800001600002002400004000008004080040118020110099100100800008000010080000021008006100380001124005110021621800378000080000160000801008017180041800418004180041
24020480040621000000004026381800258812532362480100163122800008010016000080000440818937584061488271800150800408004049924349998320100202800001600002002400004000008004080040118020110099100100800008000010080000021008000100380001021005110021622800378000080000160000801008004180041800418004180041
24020480040620010100164031691800258812532298280100163454800008010016000080000440818937584061485355800150800408004049924349998320100200800001600002002400004000008004080172118020110099100100800008000010080000021008000100680001121005110011612800378000080000160000801008004180041800418004180171
24020480040643000000004030531800250812532314480100162775800008010016000080000440818937676271497128800150800408004049924349998320100200800001600002002400004000008004080040118020110099100100800008000010080000021008000000080001121005112011622800378000080000160000801008004180041800418004180041
24020480040620010000004028731800258812532301080100163172800008010016000080000440818937621531489141800150800408004049924349998320100200800001600002002400004000008004080040118020110099100100800008000010080000021008000100080001021005110021621800378000080000160000801008004180041800418004180041
240204800406210000000124029990800258812532298780100163744800008010016000080000440818937584041486144800150800408004049924349998320100200800001600002002400004000008004080040118020110099100100800008000010080000021008000110080001121005110021622800378000080000160000801008004180041800418004180041
24020480040620010100000028240800250802532334580100163216800008010016000080000440818937584061486433800150800408004049924349998320100200800001600002002400004000008004080040118020110099100100800008000010080000021008000000180001021005112011621800378000080000160000801008004180041800418004180041
24020480040620010100004034131800258802532368180100162973800008010016000080000440818937584071487959800150800408004049924349998320100200800001600002002400004000008004080040118020110099100100800008000010080000021008000010080001121005110021622800378000080000160000801008004180041800418004180041
24020480040620010000002028291800258002532323380100163235800008010016000080000440818937584061489243800150800408004049924349998320100200800001600002002400004000008004080040118020110099100100800008000010080000021008000100380001021005110011612800378000080000160000801008004180041800418004180041

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0005

retire uop (01)cycle (02)03l1d tlb fill (05)mmu table walk data (08)09l2 tlb miss data (0b)0f18191e1f24373a3f46494f51schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd store (99)inst ldst (9b)9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache miss st (a2)a4ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acafbcl1d cache miss st nonspec (c0)l1d tlb miss nonspec (c1)c2branch call indir mispred nonspec (ca)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)ea? ldst retires (ed)? simd retires (ee)? int retires (ef)f5f6f7f8fd
24002780040620101000009703171180025111102532291180010162570800008001016000080000440767237584221488260800158004080040499463500203200102080000160000202400004000008016980040118002110910108000080000108000770008000900880000717005020716758003780000080000160000800108004180041800418004180041
240024800406211110000121202904080025111012532283680010163119800008001016000080000440767237584221488909800158004080040499463500203200102080000160000202400004000008004080040118002110910108000080000108000772500800680011800018257105020716778003780000080000160000800108004180041800418004180041
240024800406211000000090309518002511902532315880105162923800008001016000080000440767237584221488508800158004080040499463500203200102080000160000202400004000008004080040218002110910108000080000108000772502800070011800018257005020516778003780000080000160000800108004180041800418004180041
24002480040621100000012120327718002511111253233368001016291080000800101600008000044076723758419148738980015800408004049946350100320010208000016000020240000400000800408004011800211091010800008000010800088250080008018800018257005020725758003780000080000160000800108004180041800418004180041
2400248004062010000000902793180025002253233088001016307180000800101600008000044076723758419148420480015805538004049946350020320010208000016000020240000400000800408004011800211091010800008000010800077250080008108800018267005020716578003780000080000160000800108004180041800418004180041
240024800406201111000070276418002511112253232658001016275780000800101600008000044076723758422149159880015800408004049946350020320010208000016000020240000400000800408004011800211091010800008000010800087250180007108800017257105020816858003780000080000160000800108004180041800418004180041
2400248004062010000000902960180025011125322951800101633768000080010160000800004407672375841914899748001580040800404994635002032001020800001600002024000040000080040800401180021109101080000800001080007700080008007800018257005020516778003780000080000160000800108004180041800418004180041
24002480040620100000001203159180025111112532335680010163428800608001016000080000440767237584221486612800158004080040499463500203200102080000160000202400004000008004080040118002110910108000080000108000782500800070011800018257105020816578003780000080000160000800108004180041800418004180041
24002480040621101100011203460180025111112532299480010163159800008001016000080000440767237584191486915800158004080040499463500203200102080000160000202400004000008004080040118002110910108000080000108000772500800080014800018257005020716588003780000080000160000800108004180041800418004180041
24002480040621100000009029061800251101253229028001016331680000800101600008000044076723758419148871080015800408004049946350020320010208000016000020240000400000800408004011800211091010800008000010800087250080008008800018257105020516778003780000080000160000800108004180041800418004180041