Apple Microarchitecture Research by Dougall Johnson M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions M1/A14 E-core (Icestorm): Overview | Base Instructions | SIMD and FP Instructions
Code:
st4 { v0.s, v1.s, v2.s, v3.s }[1], [x6], x8 nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop
mov x0, 0 mov x8, 0
(no loop instructions)
Retires (minus 60 nops): 3.000
Issues: 4.000
Integer unit issues: 1.000
Load/store unit issues: 1.000
SIMD/FP unit issues: 2.000
retire uop (01) | cycle (02) | 03 | l1i tlb fill (04) | mmu table walk instruction (07) | mmu table walk data (08) | l2 tlb miss instruction (0a) | l2 tlb miss data (0b) | 18 | 19 | 1e | 1f | 22 | 3a | 3f | 46 | 49 | 51 | schedule uop (52) | schedule int uop (53) | schedule simd uop (54) | schedule ldst uop (55) | dispatch int uop (56) | dispatch simd uop (57) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | ldst uops in schedulers (5b) | 5f | 69 | 6d | 6e | map rewind (75) | map stall (76) | dispatch uop (78) | map ldst uop (7d) | map simd uop (7e) | map ldst uop inputs (80) | map simd uop inputs (81) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst simd store (99) | inst ldst (9b) | l1d tlb access (a0) | l1d tlb miss (a1) | l1d cache miss st (a2) | ld unit uop (a6) | st unit uop (a7) | l1d cache writeback (a8) | a9 | ac | af | l1d cache miss st nonspec (c0) | c2 | c9 | cf | d0 | d2 | l1i cache miss demand (d3) | l1i tlb miss demand (d4) | d5 | map dispatch bubble (d6) | d9 | da | db | dd | fetch restart (de) | e0 | ? int output thing (e9) | ea | eb | ec | ? ldst retires (ed) | ? simd retires (ee) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
63007 | 29563 | 238 | 1 | 2 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 1 | 4628 | 29464 | 1 | 1 | 16479 | 4000 | 1000 | 2000 | 1000 | 1000 | 2000 | 1000 | 5000 | 12807 | 17901 | 20 | 23454 | 29255 | 29402 | 3 | 10 | 4000 | 1000 | 2000 | 3000 | 5000 | 29351 | 29462 | 1 | 1 | 61001 | 1000 | 1000 | 1000 | 0 | 3 | 0 | 1000 | 0 | 0 | 3 | 1000 | 3 | 0 | 0 | 13287 | 9289 | 6979 | 3082 | 1 | 60 | 20718 | 3319 | 3802 | 16 | 61 | 58 | 28729 | 1000 | 16344 | 13523 | 14048 | 1000 | 2000 | 1000 | 29461 | 29557 | 29460 | 29616 | 29605 |
63004 | 29222 | 237 | 0 | 1 | 0 | 2 | 0 | 0 | 0 | 138 | 0 | 0 | 4601 | 29377 | 1 | 1 | 16554 | 4000 | 1000 | 2000 | 1000 | 1000 | 2000 | 1000 | 5000 | 12795 | 17898 | 18 | 23578 | 29307 | 29406 | 3 | 10 | 4000 | 1000 | 2000 | 3000 | 5005 | 29570 | 29526 | 1 | 1 | 61001 | 1000 | 1000 | 1000 | 0 | 3 | 0 | 1000 | 1 | 0 | 0 | 1000 | 3 | 0 | 0 | 13289 | 9404 | 6938 | 3089 | 0 | 60 | 20862 | 3277 | 3807 | 16 | 64 | 62 | 28772 | 1000 | 16167 | 13361 | 14112 | 1000 | 2000 | 1000 | 29483 | 29600 | 29538 | 29606 | 29522 |
63004 | 29562 | 237 | 0 | 1 | 0 | 3 | 0 | 0 | 0 | 3 | 1 | 0 | 4649 | 29366 | 1 | 1 | 16426 | 4000 | 1000 | 2000 | 1000 | 1000 | 2000 | 1000 | 5005 | 12802 | 17906 | 10 | 23536 | 29214 | 29446 | 3 | 10 | 4000 | 1000 | 2000 | 3000 | 5000 | 29414 | 29454 | 1 | 1 | 61001 | 1000 | 1000 | 1000 | 0 | 3 | 0 | 1000 | 0 | 2 | 0 | 1000 | 0 | 4 | 0 | 13100 | 9356 | 6916 | 3162 | 2 | 70 | 20844 | 3212 | 3810 | 13 | 62 | 65 | 28633 | 1000 | 16326 | 13511 | 14015 | 1000 | 2000 | 1000 | 29335 | 29547 | 29510 | 29527 | 29516 |
63004 | 29461 | 237 | 0 | 1 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 4766 | 29438 | 1 | 0 | 16464 | 4000 | 1000 | 2000 | 1000 | 1000 | 2000 | 1001 | 5000 | 12807 | 17906 | 5 | 23535 | 29221 | 29530 | 3 | 10 | 4000 | 1000 | 2002 | 3000 | 5000 | 29299 | 29436 | 1 | 1 | 61001 | 1000 | 1000 | 1000 | 0 | 3 | 0 | 1000 | 0 | 0 | 0 | 1000 | 2 | 0 | 0 | 13291 | 9341 | 6916 | 3193 | 1 | 65 | 20860 | 3350 | 3813 | 16 | 62 | 65 | 28690 | 1000 | 16185 | 13619 | 13816 | 1000 | 2000 | 1000 | 29574 | 29485 | 29497 | 29405 | 29465 |
63004 | 29602 | 237 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 88 | 0 | 4681 | 29341 | 0 | 1 | 16414 | 4000 | 1000 | 2000 | 1000 | 1000 | 2000 | 1001 | 5000 | 12805 | 17904 | 14 | 23561 | 29286 | 29399 | 3 | 10 | 4000 | 1000 | 2000 | 3000 | 5000 | 29365 | 29448 | 1 | 1 | 61001 | 1000 | 1000 | 1000 | 0 | 2 | 0 | 1000 | 0 | 0 | 385 | 1000 | 2 | 0 | 0 | 13052 | 9012 | 6918 | 3160 | 1 | 63 | 20881 | 3310 | 3816 | 10 | 65 | 60 | 28783 | 1000 | 16111 | 13459 | 14035 | 1000 | 2000 | 1000 | 29447 | 29529 | 29403 | 29351 | 29461 |
63004 | 29551 | 237 | 0 | 2 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 4670 | 29436 | 0 | 0 | 16473 | 4000 | 1000 | 2002 | 1000 | 1000 | 2000 | 1000 | 5000 | 12795 | 17906 | 7 | 23532 | 29223 | 29621 | 3 | 10 | 4000 | 1000 | 2000 | 3000 | 5000 | 29454 | 29462 | 1 | 1 | 61001 | 1000 | 1000 | 1000 | 0 | 2 | 0 | 1000 | 0 | 0 | 0 | 1000 | 2 | 0 | 0 | 13213 | 9387 | 6913 | 3160 | 1 | 63 | 20846 | 3405 | 3815 | 14 | 71 | 63 | 28891 | 1000 | 16535 | 13505 | 14107 | 1000 | 2000 | 1000 | 29554 | 29493 | 29530 | 29645 | 29599 |
63004 | 29672 | 237 | 0 | 2 | 0 | 1 | 0 | 0 | 0 | 0 | 88 | 0 | 4643 | 29475 | 0 | 0 | 16500 | 4000 | 1000 | 2000 | 1000 | 1000 | 2000 | 1000 | 5000 | 12799 | 17906 | 10 | 23569 | 29352 | 29605 | 3 | 10 | 4000 | 1000 | 2000 | 3000 | 5000 | 29527 | 29598 | 1 | 1 | 61001 | 1000 | 1000 | 1000 | 2 | 2 | 0 | 1000 | 0 | 0 | 0 | 1000 | 2 | 0 | 0 | 12973 | 9365 | 6953 | 3218 | 1 | 65 | 20856 | 3242 | 3814 | 18 | 62 | 61 | 28920 | 1000 | 16085 | 13529 | 14051 | 1000 | 2000 | 1000 | 29506 | 29573 | 29654 | 29543 | 29696 |
63004 | 29488 | 237 | 0 | 3 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 4672 | 29554 | 0 | 1 | 16633 | 4004 | 1000 | 2000 | 1000 | 1000 | 2000 | 1000 | 5000 | 12797 | 17915 | 5 | 23591 | 29452 | 29602 | 3 | 10 | 4000 | 1000 | 2000 | 3000 | 5000 | 29586 | 29478 | 1 | 1 | 61001 | 1000 | 1000 | 1000 | 0 | 2 | 0 | 1000 | 0 | 0 | 0 | 1000 | 2 | 0 | 0 | 13347 | 9235 | 7026 | 3149 | 2 | 56 | 21052 | 3295 | 3805 | 9 | 62 | 62 | 28828 | 1000 | 16380 | 13816 | 13809 | 1000 | 2000 | 1000 | 29542 | 29725 | 29641 | 29657 | 29709 |
63004 | 29662 | 238 | 0 | 2 | 0 | 0 | 1 | 1 | 1 | 396 | 88 | 0 | 4639 | 29565 | 0 | 1 | 16543 | 4000 | 1001 | 2000 | 1000 | 1000 | 2000 | 1000 | 5010 | 12806 | 17925 | 8 | 23557 | 29331 | 29650 | 7 | 69 | 4012 | 1000 | 2004 | 3000 | 5005 | 29729 | 29528 | 3 | 1 | 61001 | 1000 | 1000 | 1002 | 0 | 3 | 2 | 1002 | 0 | 2 | 435 | 1001 | 2 | 0 | 0 | 12987 | 9359 | 6939 | 3160 | 0 | 57 | 20976 | 3277 | 3814 | 19 | 61 | 57 | 28930 | 1000 | 16438 | 13664 | 14152 | 1000 | 2000 | 1000 | 29548 | 29660 | 29570 | 29703 | 29618 |
63004 | 29575 | 239 | 0 | 1 | 1 | 2 | 1 | 3 | 2 | 264 | 88 | 0 | 4647 | 29555 | 1 | 0 | 16622 | 4004 | 1000 | 2000 | 1000 | 1001 | 2000 | 1001 | 5005 | 12806 | 17952 | 10 | 23645 | 29601 | 29902 | 8 | 49 | 4000 | 1001 | 2004 | 3003 | 5010 | 29716 | 29720 | 3 | 1 | 61001 | 1000 | 1000 | 1000 | 0 | 3 | 0 | 1000 | 0 | 0 | 0 | 1000 | 2 | 0 | 129 | 13072 | 9427 | 6838 | 3115 | 1 | 61 | 21331 | 3427 | 3817 | 29 | 66 | 68 | 28998 | 1000 | 16025 | 13445 | 13932 | 1000 | 2000 | 1000 | 29473 | 29395 | 29520 | 29497 | 29358 |
Count: 8
Code:
st4 { v0.s, v1.s, v2.s, v3.s }[1], [x6], x8 st4 { v0.s, v1.s, v2.s, v3.s }[1], [x6], x8 st4 { v0.s, v1.s, v2.s, v3.s }[1], [x6], x8 st4 { v0.s, v1.s, v2.s, v3.s }[1], [x6], x8 st4 { v0.s, v1.s, v2.s, v3.s }[1], [x6], x8 st4 { v0.s, v1.s, v2.s, v3.s }[1], [x6], x8 st4 { v0.s, v1.s, v2.s, v3.s }[1], [x6], x8 st4 { v0.s, v1.s, v2.s, v3.s }[1], [x6], x8
mov x7, x6 mov x8, x6 mov x9, x6 mov x10, x6 mov x11, x6 mov x12, x6 mov x13, x6 mov x8, 0
(fused SUBS/B.cc loop)
Result (median cycles for code divided by count): 1.0005
retire uop (01) | cycle (02) | 03 | mmu table walk data (08) | 09 | 0f | 18 | 19 | 1e | 1f | 22 | 24 | 37 | 3f | 46 | 49 | 4f | 51 | schedule uop (52) | schedule int uop (53) | schedule simd uop (54) | schedule ldst uop (55) | dispatch int uop (56) | dispatch simd uop (57) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | ldst uops in schedulers (5b) | 60 | 69 | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map simd uop (7e) | map int uop inputs (7f) | map ldst uop inputs (80) | map simd uop inputs (81) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | 91 | inst branch cond (94) | inst int alu (97) | inst simd store (99) | inst ldst (9b) | 9f | l1d tlb access (a0) | l1d tlb miss (a1) | l1d cache miss st (a2) | a4 | ld unit uop (a6) | st unit uop (a7) | l1d cache writeback (a8) | a9 | ac | af | bc | l1d cache miss st nonspec (c0) | c2 | branch cond mispred nonspec (c5) | branch mispred nonspec (cb) | cf | d0 | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ? int output thing (e9) | ? ldst retires (ed) | ? simd retires (ee) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
240207 | 80040 | 642 | 0 | 0 | 0 | 0 | 0 | 12 | 1 | 0 | 0 | 2897 | 80025 | 8 | 11 | 0 | 25 | 323369 | 80100 | 162758 | 80000 | 80100 | 160000 | 80000 | 4408189 | 3758405 | 1487065 | 0 | 80015 | 80040 | 80040 | 49924 | 3 | 49998 | 320560 | 200 | 80000 | 160000 | 200 | 240000 | 400000 | 80040 | 80040 | 1 | 1 | 80201 | 100 | 99 | 0 | 100 | 100 | 80000 | 80000 | 100 | 80000 | 0 | 17 | 0 | 0 | 80001 | 0 | 0 | 4 | 80061 | 1 | 0 | 0 | 2 | 0 | 5110 | 0 | 1 | 16 | 1 | 1 | 80037 | 80000 | 80000 | 160000 | 80100 | 80041 | 80041 | 80041 | 80041 | 80153 |
240204 | 80040 | 620 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 3377 | 80025 | 8 | 8 | 0 | 61 | 322758 | 80100 | 163234 | 80000 | 80100 | 160000 | 80000 | 4408189 | 3758404 | 1487936 | 0 | 80120 | 80040 | 80040 | 49924 | 3 | 49998 | 320100 | 200 | 80000 | 160000 | 200 | 240744 | 400000 | 80040 | 80040 | 1 | 1 | 80201 | 100 | 99 | 0 | 100 | 100 | 80000 | 80000 | 100 | 80000 | 0 | 17 | 0 | 0 | 80001 | 0 | 0 | 2 | 80061 | 1 | 17 | 0 | 0 | 0 | 5110 | 0 | 1 | 16 | 1 | 1 | 80037 | 80000 | 80000 | 160000 | 80100 | 80041 | 80041 | 80171 | 80041 | 80041 |
240204 | 80040 | 621 | 0 | 0 | 0 | 0 | 0 | 18 | 2 | 0 | 0 | 2608 | 80025 | 0 | 8 | 0 | 25 | 323289 | 80100 | 163046 | 80000 | 80100 | 160000 | 80108 | 4408189 | 3758406 | 1488671 | 0 | 80015 | 80040 | 80040 | 49974 | 3 | 49998 | 320100 | 200 | 80000 | 160000 | 200 | 240000 | 400000 | 80040 | 80040 | 1 | 1 | 80201 | 100 | 99 | 0 | 100 | 100 | 80000 | 80000 | 100 | 80000 | 2 | 17 | 0 | 0 | 80001 | 0 | 0 | 2 | 80001 | 1 | 17 | 0 | 0 | 0 | 5110 | 0 | 1 | 16 | 1 | 1 | 80037 | 80093 | 80000 | 160000 | 80100 | 80041 | 80041 | 80041 | 80041 | 80041 |
240204 | 80040 | 620 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 2807 | 80025 | 8 | 8 | 0 | 25 | 323221 | 80100 | 162977 | 80000 | 80100 | 160000 | 80000 | 4408189 | 3758405 | 1487991 | 0 | 80015 | 80040 | 80040 | 49924 | 3 | 49998 | 320100 | 200 | 80000 | 160000 | 200 | 240000 | 400000 | 80040 | 80040 | 1 | 1 | 80201 | 100 | 99 | 0 | 100 | 100 | 80000 | 80000 | 100 | 80000 | 0 | 17 | 0 | 0 | 80001 | 0 | 2 | 4 | 80001 | 1 | 18 | 0 | 0 | 0 | 5110 | 0 | 1 | 16 | 1 | 1 | 80037 | 80000 | 80000 | 160000 | 80100 | 80041 | 80041 | 80041 | 80041 | 80041 |
240204 | 80040 | 620 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 3141 | 80025 | 8 | 8 | 0 | 25 | 323428 | 80100 | 163182 | 80000 | 80100 | 160000 | 80000 | 4408189 | 3758405 | 1487148 | 1 | 80119 | 80040 | 80040 | 49924 | 3 | 49998 | 320100 | 200 | 80000 | 160000 | 200 | 240000 | 400000 | 80169 | 80040 | 1 | 1 | 80201 | 100 | 99 | 0 | 100 | 100 | 80000 | 80000 | 100 | 80000 | 0 | 17 | 0 | 0 | 80001 | 0 | 0 | 2 | 80001 | 1 | 17 | 0 | 0 | 0 | 5110 | 0 | 1 | 16 | 1 | 1 | 80037 | 80000 | 80000 | 160000 | 80100 | 80041 | 80041 | 80169 | 80041 | 80041 |
240204 | 80040 | 620 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 3026 | 80025 | 8 | 8 | 0 | 25 | 322807 | 80100 | 163164 | 80000 | 80100 | 160000 | 82160 | 4408189 | 3758406 | 1488138 | 0 | 80015 | 80040 | 80040 | 49924 | 3 | 49998 | 320100 | 200 | 80000 | 160000 | 200 | 240000 | 400000 | 80040 | 80040 | 1 | 1 | 80201 | 100 | 99 | 0 | 100 | 100 | 80000 | 80000 | 100 | 80000 | 0 | 17 | 0 | 0 | 80000 | 0 | 0 | 2 | 80001 | 0 | 17 | 0 | 0 | 0 | 5110 | 0 | 1 | 16 | 1 | 1 | 80037 | 80000 | 80000 | 160000 | 80100 | 80041 | 80041 | 80041 | 80041 | 80041 |
240204 | 80040 | 620 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2685 | 80025 | 8 | 8 | 0 | 25 | 322999 | 80100 | 162472 | 80000 | 80100 | 160000 | 80000 | 4408189 | 3758408 | 1488319 | 0 | 80015 | 80040 | 80040 | 49924 | 3 | 49998 | 320100 | 200 | 80000 | 160000 | 200 | 240000 | 400000 | 80040 | 80040 | 1 | 1 | 80201 | 100 | 99 | 0 | 100 | 100 | 80000 | 80000 | 100 | 80000 | 0 | 17 | 0 | 0 | 80001 | 0 | 0 | 5 | 80001 | 1 | 17 | 0 | 0 | 0 | 5110 | 0 | 1 | 16 | 1 | 1 | 80037 | 80000 | 80000 | 160000 | 80100 | 80041 | 80041 | 80041 | 80041 | 80041 |
240204 | 80040 | 620 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 2843 | 80025 | 8 | 8 | 0 | 25 | 323200 | 80100 | 162769 | 80000 | 80100 | 160000 | 80000 | 4408189 | 3758405 | 1486090 | 0 | 80015 | 80040 | 80040 | 49924 | 3 | 49998 | 320100 | 200 | 80000 | 160000 | 200 | 240000 | 400000 | 80040 | 80040 | 1 | 1 | 80201 | 100 | 99 | 0 | 100 | 100 | 80000 | 80000 | 100 | 80000 | 0 | 17 | 0 | 0 | 80001 | 0 | 0 | 2 | 80001 | 1 | 17 | 0 | 0 | 0 | 5110 | 0 | 1 | 16 | 1 | 1 | 80037 | 80000 | 80000 | 160000 | 80100 | 80041 | 80041 | 80041 | 80041 | 80041 |
240204 | 80040 | 620 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 2385 | 80025 | 8 | 8 | 0 | 25 | 322845 | 80100 | 162744 | 80000 | 80100 | 160000 | 80000 | 4408189 | 3758413 | 1491100 | 0 | 80015 | 80040 | 80040 | 49978 | 3 | 49998 | 320100 | 200 | 80000 | 160000 | 200 | 240000 | 400000 | 80040 | 80040 | 1 | 1 | 80201 | 100 | 99 | 0 | 100 | 100 | 80000 | 80000 | 100 | 80000 | 0 | 18 | 0 | 0 | 80001 | 1 | 0 | 2 | 80001 | 1 | 17 | 0 | 0 | 0 | 5110 | 0 | 1 | 16 | 1 | 1 | 80037 | 80000 | 80000 | 160000 | 80100 | 80041 | 80041 | 80041 | 80041 | 80041 |
240204 | 80040 | 621 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 3243 | 80025 | 8 | 0 | 0 | 25 | 323109 | 80100 | 162977 | 80000 | 80100 | 160000 | 80000 | 4408189 | 3758405 | 1490562 | 0 | 80015 | 80040 | 80040 | 49924 | 3 | 49998 | 320100 | 200 | 80000 | 160000 | 200 | 240000 | 400000 | 80040 | 80040 | 1 | 1 | 80201 | 100 | 99 | 0 | 100 | 100 | 80000 | 80000 | 100 | 80000 | 0 | 17 | 0 | 0 | 80001 | 0 | 0 | 3 | 80001 | 1 | 17 | 0 | 0 | 0 | 5110 | 0 | 1 | 16 | 1 | 1 | 80037 | 80093 | 80000 | 160000 | 80100 | 80041 | 80041 | 80041 | 80041 | 80041 |
Result (median cycles for code divided by count): 1.0005
retire uop (01) | cycle (02) | 03 | l1d tlb fill (05) | mmu table walk data (08) | 09 | l2 tlb miss data (0b) | 18 | 19 | 1e | 1f | 22 | 23 | 24 | 37 | 3a | 3f | 46 | 49 | 4f | 51 | schedule uop (52) | schedule int uop (53) | schedule simd uop (54) | schedule ldst uop (55) | dispatch int uop (56) | dispatch simd uop (57) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | ldst uops in schedulers (5b) | 60 | 69 | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map simd uop (7e) | map int uop inputs (7f) | map ldst uop inputs (80) | map simd uop inputs (81) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | 91 | inst branch cond (94) | inst int alu (97) | inst simd store (99) | inst ldst (9b) | 9f | l1d tlb access (a0) | l1d tlb miss (a1) | l1d cache miss st (a2) | l1d cache miss ld (a3) | a4 | ld unit uop (a6) | st unit uop (a7) | l1d cache writeback (a8) | a9 | ac | af | bc | l1d cache miss st nonspec (c0) | l1d tlb miss nonspec (c1) | c2 | c9 | cf | d0 | d5 | map dispatch bubble (d6) | db | dd | fetch restart (de) | e0 | ? int output thing (e9) | ? ldst retires (ed) | ? simd retires (ee) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
240027 | 80040 | 621 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | 3033 | 0 | 80025 | 8 | 8 | 0 | 25 | 323063 | 80010 | 162555 | 80000 | 80010 | 160000 | 80000 | 4407672 | 3758411 | 1489540 | 0 | 80015 | 80040 | 80040 | 49946 | 3 | 50020 | 320010 | 20 | 80120 | 160000 | 20 | 240000 | 400000 | 80040 | 80040 | 1 | 1 | 80021 | 10 | 9 | 0 | 10 | 10 | 80000 | 80000 | 10 | 80000 | 0 | 17 | 0 | 0 | 0 | 80001 | 0 | 0 | 4 | 80060 | 1 | 17 | 0 | 0 | 0 | 5020 | 0 | 3 | 16 | 2 | 3 | 3 | 80037 | 80000 | 80000 | 160000 | 80010 | 80041 | 80041 | 80041 | 80041 | 80041 |
240024 | 80040 | 621 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 2919 | 0 | 80025 | 8 | 8 | 0 | 25 | 323116 | 80010 | 163316 | 80000 | 80010 | 160000 | 80000 | 4407672 | 3758405 | 1486604 | 0 | 80015 | 80040 | 80040 | 49946 | 3 | 50020 | 320010 | 20 | 80000 | 160000 | 20 | 240000 | 400000 | 80040 | 80040 | 1 | 1 | 80021 | 10 | 9 | 0 | 10 | 10 | 80000 | 80000 | 10 | 80000 | 0 | 17 | 0 | 0 | 0 | 80001 | 0 | 0 | 5 | 80000 | 1 | 17 | 0 | 0 | 0 | 5020 | 0 | 3 | 16 | 3 | 4 | 4 | 80037 | 80000 | 80000 | 160000 | 80010 | 80041 | 80041 | 80041 | 80169 | 80041 |
240024 | 80040 | 620 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 | 0 | 0 | 3022 | 0 | 80025 | 0 | 0 | 0 | 25 | 322941 | 80010 | 163229 | 80000 | 80010 | 160000 | 80000 | 4407672 | 3758405 | 1488788 | 0 | 80015 | 80040 | 80040 | 49946 | 19 | 50020 | 320010 | 20 | 80000 | 160000 | 20 | 240000 | 400000 | 80040 | 80040 | 1 | 1 | 80021 | 10 | 9 | 0 | 10 | 10 | 80000 | 80000 | 10 | 80000 | 0 | 17 | 0 | 0 | 0 | 80001 | 1 | 0 | 2 | 80001 | 0 | 17 | 0 | 0 | 0 | 5020 | 0 | 3 | 16 | 2 | 3 | 3 | 80037 | 80000 | 80000 | 160000 | 80010 | 80041 | 80041 | 80041 | 80041 | 80041 |
240024 | 80040 | 621 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | 2654 | 0 | 80025 | 8 | 8 | 0 | 25 | 323357 | 80010 | 163240 | 80000 | 80010 | 160000 | 80000 | 4407672 | 3758405 | 1487821 | 0 | 80015 | 80040 | 80040 | 49946 | 3 | 50020 | 320010 | 20 | 80000 | 160000 | 20 | 240000 | 400000 | 80040 | 80040 | 1 | 1 | 80021 | 10 | 9 | 0 | 10 | 10 | 80000 | 80000 | 10 | 80000 | 0 | 17 | 0 | 0 | 0 | 80001 | 0 | 0 | 2 | 80001 | 1 | 17 | 0 | 0 | 0 | 5038 | 0 | 3 | 16 | 3 | 3 | 3 | 80037 | 80000 | 80000 | 160000 | 80010 | 80041 | 80041 | 80041 | 80041 | 80041 |
240024 | 80040 | 620 | 0 | 0 | 0 | 0 | 1 | 0 | 24 | 1 | 0 | 0 | 0 | 2855 | 0 | 80025 | 8 | 8 | 0 | 25 | 323165 | 80010 | 162882 | 80000 | 80010 | 160000 | 80000 | 4407672 | 3758405 | 1486469 | 0 | 80015 | 80040 | 80040 | 49946 | 3 | 50020 | 320010 | 20 | 80000 | 160000 | 20 | 240000 | 400000 | 80040 | 80040 | 1 | 1 | 80021 | 10 | 9 | 0 | 10 | 10 | 80000 | 80000 | 10 | 80000 | 0 | 17 | 0 | 0 | 0 | 80001 | 2 | 0 | 8 | 80001 | 0 | 17 | 0 | 0 | 0 | 5020 | 12 | 3 | 16 | 0 | 3 | 3 | 80037 | 80000 | 80000 | 160000 | 80010 | 80041 | 80041 | 80171 | 80041 | 80041 |
240024 | 80040 | 620 | 0 | 0 | 0 | 0 | 0 | 0 | 12 | 2 | 0 | 0 | 0 | 3003 | 0 | 80025 | 8 | 8 | 0 | 25 | 322912 | 80010 | 163328 | 80000 | 80010 | 160000 | 80000 | 4409485 | 3758405 | 1486041 | 0 | 80015 | 80040 | 80040 | 49946 | 3 | 50020 | 320010 | 20 | 80000 | 160000 | 20 | 240360 | 400000 | 80040 | 80040 | 1 | 1 | 80021 | 10 | 9 | 0 | 10 | 10 | 80000 | 80000 | 10 | 80000 | 0 | 17 | 0 | 0 | 0 | 80001 | 0 | 0 | 2 | 80001 | 1 | 17 | 0 | 0 | 0 | 5020 | 6 | 3 | 16 | 0 | 3 | 3 | 80037 | 80000 | 80000 | 160000 | 80010 | 80041 | 80041 | 80041 | 80041 | 80041 |
240024 | 80040 | 620 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | 2506 | 0 | 80025 | 8 | 8 | 0 | 25 | 322919 | 80010 | 162912 | 80000 | 80010 | 160000 | 80000 | 4407672 | 3758405 | 1486240 | 0 | 80015 | 80040 | 80040 | 49946 | 3 | 50020 | 320010 | 20 | 80000 | 160000 | 20 | 240000 | 400000 | 80040 | 80040 | 1 | 1 | 80021 | 10 | 9 | 4 | 10 | 10 | 80000 | 80000 | 10 | 80000 | 0 | 17 | 0 | 0 | 0 | 80001 | 0 | 0 | 2 | 80001 | 1 | 17 | 0 | 0 | 0 | 5020 | 6 | 3 | 16 | 0 | 3 | 3 | 80144 | 80000 | 80000 | 160000 | 80010 | 80041 | 80041 | 80041 | 80041 | 80041 |
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