Firestorm: STNP (D) measurements

Code:

  stnp d0, d1, [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 7 nops): 2.000

Issues: 2.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 1.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	19	1e	1f	3d	3f	46	49	51	schedule uop (52)	schedule simd uop (54)	schedule ldst uop (55)	dispatch simd uop (57)	dispatch ldst uop (58)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	61	69	6d	6e	rob full (74)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd store (99)	inst ldst (9b)	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	cf	d0	d2	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	st nt uop (e5)	ea	eb	? ldst retires (ed)	? simd retires (ee)	f5	f6	f7	f8	fd
9006	1166	10	1	1	1	0	0	7	4	1151	15	16	25	2000	1000	1000	1000	1000	10875	8000	1	0	1145	1385	1166	11	3	389	2076	1000	1039	2000	2076	1527	1166	2	1	8001	1000	1000	1007	13	1038	0	1007	0	1	7	1000	7	1000	7	0	513	0	0	2	16	2	2	1163	1007	0	9	1000	1000	1167	1167	1167	1167	1167
9004	1402	11	1	2	0	1	9	95	4	1151	16	16	25	2000	1000	1000	1000	1000	10878	8016	0	0	1145	1166	1166	0	3	24	2000	1000	1000	2000	2000	1166	1166	1	1	8001	1000	1000	1008	8	1000	0	1007	0	0	7	1000	7	1000	7	0	513	0	0	2	16	2	2	1163	1007	0	5	1000	1000	1167	1167	1167	1167	1167
9004	1166	10	1	1	0	0	0	7	4	1151	16	16	25	2000	1000	1000	1000	1000	10875	8000	1	0	1145	1166	1166	0	3	24	2000	1000	1000	2000	2000	1166	1166	1	1	8001	1000	1000	1008	9	1000	2	1007	0	0	7	1000	7	1000	7	1	513	0	0	2	16	2	2	1163	1007	0	9	1000	1000	1167	1167	1167	1167	1167
9004	1166	11	1	0	1	0	0	7	4	1151	16	16	25	2000	1000	1000	1000	1000	10875	8000	0	0	1145	1166	1166	0	3	24	2000	1000	1000	2000	2000	1166	1166	1	1	8001	1000	1000	1007	8	1000	1	1007	0	1	16	1000	7	1000	7	0	513	0	0	2	16	2	2	1163	1007	0	6	1000	1000	1167	1167	1167	1167	1167
9004	1166	11	1	1	1	0	0	7	4	1151	15	16	25	2000	1000	1000	1000	1000	10875	8000	0	0	1145	1166	1166	0	3	24	2000	1000	1000	2000	2000	1166	1166	1	1	8001	1000	1000	1000	0	1000	0	1000	0	2	0	1000	0	1000	0	0	513	0	0	2	16	2	2	1163	1000	0	5	1000	1000	1167	1167	1167	1167	1167
9004	1166	10	0	0	0	0	6	0	4	1151	15	16	25	2000	1000	1000	1000	1000	10875	8000	0	0	1145	1166	1166	0	3	24	2000	1000	1038	2000	2000	1166	1166	1	1	8001	1000	1000	1000	0	1000	0	1000	0	0	0	1000	0	1000	0	0	513	0	0	2	16	2	2	1163	1000	0	5	1000	1000	1167	1167	1167	1167	1167
9004	1166	11	0	0	0	0	0	0	4	1151	15	16	25	2000	1000	1000	1000	1000	10875	8000	0	0	1145	1166	1166	0	3	24	2000	1000	1000	2000	2000	1166	1166	1	1	8001	1000	1000	1000	0	1000	0	1000	0	0	3	1000	0	1000	0	0	513	0	0	2	16	2	2	1163	1000	0	5	1000	1000	1167	1167	1167	1167	1167
9004	1166	11	0	0	0	0	0	0	4	1151	15	16	25	2000	1000	1000	1000	1000	10875	8000	0	0	1145	1166	1166	0	3	24	2000	1000	1000	2000	2000	1166	1166	1	1	8001	1000	1000	1000	0	1000	0	1000	0	0	0	1000	0	1000	0	0	513	0	0	2	16	2	2	1163	1000	0	5	1000	1000	1167	1167	1167	1167	1167
9004	1166	11	0	0	0	0	3	0	4	1151	15	16	25	2000	1000	1000	1000	1000	10875	8000	1	0	1145	1166	1166	0	3	24	2000	1000	1000	2000	2000	1166	1166	1	1	8001	1000	1000	1000	0	1000	0	1000	0	0	0	1000	0	1000	0	0	513	0	0	2	16	2	2	1163	1000	0	5	1000	1000	1167	1167	1167	1167	1167
9004	1166	11	0	0	0	0	0	0	4	1151	15	16	25	2000	1000	1000	1000	1000	10875	8000	0	0	1145	1166	1166	0	3	24	2000	1000	1000	2000	2000	1166	1166	1	1	8001	1000	1000	1000	0	1000	0	1000	0	0	0	1000	0	1000	0	0	513	0	0	2	16	2	2	1163	1000	0	6	1000	1000	1167	1167	1167	1167	1167

Count: 8

Code:

  stnp d0, d1, [x6]
  stnp d0, d1, [x6]
  stnp d0, d1, [x6]
  stnp d0, d1, [x6]
  stnp d0, d1, [x6]
  stnp d0, d1, [x6]
  stnp d0, d1, [x6]
  stnp d0, d1, [x6]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5189

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	37	3d	3f	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd store (99)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	l1d cache miss st nonspec (c0)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	st nt uop (e5)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160206	41512	311	0	0	0	0	0	63	0	550	148	41497	1184	1184	1466	25	163096	100	82791	80000	100	80000	80000	500	1910080	648379	0	41487	41513	41512	21425	3	21471	160100	200	80000	80000	200	160000	160000	41513	41512	1	1	80201	100	99	100	100	80000	80000	100	80000	0	80000	882	0	80000	0	0	0	80000	80000	0	5110	1	16	1	1	41509	80000	0	80000	80000	100	41513	41514	41513	41514	41513
160204	41512	310	0	0	0	0	0	0	0	2791	148	41498	1156	1162	1320	25	162983	100	82970	80000	100	80000	80000	500	1910080	648379	0	41494	41514	41513	21426	3	21471	160100	200	80000	80000	200	160000	160000	41513	41512	1	1	80201	100	99	100	100	80000	80000	100	80000	0	80000	735	0	80000	0	0	0	80000	80000	0	5110	1	16	1	1	41509	80000	0	80000	80000	100	41513	41514	41513	41514	41513
160204	41512	311	0	0	0	4	0	3	0	880	148	41498	1184	1184	1320	25	163361	100	84030	80000	100	80000	80000	500	1910080	648379	0	41488	41512	41513	21426	3	21470	160100	200	80000	80000	200	160000	160000	41513	41512	1	1	80201	100	99	100	100	80000	80000	100	80000	0	80000	735	0	80000	0	0	0	80000	80000	0	5110	1	16	1	1	41509	80000	0	80000	80000	100	41514	41513	41514	41513	41514
160204	41513	311	0	0	0	0	0	0	0	2996	148	41498	1184	1184	1320	25	163070	100	82883	80000	100	80000	80000	500	1910080	649004	0	41488	41512	41513	21426	3	21471	160100	200	80000	80000	200	160000	160000	41513	41512	1	1	80201	100	99	100	100	80000	80000	100	80000	0	80000	735	0	80000	0	0	0	80000	80000	0	5110	1	16	1	1	41509	80000	0	80000	80000	100	41514	41513	41514	41513	41514
160204	41513	311	0	0	0	0	0	0	0	3529	148	41498	1184	1184	1320	25	163070	100	82883	80000	100	80000	80000	500	1910080	649004	1	41487	41513	41512	21425	3	21470	160100	200	80000	80000	200	160000	160000	41513	41512	1	1	80201	100	99	100	100	80000	80000	100	80000	0	80000	735	0	80000	0	0	3	80000	80000	0	5110	1	16	1	1	41510	80000	0	80000	80000	100	41513	41514	41513	41514	41514
160204	41513	311	0	0	0	0	0	0	0	3446	148	41497	1184	1184	1466	25	163096	100	82791	80000	100	80000	80000	500	1910128	648289	1	41487	41513	41512	21425	3	21470	160100	200	80000	80000	200	160000	160000	41512	41513	1	1	80201	100	99	100	100	80000	80000	100	80000	0	80000	882	0	80000	0	0	0	80000	80000	0	5110	1	16	1	1	41510	80000	0	80000	80000	100	41514	41513	41514	41513	41514
160204	41513	311	0	0	0	0	0	0	0	2970	148	41498	1184	1184	1320	25	163070	100	82770	80000	100	80000	80000	500	1910080	648379	1	41488	41512	41513	21426	3	21471	160100	200	80000	80000	200	160000	160000	41513	41512	1	1	80201	100	99	100	100	80000	80000	100	80000	0	80000	735	0	80000	0	0	0	80000	80000	0	5110	1	16	1	1	41510	80000	0	80000	80000	100	41513	41514	41513	41514	41513
160204	41512	311	0	0	0	0	0	0	0	880	148	41498	1184	1184	1320	25	160804	100	82883	80000	100	80000	80000	500	1910080	648295	1	41488	41512	41513	21426	3	21471	160100	200	80000	80000	200	160000	160000	41512	41513	1	1	80201	100	99	100	100	80000	80000	100	80000	0	80000	735	0	80000	0	0	0	80000	80000	0	5110	1	16	1	1	41510	80000	0	80000	80000	100	41513	41514	41513	41514	41513
160204	41512	311	0	0	0	0	0	0	0	2791	148	41498	1184	1184	1320	25	162984	100	82218	80000	100	80000	80000	500	1910080	643183	0	41487	41513	41512	21425	3	21470	160100	200	80000	80000	200	160000	160000	41512	41513	1	1	80201	100	99	100	100	80000	80000	100	80000	0	80060	735	0	80000	0	0	0	80000	80000	0	5110	1	16	1	1	41510	80000	0	80000	80000	100	41513	41514	41513	41514	41513
160204	41512	311	0	0	0	0	0	0	0	2226	148	41498	1184	1184	1320	25	163463	100	82759	80000	100	80000	80000	500	1910080	648604	0	41488	41512	41517	21426	3	21471	160100	200	80000	80000	200	160000	160000	41513	41512	1	1	80201	100	99	100	100	80000	80000	100	80000	0	80000	882	0	80000	0	0	0	80000	80000	0	5110	1	16	1	1	41509	80000	0	80000	80000	100	41514	41513	41514	41513	41514

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5189

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	1f	37	3d	3f	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd store (99)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	st nt uop (e5)	ea	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160026	41522	310	1	1	0	0	1	0	0	0	14	2850	148	41510	1184	1184	1473	25	162143	10	80478	80000	10	80000	80000	50	1910536	648004	0	41498	0	41520	41521	21459	3	21501	160010	20	80000	80000	20	160000	160000	41525	41523	1	1	80021	10	9	10	10	80000	80000	10	80000	0	80000	735	0	80000	0	0	0	80000	0	80000	0	0	5020	11	16	2	2	41509	80000	0	80000	80000	10	41514	41513	41514	41513	41514
160024	41513	311	0	0	0	0	0	0	0	0	0	3108	148	41498	1184	1184	1320	25	162682	10	82673	80000	10	80000	80000	50	1910080	649324	0	41495	0	41523	41523	21457	3	21506	160010	20	80000	80000	20	160000	160000	41523	41523	1	1	80021	10	9	10	10	80000	80000	10	80000	0	80000	735	0	80000	0	0	0	80000	14	80000	14	1	5020	6	16	2	6	41520	80014	0	80000	80000	10	41523	41524	41524	41521	41523
160024	41525	311	1	0	0	0	0	0	0	0	14	3370	148	41508	1184	1184	1325	25	161074	10	81810	80000	10	80000	80000	50	1910560	648262	1	41498	0	41523	41522	21459	3	21503	160010	20	80000	80000	20	160000	160000	41523	41523	1	1	80021	10	9	10	10	80000	80000	10	80014	14	80000	882	2	80014	0	0	14	80000	14	80000	14	1	5020	3	16	3	6	41520	80014	0	80000	80000	10	41524	41524	41526	41523	41524
160024	41520	311	1	2	0	0	1	0	0	0	14	2705	148	41508	1184	1184	1473	25	163309	10	82832	80000	10	80000	80000	50	1910608	641450	1	41495	0	41523	41523	21457	3	21506	160010	20	80000	80000	20	160000	160000	41523	41523	1	1	80021	10	9	10	10	80000	80000	10	80015	14	80000	882	0	80014	0	0	14	80000	14	80000	14	1	5020	2	16	2	2	41520	80014	0	80000	80000	10	41522	41524	41524	41521	41522
160024	41523	311	1	1	0	0	1	0	0	0	14	555	148	41511	1184	1184	1325	25	162765	10	82828	80000	10	80000	80000	50	1910608	648728	1	41498	0	41523	41523	21457	3	21501	160010	20	80000	80000	20	160000	160000	41525	41523	1	1	80021	10	9	10	10	80000	80000	10	80014	15	80000	736	1	80014	0	0	14	80000	14	80000	14	1	5020	2	16	2	6	41523	80014	0	80000	80000	10	41524	41524	41521	41524	41524
160024	41521	311	1	0	0	0	0	0	0	0	14	2657	148	41497	1184	1184	1466	25	162970	10	82960	80000	10	80000	80000	50	1910128	647971	1	41487	0	41512	41513	21449	3	21493	160010	20	80000	80000	20	160000	160000	41513	41512	1	1	80021	10	9	10	10	80000	80000	10	80000	0	80000	735	0	80000	0	0	0	80000	0	80000	0	0	5020	2	16	2	6	41509	80000	0	80000	80000	10	41514	41637	41514	41513	41514
160024	41513	311	0	0	0	0	0	0	0	0	14	2950	148	41508	1184	1184	1320	25	162716	10	82349	80000	10	80000	80000	50	1910080	649324	1	41487	0	41512	41512	21448	3	21492	160010	20	80000	80000	20	160000	160000	41512	41513	1	1	80021	10	9	10	10	80000	80000	10	80000	0	80000	882	0	80000	0	0	0	80000	0	80000	0	0	5020	3	16	2	6	41510	80000	0	80000	80000	10	41513	41514	41513	41514	41513
160024	41512	311	0	0	0	0	0	0	0	0	0	3108	148	41498	1184	1184	1320	25	162683	10	82672	80000	10	80000	80000	50	1910080	641092	0	41488	0	41513	41512	21448	3	21492	160010	20	80000	80000	20	160000	160000	41512	41513	1	1	80021	10	9	10	10	80000	80000	10	80000	0	80000	882	0	80000	0	0	0	80000	0	80000	0	0	5020	2	16	6	2	41509	80000	0	80000	80000	10	41514	41513	41514	41513	41514
160024	41513	314	0	0	0	0	0	0	0	0	0	3088	148	41497	1184	1184	1466	25	163118	10	83108	80000	10	80000	80000	50	1910080	648655	0	41488	0	41513	41512	21448	3	21492	160010	20	80000	80000	20	160000	160000	41512	41513	1	1	80021	10	9	10	10	80000	80000	10	80000	0	80000	882	0	80000	0	0	0	80000	0	80000	0	0	5020	2	16	6	2	41510	80000	0	80000	80000	10	41514	41513	41514	41513	41514
160024	41513	311	0	0	0	0	0	0	0	0	0	2707	148	41497	1184	1184	1466	25	163118	10	83107	80000	10	80000	80000	50	1910128	648119	0	41488	0	41513	41512	21448	3	21492	160010	20	80000	80000	20	160000	160000	41512	41513	1	1	80021	10	9	10	10	80000	80000	10	80000	0	80000	882	0	80000	0	0	0	80000	0	80000	0	0	5020	2	16	6	2	41510	80000	0	80000	80000	10	41513	41514	41513	41514	41513

STNP (D)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations