Firestorm: STNP (S) measurements

Code:

  stnp s0, s1, [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 7 nops): 2.000

Issues: 2.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 1.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	1f	3a	3d	3f	46	49	51	schedule uop (52)	schedule simd uop (54)	schedule ldst uop (55)	dispatch simd uop (57)	dispatch ldst uop (58)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	rob full (74)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd store (99)	inst ldst (9b)	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	l1d cache miss st nonspec (c0)	c2	cf	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	st nt uop (e5)	? ldst retires (ed)	? simd retires (ee)	f5	f6	f7	f8	fd
9006	1465	13	0	0	0	0	1	2	132	0	0	5	1151	11	15	313	2000	1003	1076	1076	1038	12015	8000	1	1319	1390	1166	11	3	24	2000	1000	1038	2000	2000	1189	1374	1	1	8001	1000	1000	1000	0	1000	0	1038	1	9	6	1039	1000	4	515	0	11	47	9	8	1163	1038	1000	1000	1167	1167	1512	1190	2040
9004	1522	15	0	1	0	0	0	0	60	0	0	4	1151	13	13	25	2076	1076	1076	1000	1000	11987	8304	1	1145	1626	1190	0	3	329	2096	1038	1039	2046	2000	1166	1535	2	1	8001	1000	1000	1000	0	1039	0	1000	0	0	0	1038	1000	2	547	0	9	32	8	9	1163	1038	1000	1000	1192	1866	1462	1506	1466
9004	1196	9	0	0	0	0	1	0	132	176	0	4	1484	13	9	595	2000	1000	1000	1000	1000	10875	8000	1	1296	1426	1166	0	13	369	2152	1038	1000	2076	2000	1166	1403	2	1	8001	1000	1000	1000	0	1076	0	1000	0	0	229	1000	1000	0	515	0	9	16	11	10	1229	1038	1000	1000	1167	1167	1167	1190	1167
9004	1505	12	0	0	1	0	0	0	0	0	0	4	1151	13	13	25	2076	1000	1000	1039	1000	11975	8608	1	1145	1530	1166	0	3	25	2076	1000	1000	2000	2000	1429	1166	1	1	8001	1000	1000	1000	0	1000	2	1000	1	0	6	1038	1000	0	515	0	9	23	11	9	1163	1000	1000	1000	1167	1167	1167	1167	1192
9004	1445	9	0	0	0	0	1	0	9	88	1	4	1151	14	11	25	2000	1000	1000	1038	1000	10875	8000	1	1145	1166	1166	0	3	261	2000	1000	1000	2078	2000	1539	1166	1	1	8001	1000	1000	1040	0	1000	2	1038	0	4	220	1038	1000	4	548	0	10	38	11	9	1273	1000	1000	1000	1190	1167	1167	1167	1440
9004	1166	13	0	1	0	0	0	0	171	0	0	4	1151	13	13	25	2000	1000	1000	1000	1000	10875	8000	1	1145	1166	1166	0	3	24	2000	1000	1000	2000	2000	1166	1166	1	1	8001	1000	1000	1000	0	1000	0	1000	1	0	0	1000	1000	0	515	0	8	16	8	8	1163	1000	1000	1000	1167	1167	1167	1167	1167
9004	1166	9	0	0	0	0	1	0	0	0	0	4	1151	13	11	25	2000	1000	1000	1000	1000	10875	8304	1	1145	1166	1166	0	3	24	2000	1000	1000	2000	2000	1166	1166	1	1	8001	1000	1000	1038	2	1000	0	1000	0	0	0	1038	1000	0	515	0	8	25	8	9	1251	1000	1000	1000	1167	1167	1558	1880	1595
9004	1938	9	0	0	0	0	0	0	132	0	0	4	1151	13	13	25	2078	1000	1039	1000	1065	10875	8616	1	1170	1166	1189	0	3	24	2000	1038	1039	2000	2000	1166	1482	1	1	8001	1000	1000	1000	0	1000	0	1038	0	0	21	1000	1000	0	575	0	9	46	8	9	1186	1064	1000	1000	1458	1167	1167	1586	1577
9004	1166	11	0	1	0	1	0	1	264	0	0	5	1174	12	13	393	2000	1000	1000	1000	1000	10875	8312	0	1145	1166	1166	0	3	24	2000	1000	1000	2000	2000	1166	1166	1	1	8001	1000	1000	1000	0	1000	0	1038	0	0	3	1000	1000	0	515	0	9	16	8	9	1332	1010	1000	1000	1167	1191	1167	1167	1908
9004	1495	16	1	0	0	0	0	0	9	0	0	4	1609	15	11	25	2000	1000	1038	1038	1000	11976	8312	0	1234	1166	1497	0	13	24	2076	1038	1039	2000	2000	1166	1512	2	1	8001	1000	1000	1042	0	1037	2	1038	0	0	3	1000	1000	0	515	0	7	16	8	8	1163	1000	1000	1000	1491	1560	1560	1190	1167

Count: 8

Code:

  stnp s0, s1, [x6]
  stnp s0, s1, [x6]
  stnp s0, s1, [x6]
  stnp s0, s1, [x6]
  stnp s0, s1, [x6]
  stnp s0, s1, [x6]
  stnp s0, s1, [x6]
  stnp s0, s1, [x6]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5189

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	37	3d	3f	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd store (99)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	st nt uop (e5)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160206	41492	311	0	0	0	0	0	0	2811	146	41478	1168	1168	1446	25	162961	100	82800	80000	100	80000	80000	500	1909168	648602	0	41467	42067	41493	21406	3	21450	160100	200	80000	80000	200	160000	160000	41493	41492	1	1	80201	100	99	100	100	80000	80000	100	80000	15	80000	725	0	80000	0	0	0	80000	0	80000	0	0	5110	1	16	1	1	41490	80000	0	80000	80000	100	41493	41510	41505	41493	41494
160204	41493	310	0	0	0	0	0	0	2862	146	41477	1168	1168	1302	25	162962	100	82862	80000	100	80000	80000	500	1909120	648510	0	41468	41493	41630	21406	3	21451	160100	200	80000	80000	200	160000	160000	41493	41492	1	1	80201	100	99	100	100	80000	80000	100	80000	14	80000	725	0	80000	0	0	0	80000	0	80000	0	0	5110	1	16	1	1	41489	80000	0	80000	80000	100	41494	41501	41506	41507	41493
160204	41492	311	0	0	0	0	0	0	2861	146	41477	1168	1168	1302	25	162961	100	82861	80000	100	80000	80000	500	1909120	648514	1	41467	41492	41493	21406	3	21451	160100	200	80000	80000	200	160000	160000	41493	41492	1	1	80201	100	99	100	100	80000	80000	100	80000	14	80000	870	0	80000	0	0	0	80000	0	80000	0	0	5110	1	16	1	1	41489	80000	0	80000	80000	100	41494	41504	41504	41494	41619
160204	41493	311	0	0	0	0	0	0	2818	146	41478	1168	1168	1450	25	163371	100	82259	80000	100	80000	80000	500	1909168	648602	0	41467	41492	41493	21406	3	21451	160100	200	80000	80000	200	160000	160000	41493	41492	1	1	80201	100	99	100	100	80000	80000	100	80000	14	80000	870	0	80000	0	0	0	80000	0	80000	0	0	5110	1	16	1	1	41489	80000	0	80000	80000	100	41494	41504	41506	41507	41494
160204	41493	311	0	0	0	0	0	0	2862	146	41477	1168	1168	1446	1549	162931	100	83392	80000	100	80000	80000	500	1909168	648602	1	41467	41492	41493	21406	3	21451	160100	200	80000	80000	200	160000	160000	41493	41492	1	1	80201	100	99	100	100	80000	80000	100	80005	14	80000	725	0	80000	0	0	0	80000	0	80000	0	0	5110	1	16	1	1	41490	80000	0	80000	80000	100	41493	41508	41506	41496	41493
160204	41492	311	0	0	0	0	0	0	2832	146	41478	1168	1168	1302	25	163521	100	82862	80000	100	80000	80000	500	1909120	648514	0	41468	41492	41493	21406	3	21451	160100	200	80000	80000	200	160000	160000	41493	41492	1	1	80201	100	99	100	100	80000	80000	100	80000	14	80000	725	0	80000	0	0	0	80000	0	80000	0	0	5110	1	16	1	1	41490	80000	0	80000	80000	100	41493	41504	41503	41494	41493
160204	41492	311	0	0	0	0	0	0	2832	146	41478	1168	1168	1446	25	162931	100	82832	80000	100	80000	80000	500	1909168	648602	0	41467	41492	41493	21406	3	21451	160100	200	80000	80000	200	160000	160000	41493	41492	1	1	80201	100	99	100	100	80000	80000	100	80000	14	80000	870	0	80000	4	0	0	80000	0	80000	0	0	5110	1	16	1	1	41489	80000	0	80000	80000	100	41493	41512	41504	41493	41494
160204	41493	310	0	0	0	0	0	0	2832	146	41478	1168	1168	1303	25	162900	100	83421	80000	100	80000	80000	500	1909120	648514	0	41468	41493	41492	21405	3	21450	160100	200	80000	80000	200	160000	160000	41492	41493	1	1	80201	100	99	100	100	80000	80000	100	80000	14	80000	725	0	80000	0	0	0	80000	0	80000	0	0	5110	1	16	1	1	41490	80000	0	80000	80000	100	41493	41504	41506	41496	41493
160204	41492	310	0	0	0	0	0	0	957	146	41477	1168	1168	1304	25	162962	100	82767	80000	100	80000	80000	500	1909120	648457	0	41468	41493	41492	21405	3	21450	160100	200	80000	80000	200	160000	160000	41492	41493	1	1	80201	100	99	100	100	80000	80000	100	80000	14	80000	870	0	80000	1	0	0	80000	0	80000	0	0	5110	1	16	1	1	41490	80000	0	80000	80000	100	41493	41503	41523	41493	41494
160204	41493	321	0	0	0	0	0	0	2832	146	41478	1168	1168	1303	25	162962	100	82835	80000	100	80000	80000	500	1909168	648597	0	41467	41492	41493	21406	3	21451	160100	200	80000	80000	200	160000	160000	41493	41492	1	1	80201	100	99	100	100	80000	80000	100	80000	14	80000	870	0	80000	5	0	0	80000	0	80000	0	0	5110	1	16	1	1	41490	80000	0	80000	80000	100	41493	41506	41504	41495	41494

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5189

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	37	3d	3f	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	61	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd store (99)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	l1d cache miss st nonspec (c0)	cf	d0	d5	map dispatch bubble (d6)	d8	db	dd	fetch restart (de)	e0	st nt uop (e5)	eb	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160026	41492	317	0	0	0	1	144	3326	146	41478	1164	1168	1857	25	162673	10	82903	80000	10	80000	80000	50	1909168	650466	0	0	41595	42288	41493	21429	15	21472	160010	20	80000	80140	20	160288	160000	42884	41493	2	1	80021	10	9	10	10	80000	80000	10	80014	4	80012	870	0	80017	0	0	0	80000	80000	5034	0	4	34	256	0	3	4	41490	80000	0	80000	80000	10	41495	41494	41495	42354	41869
160024	41492	311	0	0	0	0	0	2903	146	41477	1168	1168	1302	25	162910	10	82900	80000	10	80000	80064	50	1909120	648379	0	0	41856	41493	42288	21880	3	21472	160010	20	80136	80000	20	160000	160256	41492	42598	1	1	80021	10	9	10	10	80000	80000	10	80000	0	80033	870	0	80000	0	0	0	80000	80000	5020	0	4	16	0	0	6	4	41489	80000	0	80000	80000	10	41495	42536	41493	41494	41493
160024	41767	311	1	1	0	0	0	1297	149	42308	1162	1168	1302	25	162924	10	82782	80000	10	80132	80000	50	1909120	650352	0	0	41467	41492	41493	21429	3	23038	160010	20	80000	80068	20	160000	160000	41493	41492	1	1	80021	10	9	10	10	80000	80000	10	80000	0	80000	725	0	80000	0	0	0	80000	80000	5020	0	7	16	0	0	3	4	41490	80000	0	80000	80000	10	41495	42569	41493	41494	42447
160024	41493	320	0	0	1	0	0	3195	151	42648	1168	1168	1446	25	162804	10	82793	80000	10	80000	80000	50	1909168	647990	0	0	41467	41492	41493	21429	3	21473	160010	20	80000	80000	20	160000	160000	41493	41492	1	1	80021	10	9	10	10	80000	80000	10	80000	0	80000	725	0	80000	0	0	0	80000	80000	5020	0	4	16	0	0	3	4	41490	80000	0	80000	80000	10	41495	41494	41493	41494	41493
160024	41492	311	0	0	0	0	0	3330	146	41478	1143	1168	1302	25	162261	10	82488	80000	10	80000	80000	50	1909120	648383	0	0	41468	41493	41492	21752	3	23101	160010	20	80000	80000	20	160000	160000	41493	41493	1	1	80021	10	9	10	10	80000	80000	10	80000	0	80000	870	0	80000	0	0	0	80000	80000	5020	0	4	16	0	0	4	4	41489	80000	0	80000	80000	10	41494	41493	41496	41493	44466
160024	41493	311	1	0	0	0	0	2903	146	41477	1168	1168	1450	25	162803	10	82794	80000	10	80000	80000	50	1909168	648711	1	0	41467	41492	41493	21429	3	21473	160010	20	80000	80000	20	160000	160000	41493	41492	1	1	80021	10	9	10	10	80000	80000	10	80000	0	80000	870	0	80000	0	0	0	80000	80000	5020	0	4	16	0	0	7	4	41490	80000	0	80000	80000	10	41494	41493	41494	41493	41494
160024	41493	311	0	0	0	0	0	2793	146	41478	1168	1168	1446	25	162803	10	82793	80000	10	80000	80000	50	1909168	648711	1	0	41467	41492	41493	21429	3	21473	160010	20	80000	80000	20	160000	160000	41493	41492	1	1	80021	10	9	10	10	80000	80000	10	80000	0	80000	870	0	80000	0	0	0	80000	80000	5020	0	4	16	0	0	4	3	41489	80000	0	80000	80000	10	41493	41493	41494	41493	41494
160024	41493	311	0	0	0	0	0	1604	146	43404	1168	1168	1952	633	162673	10	81405	80000	10	80000	80000	50	1916081	648367	0	0	41468	41493	41492	21428	3	21473	160010	20	80000	80000	20	160000	160000	41493	41492	1	1	80021	10	9	10	10	80000	80000	10	80000	0	80000	870	2	80000	0	0	15	80000	80000	5020	0	7	16	0	0	4	4	41489	80000	0	80000	80000	10	41494	41495	41494	41493	41494
160024	41493	311	0	0	0	0	6	2113	150	41499	1184	1184	1466	25	162337	10	82761	80013	10	80000	80000	50	1910128	648076	0	0	41487	41512	41513	21449	3	21493	160010	20	80000	80000	20	160000	160000	41513	41512	1	1	80021	10	9	10	10	80000	80000	10	80000	0	80000	735	0	80000	0	0	0	80000	80000	5020	0	7	16	0	0	7	6	41510	80000	0	80000	80000	10	41514	41515	41514	41513	41514
160024	41513	311	0	0	0	0	0	2122	148	41497	1184	1184	1466	25	162746	10	83236	80000	10	80000	80000	50	1910128	646340	0	0	41487	41512	41513	21449	3	21493	160010	20	80000	80000	20	160000	160000	41513	41512	1	1	80021	10	9	10	10	80000	80000	10	80000	0	80000	735	0	80000	0	0	0	80000	80000	5020	4	7	16	0	0	7	6	41510	80000	0	80000	80000	10	41515	41514	41513	41514	41513

STNP (S)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations