Firestorm: STNP (signed offset, D) measurements

Code:

  stnp d0, d1, [x6, #0x10]
  nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 7 nops): 2.000

Issues: 2.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 1.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	1e	1f	3d	3f	46	49	51	schedule uop (52)	schedule simd uop (54)	schedule ldst uop (55)	dispatch simd uop (57)	dispatch ldst uop (58)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd store (99)	inst ldst (9b)	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	st nt uop (e5)	? ldst retires (ed)	? simd retires (ee)	f5	f6	f7	f8	fd
9006	1166	8	0	0	0	0	0	4	1151	15	16	25	2000	1000	1000	1000	1000	10875	8000	1145	1166	1166	3	24	2000	1000	1000	2000	2000	1166	1166	1	1	8001	1000	1000	1000	0	1000	0	1000	0	0	0	1000	0	1000	0	0	512	1	16	1	1	1163	1007	1000	1000	1167	1167	1167	1167	1167
9004	1166	9	1	1	1	0	0	4	1151	15	16	25	2000	1000	1000	1000	1000	10875	8000	1145	1166	1166	3	24	2000	1000	1000	2000	2000	1166	1166	1	1	8001	1000	1000	1000	0	1000	0	1000	0	0	0	1000	0	1000	0	0	512	1	16	1	1	1163	1007	1000	1000	1167	1167	1167	1167	1167
9004	1166	8	1	0	1	9	0	4	1151	15	16	25	2000	1000	1000	1000	1000	10875	8000	1145	1166	1166	3	24	2000	1000	1000	2000	2000	1166	1166	1	1	8001	1000	1000	1009	7	1000	0	1007	0	0	7	1000	7	1000	7	1	512	2	16	1	1	1163	1000	1000	1000	1167	1167	1167	1167	1167
9004	1166	9	0	0	0	0	7	4	1151	16	16	25	2000	1000	1000	1000	1000	10878	8000	1145	1166	1166	3	24	2000	1000	1000	2000	2000	1166	1166	1	1	8001	1000	1000	1000	0	1000	0	1000	0	0	0	1000	0	1000	0	0	512	1	16	1	1	1163	1007	1000	1000	1167	1167	1167	1167	1167
9004	1166	9	1	1	1	0	0	4	1151	15	16	25	2000	1000	1000	1000	1000	10875	8000	1145	1166	1166	3	24	2000	1000	1000	2000	2000	1166	1166	1	1	8001	1000	1000	1000	0	1000	0	1000	0	0	0	1000	0	1000	0	0	512	1	16	1	1	1163	1000	1000	1000	1167	1167	1167	1167	1167
9004	1166	8	0	0	0	0	0	4	1151	15	16	25	2000	1000	1000	1000	1000	10875	8000	1145	1166	1166	3	24	2000	1000	1000	2000	2000	1166	1166	1	1	8001	1000	1000	1000	0	1000	0	1000	0	0	0	1000	0	1000	0	0	512	1	16	1	1	1163	1000	1000	1000	1167	1167	1167	1167	1167
9004	1166	9	0	0	0	9	0	4	1151	15	16	25	2000	1000	1000	1000	1000	10875	8000	1145	1166	1166	3	24	2000	1000	1000	2000	2000	1166	1166	1	1	8001	1000	1000	1000	0	1000	0	1000	0	0	0	1000	0	1000	0	0	512	2	16	1	1	1163	1000	1000	1000	1167	1167	1167	1167	1167
9004	1166	9	0	0	0	12	0	4	1151	15	16	25	2000	1000	1000	1000	1000	10875	8000	1145	1166	1166	3	24	2000	1000	1000	2000	2000	1166	1166	1	1	8001	1000	1000	1009	8	1000	2	1007	0	1	7	1000	7	1000	7	0	512	1	16	1	1	1163	1000	1000	1000	1167	1167	1167	1167	1167
9004	1166	8	0	0	0	3	7	4	1151	16	16	25	2000	1000	1000	1000	1000	10878	8000	1145	1166	1166	3	24	2000	1000	1000	2000	2000	1166	1166	1	1	8001	1000	1000	1000	0	1000	0	1000	0	0	0	1000	0	1000	0	0	512	1	16	1	1	1163	1000	1000	1000	1167	1167	1167	1167	1167
9004	1166	9	0	0	0	0	0	4	1151	15	16	25	2000	1000	1000	1000	1000	10875	8000	1145	1166	1166	3	24	2000	1000	1000	2000	2000	1166	1166	1	1	8001	1000	1000	1008	8	1000	2	1007	5	0	7	1000	7	1000	7	0	512	1	16	1	1	1163	1000	1000	1000	1167	1167	1167	1167	1167

Count: 8

Code:

  stnp d0, d1, [x6, #0x10]
  stnp d0, d1, [x6, #0x10]
  stnp d0, d1, [x6, #0x10]
  stnp d0, d1, [x6, #0x10]
  stnp d0, d1, [x6, #0x10]
  stnp d0, d1, [x6, #0x10]
  stnp d0, d1, [x6, #0x10]
  stnp d0, d1, [x6, #0x10]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5189

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	l2 tlb miss data (0b)	18	19	1e	1f	37	3a	3d	3f	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	61	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd store (99)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	l1d cache miss st nonspec (c0)	c2	cf	d0	d2	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	st nt uop (e5)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160206	41512	311	0	0	0	0	108	0	2683	0	148	41497	1184	1184	1466	25	162340	100	82242	80000	100	80000	80000	500	1910080	646733	0	4	41488	0	41513	41512	21425	3	23472	160100	200	80000	80000	200	160000	160000	41512	41513	1	1	80201	100	99	100	100	80000	80000	100	80000	0	80000	735	0	80000	0	0	0	80000	80000	0	5110	0	0	1	16	1	1	41510	80000	0	80000	80000	100	41513	41514	41513	41514	41513
160204	41512	310	0	0	0	0	63	0	3440	0	148	41497	1184	1184	1466	25	162342	100	82240	80000	100	80000	80000	500	1910128	647564	1	0	41487	0	41513	41512	21425	3	21470	160100	200	80000	80000	200	160000	160000	41512	41513	1	1	80201	100	99	100	100	80000	80000	100	80000	0	80000	735	0	80000	0	0	0	80000	80000	0	5110	0	0	1	16	1	1	41510	80000	0	80000	80000	100	41513	41514	41513	41514	41513
160204	41512	311	0	0	0	0	96	0	3439	0	148	41497	1184	1184	1466	25	162342	100	82197	80000	100	80000	80000	500	1910080	648389	1	4	41488	0	41513	41512	21425	3	21470	160100	200	80000	80000	200	160000	160000	41513	41512	1	1	80201	100	99	100	100	80000	80000	100	80000	0	80000	735	0	80000	0	0	0	80000	80000	0	5110	4	4	1	16	1	1	41510	80000	0	80000	80000	100	41513	41514	41513	41514	41513
160204	41512	311	0	0	0	0	105	0	3441	0	148	41497	1184	1184	1466	25	162342	100	82240	80000	100	80000	80000	500	1910128	650338	1	4	41487	0	41512	41513	21426	3	21470	160100	200	80000	80000	200	160000	160000	41512	41513	1	1	80201	100	99	100	100	80000	80000	100	80000	0	80000	882	0	80000	0	0	0	80000	80000	0	5110	4	4	1	16	1	1	41509	80000	0	80000	80000	100	41514	41513	41514	41513	41514
160204	41513	311	0	0	0	0	96	0	2657	0	148	41497	1168	1184	1466	25	162342	100	82242	80000	100	80000	80000	500	1910128	650336	0	0	41488	0	41513	41512	21425	3	21470	160100	200	80000	80000	200	160000	160000	41512	41513	1	1	80201	100	99	100	100	80000	80000	100	80000	0	80000	882	0	80000	0	0	0	80000	80000	0	5110	0	0	1	16	1	1	41509	80000	0	80000	80000	100	41514	41513	41514	41513	41514
160204	41513	310	0	0	0	0	99	0	2242	0	148	41498	1184	1184	1320	25	162758	100	82266	80000	100	80000	80000	500	1910080	648389	1	4	41488	0	41513	41512	21425	29	21471	160100	200	80000	80000	200	160000	160000	41513	41512	1	1	80201	100	99	100	100	80000	80000	100	80000	0	80000	735	0	80000	0	0	0	80000	80000	0	5110	4	0	1	16	1	1	41510	80000	0	80000	80000	100	41513	41514	41513	41514	41513
160204	41512	311	0	0	0	0	0	0	3439	0	148	41497	1184	1184	1466	25	163276	100	82793	80000	100	80000	80000	500	1910128	650338	0	0	41490	0	41513	41512	21425	3	21470	160100	200	80000	80000	200	160000	160000	41512	41513	1	1	80201	100	99	100	100	80000	80000	100	80000	0	80000	882	0	80000	0	0	0	80060	80000	0	5110	4	0	1	16	1	1	41510	80000	0	80000	80000	100	41514	41513	41514	41513	41514
160204	41513	311	0	0	0	0	42	0	2240	0	148	41498	1184	1184	1320	25	163539	100	83439	80000	100	80000	80000	500	1910080	646733	0	0	41488	0	41513	41512	21426	3	21470	160100	200	80000	80000	200	160000	160000	41512	41513	1	1	80201	100	99	100	100	80000	80000	100	80000	0	80000	882	0	80000	0	0	0	80000	80000	0	5110	0	0	1	16	1	1	41509	80000	0	80000	80000	100	41514	41513	41514	41513	41514
160204	41513	311	0	0	0	0	117	0	2240	0	148	41498	1184	1184	1320	25	163539	100	83440	80000	100	80000	80000	500	1910080	646727	1	4	41488	0	41513	41512	21425	3	21471	160100	200	80000	80000	200	160000	160000	41513	41512	1	1	80201	100	99	100	100	80000	80000	100	80000	0	80000	735	0	80000	0	0	0	80000	80000	0	5110	4	0	1	16	1	1	41509	80000	0	80000	80000	100	41514	41513	41514	41513	41514
160204	41513	311	0	0	0	0	102	0	3439	0	148	41498	1184	1184	1320	25	163539	100	83439	80000	100	80000	80000	500	1910080	646733	0	0	41488	0	41512	41513	21426	3	21471	160100	200	80000	80000	200	160000	160000	41513	41512	1	1	80201	100	99	100	100	80000	80000	100	80000	0	80000	735	0	80060	0	0	0	80000	80000	0	5110	4	0	1	16	1	1	41510	80000	0	80000	80000	100	41514	41513	41514	41513	41514

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5189

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	1e	1f	37	3d	3f	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd store (99)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	cf	d2	d5	map dispatch bubble (d6)	d9	dd	fetch restart (de)	e0	st nt uop (e5)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160026	41523	311	1	1	1	0	14	1346	148	41508	1184	1184	1325	25	160624	10	80537	80000	10	80000	80000	50	1910608	647174	0	41495	41523	41523	21461	3	21500	160010	20	80000	80000	20	160000	160000	41523	41523	1	1	80021	10	9	10	10	80000	80000	10	80015	14	80000	882	0	80014	0	1	14	80000	14	80000	14	2	5020	0	6	16	0	5	5	41510	80000	80000	80000	10	41513	41514	41513	41514	41513
160024	41512	311	0	0	0	105	0	385	148	41498	1184	1184	1320	25	160482	10	80472	80000	10	80000	80000	50	1910080	641155	0	41487	41512	41513	21449	3	21493	160010	20	80144	80000	20	160000	160000	41513	41512	1	1	80021	10	9	10	10	80000	80000	10	80000	0	80000	735	0	80000	0	0	0	80000	0	80000	0	0	5020	0	7	16	0	4	6	41509	80000	80000	80000	10	41514	41513	41514	41513	41514
160024	41513	311	0	0	0	72	0	597	148	41497	1184	1184	1466	25	160395	10	80386	80000	10	80000	80000	50	1910128	641416	0	41487	41512	41513	21449	3	21493	160010	20	80000	80000	20	160000	160000	41513	41512	1	1	80021	10	9	10	10	80000	80000	10	80000	0	80000	735	0	80000	0	0	0	80000	0	80000	0	0	5020	0	4	16	0	6	6	41510	80000	80000	80000	10	41513	41514	41513	41514	41513
160024	41512	311	0	0	0	96	0	505	148	41498	1184	1184	1320	25	160482	10	80472	80000	10	80000	80000	50	1910080	641155	1	41487	41512	41513	21449	3	21492	160010	20	80000	80000	20	160000	160000	41512	41513	1	1	80021	10	9	10	10	80000	80000	10	80000	0	80000	882	0	80000	0	0	0	80000	14	80000	14	1	5020	0	5	16	0	4	6	41522	80014	80000	80000	10	41524	41521	41524	41524	41524
160024	41523	311	1	0	1	102	14	1351	148	41508	1184	1184	1466	25	160480	10	80505	80000	10	80000	80000	50	1910128	641792	0	41487	41512	41513	21449	3	21492	160010	20	80000	80000	20	160000	160000	41512	41513	1	1	80021	10	9	10	10	80000	80000	10	80000	0	80000	735	0	80000	0	0	0	80000	0	80000	0	0	5020	0	5	16	0	5	6	41509	80000	80000	80000	10	41514	41513	41514	41513	41514
160024	41513	311	0	0	0	24	264	597	148	41497	1184	1184	1466	25	160515	10	80504	80000	10	80000	80000	50	1910128	641791	0	41658	41512	41513	21449	3	21493	160010	20	80000	80000	20	160000	160536	41513	41512	1	1	80021	10	9	10	10	80000	80000	10	80000	0	80000	735	0	80000	1	0	15106	80000	0	80000	0	0	5020	0	6	16	0	6	6	41520	80014	80000	80000	10	41523	41524	41524	41521	41523
160024	41525	311	1	1	1	552	14	3249	148	41507	1184	1184	1473	25	160530	10	80489	80000	10	80000	80000	50	1910608	649150	0	41497	41523	41523	21456	3	21500	160010	20	80000	80000	20	160000	160000	41523	41523	1	1	80021	10	9	10	10	80000	80000	10	80015	15	80000	882	0	80014	1	3	14	80000	14	80000	14	1	5020	1	6	16	0	6	5	41520	80014	80000	80000	10	41524	41524	41526	41523	41524
160024	41520	311	1	0	0	312	14	4220	148	41508	1184	1184	1472	25	160528	10	83046	80000	10	80000	80000	50	1910512	645230	0	41498	41520	41520	21459	3	21493	160010	20	80000	80000	20	160000	160000	41513	41512	1	1	80021	10	9	10	10	80000	80000	10	80000	0	80000	735	0	80000	0	0	0	80000	0	80000	0	0	5020	0	5	16	0	5	4	41510	80000	80000	80000	10	41513	41514	41513	41514	41513
160024	41512	310	0	0	1	141	0	2828	148	41498	1184	1184	1320	25	160607	10	80597	80000	10	80000	80000	50	1910080	641515	0	41488	41512	41515	21449	3	21492	160010	20	80000	80000	20	160000	160000	41512	41513	1	1	80021	10	9	10	10	80000	80000	10	80000	0	80000	882	0	80000	0	0	0	80000	0	80000	0	0	5020	0	5	16	0	5	5	41509	80000	80000	80000	10	41514	41513	41514	41513	41514
160024	41513	311	0	0	0	111	0	2828	148	41498	1184	1184	1320	25	160607	10	80597	80000	10	80000	80000	50	1910080	641515	0	41487	41512	41513	21449	3	21493	160010	20	80000	80000	20	160000	160000	41513	41512	1	1	80021	10	9	10	10	80000	80000	10	80000	0	80000	735	0	80060	0	0	27	80000	0	80000	0	0	5020	0	5	16	0	4	5	41509	80000	80000	80000	10	41514	41513	41514	41513	41514

STNP (signed offset, D)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations