Firestorm: STNP (signed offset, S) measurements

Code:

  stnp s0, s1, [x6, #0x10]
  nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 7 nops): 2.000

Issues: 2.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 1.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	1e	1f	3a	3d	3f	46	49	51	schedule uop (52)	schedule simd uop (54)	schedule ldst uop (55)	dispatch simd uop (57)	dispatch ldst uop (58)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd store (99)	inst ldst (9b)	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	st nt uop (e5)	? ldst retires (ed)	? simd retires (ee)	f5	f6	f7	f8	fd
9006	1166	9	0	0	0	0	0	0	4	1151	13	13	25	2000	1000	1000	1000	1000	10875	8000	1145	1166	1166	3	24	2000	1000	1000	2000	2000	1166	1166	1	1	8001	1000	1000	1000	0	1000	0	1000	0	0	0	1000	0	1000	0	0	513	0	2	16	2	2	1163	1007	1000	1000	1167	1167	1167	1167	1167
9004	1166	9	1	1	1	0	7	0	4	1151	13	13	25	2000	1000	1000	1000	1000	10875	8000	1145	1166	1166	3	24	2000	1000	1000	2000	2000	1166	1166	1	1	8001	1000	1000	1008	8	1000	1	1007	0	1	7	1000	7	1000	7	0	513	0	2	16	2	2	1163	1007	1000	1000	1167	1167	1167	1167	1167
9004	1166	8	1	1	0	0	7	0	4	1151	13	13	25	2000	1000	1000	1000	1000	10875	8000	1145	1166	1166	3	24	2000	1000	1000	2000	2000	1166	1166	1	1	8001	1000	1000	1000	0	1000	0	1000	0	0	0	1000	0	1000	0	0	513	0	2	16	2	2	1163	1007	1000	1000	1167	1167	1167	1167	1167
9004	1166	9	1	0	0	0	7	0	4	1151	13	13	25	2000	1000	1000	1000	1000	10875	8000	1145	1166	1166	3	24	2000	1000	1000	2000	2000	1166	1166	1	1	8001	1000	1000	1000	0	1000	0	1000	0	0	0	1000	0	1000	0	0	513	0	2	16	2	2	1163	1007	1000	1000	1167	1167	1167	1167	1167
9004	1166	9	1	1	1	0	7	0	4	1151	13	13	25	2000	1000	1000	1000	1000	10875	8000	1145	1166	1166	3	24	2000	1000	1000	2000	2000	1166	1166	1	1	8001	1000	1000	1000	0	1000	0	1000	0	0	0	1000	0	1000	0	0	513	0	2	16	2	2	1163	1000	1000	1000	1167	1167	1167	1167	1167
9004	1166	9	0	0	0	0	0	0	4	1151	13	13	25	2000	1000	1000	1000	1000	10875	8000	1145	1166	1166	3	24	2000	1000	1000	2000	2000	1166	1166	1	1	8001	1000	1000	1000	0	1000	0	1000	0	0	0	1000	0	1000	0	0	513	0	2	16	2	2	1163	1000	1000	1000	1167	1167	1167	1167	1167
9004	1166	9	0	0	0	0	0	0	4	1151	13	13	25	2000	1000	1000	1000	1000	10875	8000	1145	1166	1166	3	24	2000	1000	1000	2000	2000	1166	1166	1	1	8001	1000	1000	1000	0	1000	0	1000	0	0	0	1000	0	1000	0	0	513	0	2	16	2	2	1163	1000	1000	1000	1167	1167	1167	1167	1167
9004	1166	9	0	0	0	0	0	0	4	1151	13	13	25	2000	1000	1000	1000	1000	10875	8000	1145	1166	1166	3	24	2000	1000	1000	2000	2000	1166	1166	1	1	8001	1000	1000	1007	8	1000	0	1007	0	1	7	1000	7	1000	7	2	513	0	2	16	2	2	1163	1000	1000	1000	1167	1167	1167	1167	1167
9004	1166	9	0	0	0	0	0	0	4	1151	13	13	25	2000	1000	1000	1000	1000	10875	8000	1145	1166	1166	3	24	2000	1000	1000	2000	2000	1166	1166	1	1	8001	1000	1000	1007	8	1000	0	1007	0	2	7	1000	7	1000	7	1	513	0	2	16	2	2	1163	1000	1000	1000	1167	1167	1167	1167	1167
9004	1166	9	0	0	0	0	0	0	4	1151	13	13	25	2000	1000	1000	1000	1000	10875	8000	1145	1166	1166	3	24	2000	1000	1000	2000	2000	1166	1166	1	1	8001	1000	1000	1000	0	1000	0	1000	0	0	0	1000	0	1000	0	0	513	0	2	16	2	2	1163	1007	1000	1000	1167	1167	1167	1167	1167

Count: 8

Code:

  stnp s0, s1, [x6, #0x10]
  stnp s0, s1, [x6, #0x10]
  stnp s0, s1, [x6, #0x10]
  stnp s0, s1, [x6, #0x10]
  stnp s0, s1, [x6, #0x10]
  stnp s0, s1, [x6, #0x10]
  stnp s0, s1, [x6, #0x10]
  stnp s0, s1, [x6, #0x10]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5189

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	19	1e	1f	37	3d	3f	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd store (99)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	st nt uop (e5)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160206	41521	311	1	0	1	1	654	14	541	148	41508	1184	1184	1325	25	160729	100	80629	80000	100	80000	80000	500	1910608	648804	1	41495	41523	41523	21434	3	21487	160100	200	80000	80000	200	160000	160000	41520	41520	1	1	80201	100	99	100	100	80000	80000	100	80015	14	80000	882	0	80014	0	1	14	80000	14	80000	14	0	5110	1	16	1	1	41520	80014	80000	80000	100	41524	41524	41521	41524	41524
160204	41523	310	1	0	0	0	0	14	3939	148	41508	1184	1184	1473	25	162850	100	83003	80000	100	80000	80000	500	1910464	649883	1	41498	41520	41520	21436	3	21483	160100	200	80000	80000	200	160000	160000	41523	41523	1	1	80201	100	99	100	100	80000	80000	100	80000	0	80000	735	0	80000	0	0	0	80000	0	80000	0	0	5110	1	16	1	1	41509	80000	80000	80000	100	41513	41513	41513	41513	41513
160204	41512	311	0	0	0	0	0	0	3543	148	41497	1184	1184	1466	25	162926	100	82826	80000	100	80000	80000	500	1910080	648489	1	41488	41513	41513	21426	3	21487	160100	200	80000	80000	200	160000	160000	41512	41512	1	1	80201	100	99	100	100	80000	80000	100	80000	0	80000	882	0	80000	0	0	0	80000	0	80000	0	0	5110	1	16	1	1	41510	80000	80000	80000	100	41514	41514	41514	41514	41514
160204	41513	310	0	0	0	0	0	0	2826	148	41497	1184	1184	1466	25	162926	100	82826	80000	100	80000	80000	500	1910080	648489	1	41488	41513	41513	21426	23	21487	160100	200	80000	80000	200	160000	160000	41512	41512	1	1	80201	100	99	100	100	80000	80000	100	80000	0	80000	735	0	80000	0	0	0	80000	0	80000	0	0	5110	1	16	1	1	41509	80000	80000	80000	100	41513	41513	41513	41513	41513
160204	41512	310	0	0	0	0	0	0	2773	148	41498	1184	1184	1320	25	163629	100	80704	80000	100	80000	80000	500	1910128	648331	1	41488	41513	41513	21426	3	21479	160100	200	80000	80000	200	160000	160000	41512	41512	1	1	80201	100	99	100	100	80000	80000	100	80000	0	80000	882	1	80000	0	0	0	80000	0	80000	0	0	5110	1	16	1	1	41510	80000	80000	80000	100	41513	41513	41513	41513	41513
160204	41512	311	0	0	0	0	0	0	2773	148	41497	1184	1184	1466	25	162843	100	82827	80000	100	80000	80000	500	1910080	650653	0	41487	41512	41512	21425	3	21495	160100	200	80000	80000	200	160000	160000	41512	41512	1	1	80201	100	99	100	100	80000	80000	100	80000	0	80000	882	0	80000	0	0	0	80000	0	80000	0	0	5110	1	16	1	1	41510	80000	80000	80000	100	41514	41514	41514	41514	41514
160204	41513	311	0	0	0	0	0	0	705	148	41497	1184	1184	1466	25	163486	100	83386	80000	100	80000	80000	500	1910080	650175	1	41487	41512	41512	21425	3	21495	160100	200	80000	80000	200	160000	160000	41513	41513	1	1	80201	100	99	100	100	80000	80000	100	80000	0	80000	735	0	80000	3	0	0	80000	0	80000	0	0	5110	1	16	1	1	41509	80000	80000	80000	100	41513	41513	41513	41513	41513
160204	41512	311	0	0	0	0	0	0	2773	148	41498	1184	1184	1320	25	163629	100	83529	80000	100	80000	80000	500	1910128	648530	1	41488	41513	41512	21425	3	21482	160100	200	80000	80000	200	160000	160000	41512	41512	1	1	80201	100	99	100	100	80000	80000	100	80000	0	80000	882	0	80000	1	0	0	80000	0	80000	0	0	5110	1	16	1	1	41509	80000	80000	80000	100	41513	41513	41513	41513	41513
160204	41512	311	0	0	0	0	0	0	2765	148	41498	1184	1184	1320	25	162873	100	82773	80000	100	80000	80000	500	1910128	650046	1	41488	41513	41513	21426	3	21483	160100	200	80000	80000	200	160000	160000	41513	41513	1	1	80201	100	99	100	100	80000	80000	100	80000	0	80000	882	0	80000	0	0	0	80000	0	80000	0	0	5110	1	16	1	1	41510	80000	80000	80000	100	41514	41514	41514	41514	41514
160204	41513	311	0	0	0	0	0	0	3382	148	41497	1184	1184	1325	25	163404	100	83302	80000	100	80000	80000	500	1910536	650691	1	41498	41522	41522	21436	3	21485	160100	200	80000	80000	200	160000	160000	41526	41526	1	1	80201	100	99	100	100	80000	80000	100	80016	15	80000	882	2	80014	0	0	14	80000	14	80000	14	1	5110	1	16	1	1	41519	80014	80000	80000	100	41524	41521	41524	41524	41522

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5189

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss instruction (0a)	18	19	1e	37	3d	3f	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	61	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd store (99)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d cache miss st (a2)	a4	st unit uop (a7)	l1d cache writeback (a8)	ac	af	l1d cache miss st nonspec (c0)	c2	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	st nt uop (e5)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160026	41523	311	0	0	0	0	2728	148	41497	1184	1184	1466	25	162232	10	82740	80000	10	80000	80000	50	1910080	646666	0	0	41488	41513	41512	21448	3	21496	160010	20	80000	80000	20	160000	160000	41512	41513	1	1	80021	10	9	10	10	80000	80000	10	80000	80000	882	80000	0	0	80000	80000	0	5020	5	0	0	12	16	9	6	41510	80000	80000	80000	10	41513	41514	41513	41514	41513
160024	41512	311	0	0	0	0	3072	148	41498	1184	1184	1320	25	161118	10	81490	80000	10	80000	80000	50	1910080	650644	0	0	41487	41512	41513	21449	3	21493	160010	20	80000	80000	20	160000	160000	41513	41512	1	1	80021	10	9	10	10	80000	80000	10	80000	80000	882	80000	7	0	80000	80000	0	5020	5	3	0	9	16	9	7	41510	80000	80000	80000	10	41514	41513	41514	41513	41514
160024	41513	311	0	0	0	0	2113	148	41497	1184	1184	1466	25	163244	10	83234	80000	10	80000	80000	50	1910128	646340	0	0	41487	41512	41513	21449	3	21492	160010	20	80000	80000	20	160000	160000	41512	41513	1	1	80021	10	9	10	10	80000	80000	10	80000	80000	882	80000	0	0	80000	80000	0	5020	5	3	0	9	16	9	7	41509	80000	80000	80000	10	41514	41513	41514	41513	41514
160024	41513	311	0	0	0	0	3234	148	41498	1184	1184	1320	25	162123	10	82113	80000	10	80000	80000	50	1910080	649703	0	0	41488	41513	41512	21448	3	21493	160010	20	80000	80000	20	160000	160000	41513	41513	1	1	80021	10	9	10	10	80000	80000	10	80000	80000	882	80000	0	0	80000	80000	0	5020	0	0	0	12	16	7	9	41509	80000	80000	80000	10	41513	41514	41513	41514	41513
160024	41512	311	0	0	0	0	2690	148	41497	1184	1184	1320	25	162118	10	82113	80000	10	80000	80000	50	1910080	648381	0	0	41488	41513	41512	21448	3	21503	160010	20	80000	80000	20	160000	160000	41513	41512	1	1	80021	10	9	10	10	80000	80000	10	80000	80000	735	80000	0	0	80000	80000	0	5020	5	4	0	9	16	7	8	41509	80000	80000	80000	10	41514	41513	41514	41513	41514
160024	41513	311	0	0	0	0	2113	148	41497	1184	1184	1466	25	163244	10	83234	80000	10	80000	80000	50	1910128	646340	0	0	41487	41512	41513	21449	3	21503	160010	20	80000	80000	20	160000	160000	41513	41512	1	1	80021	10	9	10	10	80000	80000	10	80000	80000	735	80000	0	0	80000	80000	0	5020	0	0	0	10	16	7	9	41510	80000	80000	80000	10	41513	41513	41514	41513	41514
160024	41513	311	0	0	0	0	3234	148	41498	1184	1184	1320	25	163087	10	82108	80000	10	80000	80000	50	1915984	646182	1	0	41487	41513	41512	21448	3	21500	160010	20	80000	80000	20	160000	160000	41513	41512	1	1	80021	10	9	10	10	80000	80000	10	80000	80000	735	80000	0	0	80000	80000	0	5020	5	4	0	11	16	13	9	41509	80000	80000	80000	10	41514	41513	41514	41513	41514
160024	41513	311	0	0	0	0	2113	148	41497	1184	1184	1466	25	163244	10	83234	80000	10	80000	80000	50	1910128	646340	1	0	41487	41512	41513	21449	3	21493	160010	20	80000	80000	20	160000	160000	41513	41512	1	1	80021	10	9	10	10	80000	80000	10	80000	80000	735	80000	0	0	80000	80000	0	5020	0	0	0	10	16	10	13	41510	80000	80000	80000	10	41513	41514	41513	41514	41513
160024	41512	311	0	0	0	0	3234	148	41498	1184	1184	1320	25	162123	10	82113	80000	10	80000	80000	50	1910080	649703	1	0	41488	41513	41512	21448	3	21492	160010	20	80000	80000	20	160000	160000	41512	41513	1	1	80021	10	9	10	10	80000	80000	10	80000	80000	882	80000	0	0	80000	80000	0	5020	0	0	0	9	16	10	11	41510	80000	80000	80000	10	41513	41514	41513	41514	41513
160024	41512	311	0	0	0	0	2108	148	41497	1184	1184	1466	25	163244	10	83234	80000	10	80000	80000	50	1910128	648076	0	0	41488	41513	41512	21448	3	21493	160010	20	80000	80000	20	160000	160000	41513	41512	1	1	80021	10	9	10	10	80000	80000	10	80000	80000	735	80000	0	0	80000	80000	0	5020	5	0	0	9	16	10	10	41509	80000	80000	80000	10	41514	41513	41514	41513	41514

STNP (signed offset, S)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations