Firestorm: STP (D) measurements

Code:

  stp d0, d1, [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 7 nops): 2.000

Issues: 2.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 1.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	19	1e	1f	22	24	3a	3f	46	49	51	schedule uop (52)	schedule simd uop (54)	schedule ldst uop (55)	dispatch simd uop (57)	dispatch ldst uop (58)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd store (99)	inst ldst (9b)	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	? simd retires (ee)	f5	f6	f7	f8	fd
9006	1166	9	0	0	0	0	0	0	1	0	0	1	1151	10	0	25	2000	1000	1000	1000	1000	10875	8000	1	1145	1166	1166	3	24	2000	1000	1000	2000	2000	1166	1166	1	1	8001	1000	1000	1008	9	23	0	1007	0	0	7	1000	8	23	7	0	512	5	16	2	1	1163	1000	1000	1167	1167	1167	1167	1167
9004	1166	9	1	0	1	1	0	0	7	1	0	0	1151	0	0	25	2000	1000	1000	1000	1000	10875	8000	1	1145	1166	1166	3	24	2000	1000	1000	2000	2000	1166	1166	1	1	8001	1000	1000	1000	0	0	0	1000	0	0	0	1000	0	15	0	0	513	1	16	1	1	1163	1000	1000	1167	1167	1167	1167	1167
9004	1166	8	0	0	0	0	0	0	1	1	0	1	1151	10	10	25	2000	1000	1000	1000	1000	10878	8000	1	1145	1166	1166	3	24	2000	1000	1000	2000	2000	1166	1166	1	1	8001	1000	1000	1000	0	0	0	1000	0	0	0	1000	0	15	0	0	512	1	16	1	1	1163	1000	1000	1167	1167	1167	1167	1167
9004	1166	9	0	0	0	0	0	0	1	0	0	0	1151	8	8	25	2000	1000	1000	1000	1000	10875	8000	0	1145	1166	1166	3	24	2000	1000	1000	2000	2000	1166	1166	1	1	8001	1000	1000	1000	0	15	0	1000	0	0	0	1000	0	15	0	0	513	2	16	2	2	1163	1000	1000	1167	1167	1167	1167	1167
9004	1166	9	0	0	0	0	0	0	1	1	0	0	1151	8	8	25	2000	1000	1000	1000	1000	10875	8000	0	1145	1166	1166	3	24	2000	1000	1000	2000	2000	1166	1166	1	1	8001	1000	1000	1000	0	15	0	1000	1	0	0	1000	0	15	0	0	513	2	16	1	1	1163	1000	1000	1167	1167	1167	1167	1167
9004	1166	9	1	0	1	1	0	0	9	1	0	1	1151	10	10	25	2000	1000	1000	1000	1000	10878	8000	1	1145	1166	1166	3	24	2000	1000	1000	2000	2000	1166	1166	1	1	8001	1000	1000	1007	8	0	1	1008	0	0	8	1000	8	23	7	0	512	2	16	1	1	1163	1000	1000	1167	1167	1167	1167	1167
9004	1166	9	0	0	0	0	0	0	1	0	0	0	1151	8	8	25	2000	1000	1000	1000	1000	10875	8000	1	1145	1166	1166	3	24	2000	1000	1000	2000	2000	1166	1166	1	1	8001	1000	1000	1008	7	23	2	1007	0	0	7	1001	8	23	7	2	512	2	16	2	1	1163	1000	1000	1167	1167	1167	1167	1167
9004	1166	8	0	0	0	0	0	0	1	1	0	0	1151	8	8	25	2000	1000	1000	1000	1000	10875	8000	0	1145	1166	1166	3	24	2000	1000	1000	2000	2000	1166	1166	1	1	8001	1000	1000	1000	0	15	0	1000	1	0	0	1000	0	0	0	0	512	2	16	1	1	1163	1000	1000	1167	1167	1167	1167	1167
9004	1166	9	0	0	0	0	0	0	1	0	0	0	1151	8	0	25	2000	1000	1000	1000	1000	10875	8000	1	1145	1166	1166	3	24	2000	1000	1000	2000	2000	1166	1166	1	1	8001	1000	1000	1000	0	15	0	1000	0	0	0	1000	0	0	0	0	512	1	16	1	1	1163	1000	1000	1167	1167	1167	1167	1167
9004	1166	8	0	0	0	0	0	0	1	1	0	1	1151	10	0	25	2000	1000	1000	1000	1000	10878	8000	0	1145	1166	1166	3	24	2000	1000	1000	2000	2000	1166	1166	1	1	8001	1000	1000	1008	7	23	0	1008	0	0	7	1000	7	23	7	1	512	1	16	1	2	1163	1000	1000	1167	1167	1167	1167	1167

Count: 8

Code:

  stp d0, d1, [x6]
  stp d0, d1, [x6]
  stp d0, d1, [x6]
  stp d0, d1, [x6]
  stp d0, d1, [x6]
  stp d0, d1, [x6]
  stp d0, d1, [x6]
  stp d0, d1, [x6]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5006

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	22	23	37	3a	3f	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	rob full (74)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd store (99)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160206	40061	300	1	0	0	1	0	0	0	15	0	0	2810	1	40036	16	16	3	25	161372	100	81891	80000	100	80000	80000	500	1839784	648488	0	40036	40050	40059	19971	0	3	20016	160100	200	80000	80000	200	160000	160000	40059	40049	1	1	80201	100	99	100	100	80000	80000	100	80015	15	0	3	0	80016	1	1	18	80002	14	36	14	1	0	5110	2	16	1	1	40046	0	80000	80000	100	40054	40061	40053	40049	40052
160204	40050	300	1	1	0	0	0	0	0	19	0	0	1892	1	40034	16	16	0	25	163415	100	82188	80000	100	80000	80000	500	1839904	646749	1	40035	40051	40058	19972	0	3	20018	160100	200	80000	80000	200	160000	160000	40053	40050	1	1	80201	100	99	100	100	80000	80000	100	80014	14	36	0	0	80016	0	1	19	80002	16	36	14	0	0	5110	1	16	1	1	40047	0	80000	80000	100	40059	40061	40059	40051	40053
160204	40497	300	1	1	0	1	0	0	0	19	1	0	2189	1	40036	16	16	5	25	161817	100	82817	80000	100	80000	80000	500	1840288	646704	1	40033	40049	40050	19963	0	3	20017	160100	200	80000	80000	200	160000	160000	40058	40050	1	1	80201	100	99	100	100	80000	80000	100	80017	16	0	0	0	80016	0	2	14	80002	16	0	14	2	0	5110	1	16	1	1	40047	0	80000	80000	100	40051	40051	40051	40052	40052
160204	40060	300	1	0	0	1	0	0	0	18	0	0	2418	1	40043	16	16	140	25	161766	100	81238	80000	100	80232	80000	500	1839904	646462	0	40025	40048	40050	19965	0	3	20008	160100	200	80000	80000	200	160000	160000	40061	40050	1	1	80201	100	99	100	100	80000	80000	100	80016	15	36	1	1	80014	1	0	18	80000	16	0	14	0	0	5110	1	16	1	1	40048	0	80000	80000	100	40053	40062	40051	40062	40053
160204	40058	300	1	0	0	1	0	0	0	21	0	0	2777	1	40034	16	0	5	25	162510	100	82280	80000	100	80000	80000	500	1839952	647273	0	40025	40058	40061	19974	0	3	20010	160100	200	80136	80000	200	160000	160000	40058	40050	1	1	80201	100	99	100	100	80000	80000	100	80014	15	36	0	0	80014	0	0	18	80002	16	0	14	0	0	5110	1	16	1	1	40048	0	80000	80000	100	40051	40062	40051	40061	40053
160204	40048	299	1	0	0	1	0	0	0	19	0	0	2254	1	40042	0	16	0	25	162413	100	82419	80000	100	80000	80000	500	1840264	648010	0	40224	40050	40053	20118	0	3	20016	160100	200	80000	80000	200	160000	160000	40060	40060	1	1	80201	100	99	100	100	80000	80000	100	80014	14	36	0	1	80016	0	0	18	80000	16	36	14	1	0	5110	1	16	1	1	40055	0	80000	80000	100	40053	40051	40053	40060	40050
160204	40059	300	1	1	0	1	0	0	0	14	0	0	1729	1	40032	0	14	5	25	161759	100	82280	80000	100	80000	80000	500	1839952	646604	0	40028	40050	40058	19972	0	3	20008	160100	200	80000	80000	200	160000	160000	40058	40057	1	1	80201	100	99	100	100	80000	80000	100	80015	15	0	0	0	80014	1	1	16	80002	14	36	14	2	0	5110	1	16	1	1	40046	0	80000	80000	100	40051	40050	40053	40062	40051
160204	40059	300	1	0	0	1	0	0	0	20	0	0	2468	1	40038	16	0	6	25	161846	100	82419	80000	100	80000	80000	500	1839904	646827	0	40025	40050	40058	19972	0	3	20008	160100	200	80000	80000	200	160000	160000	40051	40050	1	1	80201	100	99	100	100	80000	80000	100	80014	15	36	0	1	80016	0	1	18	80002	16	36	14	2	0	5110	1	16	1	1	40047	0	80000	80000	100	40060	40053	40059	40053	40059
160204	40048	300	1	0	0	0	0	0	0	15	0	0	2316	1	40043	16	14	5	25	162378	100	82410	80000	100	80000	80000	500	1839952	644257	0	40025	40050	40061	19961	0	3	20019	160100	200	80000	80000	200	160000	160000	40053	40059	1	1	80201	100	99	100	100	80000	80000	100	80015	15	36	0	1	80016	0	1	14	80000	14	36	14	0	0	5110	1	16	1	1	40047	0	80000	80000	100	40053	40060	40051	40050	40052
160204	40058	300	1	1	0	1	0	0	6	20	1	0	2188	1	40045	16	16	0	25	161410	100	82054	80000	100	80000	80000	500	1840312	643848	0	40027	40059	40060	19971	0	3	20010	160100	200	80000	80000	200	160000	160000	40058	40061	1	1	80201	100	99	100	100	80000	80000	100	80015	15	0	0	0	80016	0	2	2258	80060	14	0	14	0	0	5110	1	16	1	1	40049	0	80000	80000	100	40059	40049	40059	40050	40052

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5007

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	22	23	24	37	3a	3f	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	61	69	6d	6e	map stall dispatch (70)	rob full (74)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd store (99)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	branch mispred nonspec (cb)	cf	d0	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160026	40061	300	0	1	1	0	1	0	0	0	19	0	0	0	2253	1	40044	16	0	4	31	164834	10	81655	80000	10	80000	80116	50	1839760	644624	0	0	40026	40061	40052	19985	0	3	20038	160010	20	80000	80240	20	160000	160000	40061	40053	1	1	80021	10	9	10	10	80000	80000	10	80014	15	36	0	1	80016	0	1	18	80002	16	36	14	2	0	5020	0	0	6	16	6	5	40048	0	80000	80000	10	40051	40059	40059	40051	40060
160024	40050	300	0	1	2	0	1	0	0	0	14	0	0	0	1973	1	40045	0	16	1	25	161265	10	82429	80000	10	80000	80000	50	1840024	649715	0	0	40033	40049	40051	19986	0	3	20028	160010	20	80000	80000	20	160000	160000	40067	40051	1	1	80021	10	9	10	10	80000	80000	10	80014	14	36	0	1	80014	0	1	18	80002	14	36	14	1	0	5020	0	0	5	16	6	5	40048	0	80000	80000	10	40049	40059	40051	40058	40053
160024	40047	300	0	1	0	0	1	0	0	0	14	0	0	0	2932	1	40046	16	16	3	25	163194	10	82062	80000	10	80000	80000	50	1839904	645740	1	0	40025	40050	40052	19988	0	3	20028	160010	20	80000	80000	20	160000	160000	40058	40060	1	1	80021	10	9	10	10	80000	80000	10	80014	14	36	0	1	80016	0	0	18	80000	16	0	14	1	0	5020	0	0	5	16	5	5	40047	0	80000	80000	10	40059	40051	40059	40053	40051
160024	40058	300	0	1	1	0	0	0	0	0	14	0	0	0	2474	1	40036	16	0	0	25	162334	10	84503	80000	10	80000	80000	50	1839904	650548	1	0	40026	40058	40048	19983	0	3	20039	160010	20	80000	80000	20	160000	160000	40050	40062	1	1	80021	10	9	10	10	80000	80000	10	80016	16	0	0	1	80016	0	0	20	80002	16	36	14	1	0	5020	0	0	6	16	6	5	40055	0	80000	80000	10	40051	40051	40051	40053	40059
160024	40050	300	0	1	1	0	0	0	0	0	14	1	0	0	3204	1	40035	0	16	0	25	164474	10	80783	80000	10	80000	80000	50	1839904	647162	0	0	40032	40053	40058	19986	0	3	20028	160010	20	80000	80000	20	160000	160000	40058	40051	1	1	80021	10	9	10	10	80000	80000	10	80015	15	35	0	1	80016	1	0	24	80060	16	36	14	0	0	5020	0	0	6	16	6	6	40047	0	80000	80000	10	40051	40049	40059	40050	40053
160024	40058	300	0	1	1	0	1	0	0	0	14	0	0	0	3970	1	40046	0	0	3	25	162161	10	83054	80000	10	80000	80000	50	1840312	649595	0	0	40027	40058	40061	19996	0	3	20030	160010	20	80000	80000	20	160000	160000	40050	40059	1	1	80021	10	9	10	10	80000	80000	10	80014	14	36	0	0	80014	0	0	14	80000	16	36	14	2	0	5020	0	0	6	16	6	5	40055	0	80000	80000	10	40051	40053	40060	40052	40060
160024	40058	300	0	1	0	0	0	0	0	0	14	1	0	0	523	1	40035	16	0	0	25	162673	10	82587	80000	10	80000	80000	50	1839784	650979	0	0	40025	40058	40050	19986	0	3	20039	160010	20	80000	80000	20	160000	160000	40052	40062	1	1	80021	10	9	10	10	80000	80000	10	80014	14	36	0	0	80016	0	1	14	80002	14	0	14	1	0	5020	0	0	6	16	6	5	40045	0	80000	80000	10	40061	40060	40052	40059	40052
160024	40058	300	0	1	1	0	1	0	0	0	17	1	0	0	2492	1	40035	0	0	2	25	162476	10	83449	80000	10	80000	80000	50	1840408	650935	0	0	40028	40049	40050	19984	0	3	20038	160010	20	80000	80000	20	160000	160000	40052	40064	1	1	80021	10	9	10	10	80000	80000	10	80016	15	0	0	0	80016	0	0	14	80002	16	36	14	0	0	5020	0	0	6	16	5	5	40056	0	80000	80000	10	40051	40049	40059	40051	40059
160024	40050	300	0	1	0	0	1	0	0	6	20	0	0	0	2015	1	40043	0	16	0	25	163160	10	81385	80000	10	80000	80000	50	1840312	648952	0	0	40035	40058	40058	19986	0	3	20032	160010	20	80000	80000	20	160000	160000	40061	40054	1	1	80021	10	9	10	10	80000	80000	10	80014	14	36	0	0	80014	0	1	14	80002	16	36	14	2	0	5020	0	0	7	16	5	5	40432	0	80000	80000	10	40053	40062	40051	40049	40059
160024	40050	300	0	1	1	0	1	0	0	102	14	0	0	0	3706	1	40035	16	16	5	25	163305	10	82968	80000	10	80000	80117	50	1840384	648910	1	0	40033	40052	40059	19986	0	3	20027	160010	20	80000	80000	20	160000	160000	40059	40059	1	1	80021	10	9	10	10	80000	80000	10	80016	15	0	0	0	80014	1	0	18	80002	16	36	14	0	0	5020	0	0	4	16	5	6	40049	0	80000	80000	10	40059	40051	40058	40052	40058

STP (D)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations